JPH07312097A - Sram and its test method - Google Patents

Abstract

PURPOSE:To obtain a SRAM and its test method which can detect existence of a minute leak current. CONSTITUTION:A semiconductor switch 34 which can be turned off at the time of a test is inserted between a power supply line Vdd and TFT 16, 18 of a memory cell 10. Data is written turning on the switch 34, after the switch 34 is turned off and a fixed time elapses, further, the switch 34 is turned on. After that, data is read out, a memory cell 10 in which written data is reversed is discriminated as a defect. It is performed for '1' and '0' of written data respectively. Also, leaving the switch 34 an off state, after data is written and a fixed time elapses, data is read out, a memory cell in which read-out of data cannot be performed can also be discriminated as a defect. Especially, when it is utilized for a product of an initial stage, a large merit is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SRAM and a method of testing the same, and more particularly, an S having a TFT load element.
The present invention relates to an SRAM capable of detecting the presence / absence of a leak of a predetermined value or more with respect to a minute leak current from a storage node of a memory cell in a RAM and a test method thereof.

[0002]

2. Description of the Related Art PMOS type thin film transistor (TFT)
SRAMs that employ memory cells having a load element as a load element tend to be used frequently in recent years because their miniaturization and power saving are particularly easy. However, in the TFT load type memory cell, since the TFT current is extremely small, it is difficult to detect a leak in the gate oxide film or the like of the drive transistor.

FIG. 2 is a circuit diagram showing the structure of a TFT load type memory cell. The memory cell 10 includes a pair of N-channel type drive transistors 12 and 14, a pair of P-channel type TFTs 16 and 18 respectively constituting load elements of the pair of N-channel type drive transistors 12 and 14, and the drive transistors 12 and 14. Pair of storage nodes 20, 2 consisting of the connection point between the drain of the TFT and the drains of the TFTs 16, 18.
2 is composed of a pair of word transistors 28 and 30 respectively connected to corresponding bit lines 24 and 26 outside the cell. Each one drive transistor 12, 14 and TF
The CMOS composed of T16 and T18 is inserted and connected between the power supply line Vdd and the power supply line VSS.

Consider a case where a leak 32 occurs in the gate oxide film at the gate portion of the drive transistor 14 connected to the storage node 20, as shown in FIG. When the data “1” is written in the memory cell and the storage node 20 is at the H level, the leak current I due to the leak 32 is generated.
_L is supplied from the Vdd power supply line via the TFT 16 of the other CMOS. If the leak current I _L has a current value on the order of nanoamperes, the TFT 16 has a sufficient ability to flow a current on that order. Therefore, in this case, since the written data can be sufficiently retained, the existence of the leak 32 does not cause any particular problem. If the leak current I _L is, for example, about 100 μA, SRA
The presence of leak current can be detected by measuring the standby current and the like during the test when M is completed. Therefore, in this case, since the defective SRAM can be eliminated, it does not cause a big problem.

[0005]

However, in the conventional SRAM of the above-mentioned type, when the leakage current in the gate oxide film is, for example, on the order of several to several tens of .mu.A, whether it is a good product or a defective product depends on the above-mentioned measurement of the standby current. Is extremely difficult to judge. In this case, in the functional test, the transistor characteristics change due to the influence of temperature conditions or hot carriers, and it is determined that the product is a good product or a defective product depending on the conditions at that time. Therefore, there is an example in which the SRAM mounted on the circuit after being judged as a non-defective product at the time of the function test is actually a defective product, causing erroneous data to cause a failure.

In view of the above, the present invention is an SRAM having a TFT load type memory cell, and even for a minute leak current from a storage node, it is possible to easily determine the presence or absence of a leak of a predetermined value or more. It is an object of the present invention to provide an SRAM and a method for testing the same, which enables accurate elimination of

[0007]

In order to achieve the above object, an SRAM according to the present invention is an SRAM including a memory cell having a pair of drive transistors each having a P-channel thin film transistor as a load element. A switch is inserted between and so that the switch can be turned on / off from the outside.

A first SRAM testing method according to the present invention is a method for testing the SRAM according to the present invention, wherein a switch is turned on to write data in a memory cell, and after the writing, the switch is turned off. Further, the switch is turned on again after a certain period of time, and the data in the memory cell is judged.

Further, a second SRAM testing method according to the present invention is a method for testing the SRAM according to the present invention, wherein a switch is turned off, data is written in a memory cell, and a certain time has elapsed after the writing. It is characterized in that the data of the memory cell is determined later.

[0010]

In the SRAM according to the present invention, the first aspect of the present invention is provided.
In the SRAM test method of 1), the potential of the storage node is at an H level due to a leak of a predetermined value or more within a certain time after the switch is turned on and then the switch is turned off after writing predetermined data to the memory cell. When the switch is turned on again, the data written in the memory cell is inverted due to the potential decrease. Therefore, by detecting the presence or absence of data inversion,
It is possible to detect a leak current of a predetermined value or more.

Further, in the SRAM according to the present invention, in the second SRAM test method according to the present invention, data is written in the memory cell with the switch kept off, and a predetermined value or more from the storage node which becomes H level is exceeded. If the data cannot be held due to the leak current, the data cannot be read even if the data is read after the elapse of a predetermined time. Therefore, it becomes possible to detect a leak current of a predetermined value or more depending on whether or not the data can be read.

[0012]

The present invention will be described in more detail with reference to the drawings. FIG. 1 shows a circuit configuration of an SRAM memory cell according to an embodiment of the present invention. The internal structure of the memory cell is the same as that of the memory cell in the conventional SRAM described with reference to FIG. That is, S of this embodiment
The memory cell in the RAM is composed of a pair of N-channel type drive transistors 12 and 14, a pair of P-channel type TFTs 16 and 18 constituting load elements of the pair of N-channel type drive transistors 12 and 14, and a drive transistor 12, A pair of word transistors 28 and 30 respectively connecting a pair of storage nodes 20 and 22 composed of respective connection points between the drain of 14 and the drains of TFTs 16 and 18 to corresponding bit lines 24 and 26 outside the cell. .
Each one drive transistor 12, 14 and TFT 16,
The CMOSs each configured by 18 are inserted and connected between the high potential power supply line Vdd and the low potential power supply line VSS via the switch 34.

The switch 34 inserted between the Vdd power supply line and the TFTs 16 and 18 is formed as a semiconductor switch made of, for example, PMOSFET. The semiconductor switch 34 may be controlled as long as the semiconductor switch 34 can be turned off at the time of testing the SRAM. The semiconductor switch 34 may be provided for each memory cell 10, or
It may be provided for each of a plurality of memory cell groups. Alternatively, they may be collectively provided on the Vdd line. In the SRAM of the present embodiment, the pass / fail judgment can be easily made by performing a simple test in which the semiconductor switch 34 is turned on or off to write and read data.

The SRAM of the above embodiment is tested as follows by the SRAM testing method of one embodiment of the method of the present invention. First, with the semiconductor switch 34 turned on, predetermined data is written in the memory cell 10 to be evaluated according to a normal SRAM operating method. Here, for example, by writing the data “1”, the storage node 2
0 becomes H level, and the storage node 22 becomes L level. Then, the semiconductor switch 34 is turned off to stand by. After the elapse of a predetermined time, the semiconductor switch 34 is turned on again to read the written data, and it is detected whether or not the data is normally stored. Data writing and reading are performed for each of data "1" and "0". Also, if desired, the off-time may be changed for testing.

For example, in the drive transistor 14, when the leak 32 exists due to insufficient film thickness of the gate oxide film and the like, when the semiconductor switch 34 is turned off, the potential becomes H level by writing the data "1". No current is supplied to the existing storage node 20, and the potential thereof decreases according to the magnitude of the leak current I _L. Therefore, when the leakage current I _L from the storage node 20 is greater than the predetermined value, at the time of turning on the switch 34 again, the data "1" is to be inverted from the written state "0" side Transition.

Therefore, the presence / absence of the above-mentioned data inversion makes it possible to determine the presence / absence of a leakage current of a predetermined value or more even for a minute leakage current I _L. In this embodiment, for example, 1
If there is a leakage current of μA or more, a predetermined time sufficient for data inversion is set, and a memory cell in which data inversion does not occur is regarded as a good product. As a result, it is possible to eliminate even an SRAM having a minute leak that may be good or bad depending on the test condition, so that it is possible to avoid the occurrence of a failure due to the leak in the circuit after the SRAM is mounted. I can.

Next, the SRA of the second embodiment of the method of the present invention.
The test method for M will be described. In this method, in the memory cell 10 of FIG. 1, the semiconductor switch 34 is turned off during this test. Data is written to the memory cell 10 and data is read after a predetermined time has elapsed. The write data is performed for each of "1" and "0". Here, a memory cell from which data can be normally read is determined to be a good product, and a memory cell from which data cannot be normally read is determined to be a defective product. As described above, in the case of the method of this embodiment, if the leak current from the storage node at the H level is larger than the predetermined value, the written data cannot be read. As the predetermined time, for example, as in the case of the first embodiment, the time during which data cannot be read if there is a leak current of 1 μA or more is set.

According to the test method of each of the above-mentioned embodiments, it is possible to detect the presence or absence of a leakage of a predetermined value or more even for a minute leakage current. Therefore, conventionally, there is a minute leakage current which is difficult to judge pass / fail. Even for a memory cell, that is, a memory cell having a defect whose test result may be good or bad depending on the condition at the time of testing, the defect can be easily detected, so that the correct pass / fail determination of the SRAM can be easily performed.

Particularly, the SRAM of the present invention and the test method thereof are useful for finding the optimum conditions of the production process of products in the early stage of production, for example, products in the trial production stage or sample shipping stage.

Although the present invention has been described based on its preferred embodiments, the SRAM and its testing method of the present invention are as follows.
It is not limited to the configuration of the above embodiment.

[0021]

As described above, the SRAM of the present invention
According to the above, a simple test facilitates the quality determination of a memory cell having a minute leak current, which was difficult to determine in the past, and a defective SRAM can be accurately excluded. Therefore, the present invention provides a circuit after the SRAM is mounted. The effect of providing an SRAM capable of suppressing the occurrence of defects is obtained.

Further, according to the first SRAM test method of the present invention, the switch is turned on to write data in the memory cell, the switch is turned off after the writing, and the switch is turned on again after a lapse of a certain time to turn on the memory cell. Since the data can be determined and the memory cell in which the inversion of the data has not occurred can be determined as a non-defective product, there is an effect that the accurate pass / fail determination of the SRAM can be easily performed.

Further, according to the second SRAM test method of the present invention, the switch is turned off to write the data in the memory cell, and after a lapse of a certain time after the writing, the data in the memory cell is judged and the data can be read. Since it is possible to determine that the memory cell is a non-defective product, similarly, there is an effect that the accurate pass / fail determination of the SRAM can be easily performed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an SRAM memory cell according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a conventional SRAM memory cell.

[Explanation of symbols]

 10 memory cells 12 and 14 drive transistors 16 and 18 TFTs 20 and 22 storage nodes 24 and 26 bit lines 28 and 30 word transistors 32 leaks 34 semiconductor switches

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 27/11 29/786 9056-4M H01L 29/78 311 C

Claims (3)

[Claims] 1. An SRAM having a memory cell having a pair of drive transistors each having a P-channel thin film transistor as a load element, wherein a switch is inserted between a power supply line and a thin film transistor, and the switch can be turned on / off from the outside. An SRAM characterized in that. 2. The method for testing the SRAM according to claim 1, wherein a switch is turned on to write data in the memory cell,
A test method for an SRAM, characterized in that the switch is turned off after the writing, and then the switch is turned on again after a lapse of a certain period of time to judge the data of the memory cell. 3. The method for testing the SRAM according to claim 1, wherein the switch is turned off, data is written in the memory cell, and data in the memory cell is judged after a certain time has elapsed after the writing. Characteristic SRAM test method.