JPH07311902A - Read circuit of mr head - Google Patents

Abstract

PURPOSE:To shorten a time while a circuit cannot be used in a read state by prohibiting a capacitor from discharging electric charges when data are written. CONSTITUTION:This circuit comprises one capacitor Cx connected in common to an emitter of one transistor Q02... and an emitter of the other transistor Q03... of a plurality of amplifying means, and a sixth switching means S06 connecting each of a plurality of fifth switching means S02 t a fourth current source Is. Moreover, it comprises a sending means OR for sending an operation signal to the sixth switching means S06 when data are read and written, and selecting means SEL0-SEL2 for sending operation signals to the first-fifth switching means S03, S04, S05, S01 and S02 on the basis of a fed selection signal. Since the capacitor Cx is prohibited in this manner from discharging electric charges when data are written, a time while a specified channel cannot be used in a read state is shortened when data are to be read out again by the channel. A consumed electricity is accordingly reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for reproducing data recorded on a recording medium by an MR head using a magnetoresistive effect element, and more particularly, when the MR head is switched from a writing state to a reading state. The present invention relates to an MR head read circuit that shortens the switching time until stable data reproduction is possible.

In recent years, in magnetic recording / reproducing devices as external storage devices of electronic computers, miniaturization and large capacity have been advanced, and as a data reproducing head, an MR head using a magnetoresistive effect element is used instead of a thin film head. It has come to be done.

This is because the use of the MR head makes it possible to obtain a reproduction output that does not depend on the peripheral speed of the recording medium, so that the recording density can be increased by lowering the peripheral speed of the recording medium. is there.

When reproducing data with an MR head, it is necessary to pass a sense current through the magnetoresistive effect element, which causes a potential difference between both terminals of the magnetoresistive effect element. Then, connect one terminal of the magnetoresistive element to the base of one transistor, connect the other terminal of this magnetoresistive element to the base of the other transistor, and connect a capacitor between the emitters of these two transistors. In a read circuit using a differential amplifier configured as described above, electric charges that generate a voltage corresponding to the potential difference are accumulated in the capacitor, and the voltage of the capacitor gives a potential difference to the bias voltage of the two transistors.

By the way, in the magnetic disk device,
Since multiple MR heads are used, this multiple M
A plurality of read circuits that respectively reproduce data from the R head are configured by one LSI, and the capacitors are shared by the plurality of read circuits.

Then, the read circuit designated by the selection signal from the host device supplies the sense current to the corresponding MR head to reproduce the data, but at the time of writing the data, the sense current is supplied. Is stopped, the electric charge accumulated in the capacitor is discharged.

Therefore, when reading data again,
Until the charging of the capacitor due to the potential difference generated between both terminals of the magnetoresistive element is completed, the bias voltage of the transistor forming the differential amplifier is not stable, and thus data cannot be reproduced during this period. , This time needs to be short.

[0008]

2. Description of the Related Art FIG. 39 is a diagram for explaining an example of a conventional MR head read circuit. Transistor Q1 and resistor R
1, R2, the resistance Rmr of the magnetoresistive effect element, and the current source Is constitute an MR head bias circuit, and transistors Q2 and Q3, resistors R3 and R4, and a capacitor Cx are provided.
And the current sources I1 and I2 form a first-stage amplifier, and the amplifier AMP1, the current source I3, and the resistors R5 and R6 form a second-stage amplifier.

The transistor Q1 operates by applying a bias voltage from the power source Vx to the base, and the current supplied from the power source Vc is applied to the resistor R1 and the resistor Rmr of the magnetoresistive effect element.
And the resistor R2, and the current is supplied to the current source Is.

Therefore, when Rmr changes due to a change in the magnetic field, a signal that changes corresponding to this change amount is applied between the bases of the transistors Q2 and Q3 to be amplified, and the signal amplified by the amplifier AMP1 is resistance-converted. R5 and R
6 is extracted.

A characteristic of this MR head read circuit is that the bias voltage applied to the bases of the transistors Q2 and Q3 has a potential difference of Rmr × Is, where Is is the current flowing through the magnetoresistive effect element. is there.

Therefore, only when reading data,
If a current is caused to flow through the current source Is and the current sources I1 to I3, the electric charge accumulated in the capacitor Cx for passing an AC signal is discharged at the time of writing the data. Therefore, at the time of reading the data, the Rmr is stored in the capacitor Cx. × I
Until the electric charges that generate the potential difference of s are charged,
The bias voltage supplied to the bases of the transistors Q2 and Q3 will change.

Time T until the bias voltage stabilizes
x becomes Tx = (Rmr × Is × Cx) / I2 ..., and the resistance Rmr of the magnetoresistive effect element and the current source Is
The larger the current value and the capacity of the capacitor Cx,
The smaller the current of the current source I2, the longer it takes.

FIG. 40, FIG. 41 and FIG. 42 are block diagrams for explaining an example of the prior art. An n + 1 channel MR head read circuit is shown, and each channel portion is shown in FIGS.
1, a part surrounded by a dotted line in FIG. 42, and the other parts are common parts. Each channel part has head number HD # 00-H
As shown by D # 0n, n + 1 basic circuits shown in FIG. 39 are formed.

That is, FIG. 40 shows the configuration of the head number HD # 00, FIG. 41 shows the configuration of the head number HD # 01, and FIG. 42 shows the configuration of the head number HD # 0n. However, in order to share the capacitor Cx and the current source Is in each basic circuit and to operate only the basic circuit of the selected head number, the switch Sx1 is provided between the power source Vx and the transistor Qx1 as shown in the figure. , A switch Sx2 between the resistor Rx2 and the current source Is, a switch Sx3 between the transistor Qx2 and the current source Ix1, and a transistor Qx3.
And the current source Ix2 between the switch Sx4 and the amplifier AMP0
The switch Sx5 is inserted between x and the current source Ix3, and the switch S06 is inserted between the switch Sx2 and the current source Is. The meaning of each x in Qx, Sx, and Ix is 0.
Each head number from to n is shown.

The switch S06 outputs the read signal RG.
Are controlled to be turned on or off by turning on or off, and the switches Sx1 to Sx5 select signals HDS1 to HS when the read signal RG input to the selection circuit SEL is on.
The head with the head number designated by D3 is turned on.

Therefore, when the read signal RG is off, the switch S06 is off, so that no current flows through the current source Is and no current flows through the magnetoresistive effect element of any head number. Therefore, each resistor Rmr0 to Rmrn
A potential difference is not generated in the capacitor Cx, and the charge of the capacitor Cx remains discharged.

FIG. 43 is a diagram for explaining the waveform of each part when the read signal is turned on. In FIG. 43, as shown by RG, the read signal becomes the logic "1" and the reading is instructed. For example, the selection signals HDS1, 2, 4 shown in FIG. 40 are both the logic "0", and the selection circuit SEL becomes Head number HD #
FIG. 40 shows waveforms when 00 is selected, and when the switches S01 to S06 in FIG. 40 are off, the current sources Is, I01, I
Since 02 is separated, the transistor Q01 and
The voltage of each base and emitter of the transistor Q02 and the transistor Q03 is substantially equal to the voltage of the power supply Vs.

When each of the switches S01 to S06 is turned on, the emitter of the transistor Q01 becomes Q01E.
As shown in, the voltage V
_BE (Q01) lower voltage, and the base of the transistor Q02 is R01 × I than Q01E as shown in Q02B.
The voltage becomes lower by s, and the base of the transistor Q03 is Rmr0 × Is than Q02B as shown in Q03B.
The voltage of the transistor Q02 becomes lower than that of Q02B by the voltage V _BE (Q02) between the base and the emitter of the transistor Q02, and the emitter of the transistor Q03 once becomes the emitter of the transistor Q02 as shown in Q03E. The voltage becomes the same as the voltage Q02E, but then decreases by the voltage V _BE (Q03) between the base and the emitter until the voltage becomes lower than the base voltage Q03B of the transistor Q03.

This is Rmr0 for the capacitor Cx.
The time Tx shown in the above formula is expressed by the voltage represented by × Is
Indicates that the emitter voltage Q03E of the transistor Q03 is not stable until after the lapse of time and charging is completed.

In a normal read state, a minute signal is generated at both ends of Rmr0 by the external magnetic field.
The generated signal is superimposed on the voltages of the base and emitter of the transistors Q02 and Q03.

Therefore, the reproduced signal is output to the collectors of the transistors Q02 and Q03, as shown in FIG.
As indicated by VQ02C-VQ03C of No. 8, the emitter voltage of the transistor Q03 is not stable during the time indicated by Tx, so that the first-stage amplifier composed of the transistors Q02 and Q03 is in a saturated state and is reproduced. Signal is not amplified normally.

This effect also appears in the post-amplifier AMP00 and, as indicated by VOUTP and VOUTN in FIG. 43, Tx.
Amplification of the signal is not performed normally in the range over the time indicated by
VOUTP-VOUTN Td range of fixed time,
The read function does not work properly.

[0024]

As described above, conventionally, the read function does not operate normally for a fixed time Td after the read signal is sent out. Therefore, when the read state and the write state are repeated, this Td is used. There is a problem that it cannot be used as a read state during the indicated time.

In view of the above problems, the present invention has an object to shorten the period in which the read state cannot be used immediately after switching from the write state to the read state as much as possible.

[0026]

As shown in FIGS. 1 to 12, the purpose of the MR head read circuit is to connect one terminal of a magnetoresistive element to one of the transistors (Q02 to Qn2). Connected to the base of, the other terminal of this magnetoresistive effect element is connected to the base of the other transistor (Q03 ~ Qn3), and the one transistor (Q02 ~ Qn2)
Is connected to the first current source (I01 to In1) via the first switching means (S03 to Sn3), and the other transistor (Q
03-Qn3) is connected to a second current source (I02-In2) via second switching means (S04-Sn4), and the first and second switching means (S03-Sn3) (S04) are connected. ~ Sn4) is operated, the third current source (I03 ~ I3 ~) via the pre-stage amplifier configured to amplify the signal reproduced by the magnetoresistive effect element and the third switching means (S05 ~ Sn5). In3) connected to this third switching means
When (S05-Sn5) is operated, a bias voltage is applied through the second-stage amplifier (AMP00-AMP0n) that further amplifies the signal amplified by the previous-stage amplifier, and the fourth switching means (S01-Sn1) to the magnetic field. Transistor (Q01
To Qn1) and a fifth switching means (S02 to Sn2) for connecting the magnetoresistive effect element to a fourth current source (Is).

A capacitor (Cx) commonly connected between the emitters of the one transistors (Q02 to Qn2) and the emitters of the other transistors (Q03 to Qn3) of the plurality of amplifying means. And a plurality of the fifth switching means
Sixth connecting (S02 to Sn2) to the fourth current source (Is), respectively
Switching means (S06) and a sending means (O) for sending an operation signal to the sixth switching means (S06) when reading and writing data.
R) and the given selection signal based on the first to fifth switching means (S03 to Sn3) (S04 to Sn4) (S05 to Sn5) (S01 to Sn1) (S
02-Sn2) to select operation means (SEL0-SE)
L2) and are provided.

As shown in FIGS. 1 to 3, when reading data, an operation signal is sent to the first to fifth switching means of the amplifying means which is needed, and when writing data, the necessary signal is sent. The operating signal is sent to the first to fifth switching means of the other amplifying means except the amplifying means, or
As shown in FIGS. 4 to 6, at the time of reading data, an operation signal is sent to the required first, second, fourth and fifth switching means of the amplifying means, and the necessary amplifying means. An operation signal is sent to the third switching means, and when writing data, the operation signal is sent to the first, second, fourth and fifth switching means of the other amplifying means excluding the necessary amplifying means. Or, as shown in FIGS. 7 to 9, when reading data, an operation signal is sent to the required fourth and fifth switching means of the amplifying means, and when writing data, Operation signals are sent to the fourth and fifth switching means of the other amplifying means excluding the necessary amplifying means, and at the time of reading and writing of data, the first to third of the necessary amplifying means. Send an operation signal to the switching means,
Alternatively, as shown in FIGS. 10 to 12, when reading data, an operation signal is sent to the fourth and fifth switching means of the necessary amplifying means, and when writing data, the necessary amplifying means. Except for the above, the operation signal is sent to the fourth and fifth switching means of the other amplifying means, and the operation signal is sent to the necessary first and second switching means of the amplifying means when reading and writing data. And the operation signal is sent to the third switching means of the required amplifying means only when data is read.

Further, as shown in FIGS. 13 to 15, M
The read circuit of the R head connects one terminal of the magnetoresistive element to the base of one transistor (Q02 to Qn2),
The other terminal of the magnetoresistive element is connected to the bases of the other transistors (Q03 to Qn3), and the emitter of the one transistor (Q02 to Qn2) is connected to the first switching means (S03).
~ Sn3) to the first current source (I01 to In1), and the emitter of the other transistor (Q03 to Qn3) is connected to the second current source via the second switching means (S04 to Sn4). (I02 to In2), and is configured to amplify the signal reproduced by the magnetoresistive effect element when the first and second switching means (S03 to Sn3) (S04 to Sn4) are operated. It is connected to the third current source (I03 to In3) via the first pre-stage amplifier and the third switching means (S05 to Sn5), and when the third switching means (S05 to Sn5) operates,
A first post-stage amplifier (AMP00 to AMP0n) for further amplifying the signal amplified by the first pre-stage amplifier, and a fourth switching means (S01).
~ Sn1) is supplied with a bias voltage through the transistors (Q01 to Qn1) for supplying a current to the magnetoresistive effect element, and a fifth transistor for connecting the magnetoresistive effect element to a fourth current source (Is).
Switching means (S02 to Sn2) and a plurality of amplifying means and one terminal of the reference resistance (Rx) to one transistor (Q
D2) base, the other terminal of this reference resistor (Rx) is connected to the base of another transistor (QD3), and the emitter of said one transistor (QD2) is the seventh switching means (SD3). Is connected to the fifth current source (ID1) via the transistor and the emitter of the other transistor (QD3) is connected to the eighth switching means (SD).
4) is connected to the sixth current source (ID2), and when the seventh and eighth switching means (SD3) (SD4) are operated, the reference resistance
A second pre-amplifier configured to amplify the output of (Rx) and a seventh current source (ID
3) and when the ninth switching means (SD5) operates, the second rear-stage amplifier (AMP0D) for further amplifying the signal amplified by the second front-stage amplifier and the tenth switching means ( SD
1) A bias voltage is applied via the reference resistance (Rx)
The transistor (QD1) that supplies current to the
(Rx) is connected to the fourth current source (Is) and an eleventh switching means (SD2) is provided, and pseudo amplification means is provided.

The emitters of the one transistor (Q02 to Qn2) of the plurality of amplifying means and the one transistor (QD2) of the pseudo amplifying means and the other transistor (Q03 to Qn of the plurality of amplifying means). Qn3) and one capacitor (Cx) commonly connected between the other transistor (QD3) emitter of the pseudo amplification means, and the fifth switching means (S02 to Sn2) of the plurality of amplification means. ) And sixth switching means (S06) for connecting the eleventh switching means (SD2) of the pseudo-amplifying means to the fourth current source (Is), respectively,
At the time of reading and writing data, the sixth switching means (S0
6) a transmission means (OR) for transmitting an operation signal, and a first operation means for transmitting an operation signal to the first to fifth switching means of the amplification means, which is required, on the basis of a selection signal given at the time of reading data. 1 selection means (SEL1) is provided, and when reading data, an operation signal is sent to the first to fifth switching means of the required amplifying means, and when writing data, the pseudo amplifying means. 7th to 11th switching means (SD1 to
This is achieved by sending an operation signal to SD5).

Further, as shown in FIGS. 16 to 18, M
The read circuit of the R head connects one terminal of the magnetoresistive element to the base of one transistor (Q02 to Qn2),
The other terminal of the magnetoresistive element is connected to the bases of the other transistors (Q03 to Qn3), and the emitter of the one transistor (Q02 to Qn2) is connected to the first switching means (S03).
~ Sn3) to the first current source (I01 to In1), and the emitter of the other transistor (Q03 to Qn3) is connected to the second current source via the second switching means (S04 to Sn4). (I02 to In2), and is configured to amplify the signal reproduced by the magnetoresistive effect element when the first and second switching means (S03 to Sn3) (S04 to Sn4) are operated. It is connected to the third current source (I03 to In3) via the first pre-stage amplifier and the third switching means (S05 to Sn5), and when the third switching means (S05 to Sn5) operates,
A post-stage amplifier (AMP00-AMP0n) for further amplifying the signal amplified by the first pre-stage amplifier, and a fourth switching means (S01-Sn1).
Transistors (Q01 to Qn1) that are supplied with a bias voltage via the transistor to supply current to the magnetoresistive effect element, and fifth switching means (S02) for connecting the magnetoresistive effect element to the fourth current source (Is). ~ Sn2) and one terminal of the reference resistance (Rx) is connected to the base of one transistor (QD2), and the other terminal of this reference resistance (Rx) is connected to another transistor. It is connected to the base of (QD3) and the emitter of the one transistor (QD2) is connected to the seventh switching means (SD
3) is connected to the fifth current source (ID1), the emitter of the other transistor (QD3) is connected to the sixth current source (ID2) via the eighth switching means (SD4), A second pre-amplifier configured to amplify the output of the reference resistor (Rx) when the seventh and eighth switching means (SD3) (SD4) are operated,
A transistor (QD1) supplied with a bias voltage through the ninth switching means (SD1) and supplying a current to the reference resistor (Rx)
And a pseudo amplification means composed of a tenth switching means (SD2) for connecting the reference resistance (Rx) to the fourth current source (Is).

Then, the emitters of the one transistor (Q02 to Qn2) of the plurality of amplifying means and the one transistor (QD2) of the pseudo amplifying means and the other transistor (Q03 to Qn of the plurality of amplifying means). Qn3) and one capacitor (Cx) commonly connected between the other transistor (QD3) emitter of the pseudo amplification means, and the fifth switching means (S02 to Sn2) of the plurality of amplification means. ) And sixth switching means (S06) for connecting the tenth switching means (SD2) of the pseudo-amplifying means to the fourth current source (Is), respectively,
The sixth switching means (S
06), and a transmission means (OR) for transmitting an operation signal, and a selection for transmitting an operation signal to the first to fifth switching means of the amplification means, which is required, based on the selection signal given at the time of reading the data. Means (SEL1) are provided, and when reading data, an operation signal is sent to the first to fifth switching means of the required amplifying means, and when writing data, the seventh amplifying means of the pseudo amplifying means is provided. Is achieved by sending an operation signal to the tenth switching means (SD1 to SD4).

Further, as shown in FIGS. 19 to 21, M
The read circuit of the R head connects one terminal of the magnetoresistive element to the base of one transistor (Q02 to Qn2),
The other terminal of the magnetoresistive element is connected to the bases of the other transistors (Q03 to Qn3), and the emitter of the one transistor (Q02 to Qn2) is connected to the first switching means (S03).
~ Sn3) to the first current source (I01 to In1), and the emitter of the other transistor (Q03 to Qn3) is connected to the second current source via the second switching means (S04 to Sn4). (I02 to In2), and is configured to amplify the signal reproduced by the magnetoresistive effect element when the first and second switching means (S03 to Sn3) (S04 to Sn4) are operated. Pre-stage amplifier and third switching means
It is connected to a third current source (I03 to In3) via (S05 to Sn5), and when this third switching means (S05 to Sn5) operates, a rear stage that further amplifies the signal amplified by the front stage amplifier. Amplifier (A
MP00 to AMP0n), transistors (Q01 to Qn1) supplied with a bias voltage via fourth switching means (S01 to Sn1) and supplying a current to the magnetoresistive effect element, and the magnetoresistive effect element The fifth switching means (S02-) connected to the current source (Is) of
Sn2) and a plurality of amplification means and a reference resistance (Rx)
One terminal of this transistor is connected to the base of one transistor (QD2), and the other terminal of this reference resistor (Rx) is connected to another transistor.
An amplifier connected to the base of (QD3) and configured to amplify the output of this reference resistor (Rx), and a seventh switching means (SD
1) is supplied with a bias voltage via the transistor (QD1) for supplying a current to the reference resistor (Rx), and the reference resistor (Rx).
x) is connected to the fourth current source (Is), the eighth switching means (S
D2) and a pseudo amplification means.

Then, the emitters of the one transistor (Q02 to Qn2) of the plurality of amplifying means and the one transistor (QD2) of the pseudo amplifying means and the other transistor (Q03 to Qn of the plurality of amplifying means). Qn3) and one capacitor (Cx) commonly connected between the other transistor (QD3) emitter of the pseudo amplification means, and the fifth switching means (S02 to Sn2) of the plurality of amplification means. ) And sixth switching means (S06) for connecting the eighth switching means (SD2) of the pseudo-amplifying means to the fourth current source (Is), respectively, and at the time of reading and writing data, 6 switching means (S0
6) a sending means (OR) for sending an operation signal, and a selection for sending an operation signal to the third to fifth switching means of the necessary amplifying means based on a selection signal given at the time of reading data. Means (SEL1) and a selecting means (SEL2) for sending an operation signal to the first and second switching means of the amplifying means, which is required, based on a given selection signal when reading and writing data. Is provided, at the time of reading data, an operation signal is sent to the first to fifth switching means of the required amplifying means, and at the time of writing of data, the first and the fifth amplifying means of the required amplifying means. This is achieved by sending operation signals to the second switching means and the seventh and eighth switching means (SD1, SD2) of the pseudo amplification means.

Further, as shown in FIGS. 22 to 30, M
The read circuit of the R head connects one terminal of the magnetoresistive element to the base of one transistor (Q02 to Qn2),
The other terminal of this magnetoresistive element is connected to the bases of the other transistors (Q03 to Qn3), and the first switching means (S3) that shares the emitter of the one transistor (Q02 to Qn2) is used. The first current source (I1) is connected to the second current source (I2) via the second switching means (S4) which shares the emitter of the other transistor (Q03 to Qn3), A pre-stage amplifier configured to amplify a signal reproduced by the magnetoresistive effect element when the first and second switching means (S3) (S4) are operated, and the fourth switching means (S01 to Sn1). Transistors (Q01 to Qn1) that are supplied with a bias voltage via the transistor to supply current to the magnetoresistive effect element, and fifth switching means (S02) for connecting the magnetoresistive effect element to the fourth current source (Is). ~
Sn2) and a plurality of amplification means.

Then, the third switching means (S5)
Is connected to the current source (I3) of the amplifier, and when the third switching means (S5) operates, a rear stage amplifier (AMP) for further amplifying the signal amplified by the front stage amplifier of each of the amplifying means, A single capacitor (Cx) connected in common between the emitter of the one transistor (Q02 to Qn2) and the emitter of the other transistor (Q03 to Qn3) of the amplification means, and a plurality of the fifth capacitors. The switching means (S02 to Sn2) are respectively connected to the fourth current source.
A sixth switching means (S6) connected to (Is) and the fourth and fifth switching means (S01 to Sn1) (S) based on a given selection signal.
02-Sn2) and a selection means (SEL0) for sending operation signals respectively,
When reading and writing data, the first, second and third
And send an operation signal to the sixth switching means (S3 to S6),
Alternatively, an operation signal is sent to the first, second and sixth switching means (S3, S4, S6), or an operation signal is sent to the sixth switching means (S6) (OR ) And are provided.

Then, as shown in FIGS. 22 to 24, an operation signal is sent to the required fourth and fifth switching means of the amplifying means at the time of reading the data, and at the time of writing the data, the above-mentioned operation signal is sent. An operation signal is sent to the fourth and fifth switching means of the other amplifying means other than the required amplifying means, or as shown in FIGS. 25 to 27, it is necessary when reading data. The operation signal is sent to the fourth and fifth switching means of the amplifying means, and the third signal
The operation signal to the switching means (S5), and at the time of writing the data, the operation signal is sent to the fourth and fifth switching means of the other amplifying means excluding the required amplifying means, or As shown in FIGS. 28 to 30, at the time of reading data, an operation signal is sent to the required fourth and fifth switching means of the amplifying means, and at the same time, the first, second and third switching means are provided. An operation signal is sent to the switching means (S3, S4, S5), and at the time of writing data, an operation signal is sent to the fourth and fifth switching means of the other amplifying means except the required amplifying means. Achieved by

Further, as shown in FIGS. 31 to 33, M
The read circuit of the R head connects one terminal of the magnetoresistive element to the base of one transistor (Q02 to Qn2),
The other terminal of this magnetoresistive element is connected to the bases of the other transistors (Q03 to Qn3), and the first switching means (S3) that shares the emitter of the one transistor (Q02 to Qn2) is used. The first current source (I1) is connected to the second current source (I2) via the second switching means (S4) which shares the emitter of the other transistor (Q03 to Qn3), A pre-stage amplifier configured to amplify a signal reproduced by the magnetoresistive effect element when the first and second switching means (S3) (S4) are operated, and the fourth switching means (S01 to Sn1). Transistors (Q01 to Qn1) to which a bias voltage is applied through to supply a current to the magnetoresistive effect element, and fifth switching means (S02) for connecting the magnetoresistive effect element to a fourth current source (Is). ~
Sn2) and a plurality of amplification means and a reference resistance (Rx)
One terminal of this transistor is connected to the base of one transistor (QD2), and the other terminal of this reference resistor (Rx) is connected to another transistor.
Is connected to the base of (QD3), the emitter of the one transistor (QD2) is connected to the first current source (I1) via the first switching means (S3), and the other transistor (QD3) is connected to the other transistor (Q1).
The emitter of D3) is connected to the second via the second switching means (S4).
Connected to the current source (I2) of the first and second switching means (S3)
A pseudo pre-stage amplifier configured to amplify the output of the reference resistance (Rx) when (S4) operates, and a seventh switching means (S
A bias voltage is applied via D1) to the reference resistor (Rx)
A transistor (QD1) that supplies current to the
Eighth switching means for connecting (Rx) to the fourth current source (Is)
(SD2) and a pseudo amplification means.

Then, the third switching means (S5)
When the third switching means (S5) is operated, the signal amplified by the pre-stage amplifier of each amplification means and the pseudo pre-stage amplifier of the pseudo amplification means are amplified. A post-stage amplifier (AMP) for further amplifying the signal, the one transistor (Q02 to Qn2) of the plurality of amplifying means and the emitter of the one transistor (QD2) of the pseudo amplifying means, and the plurality of amplifying means. The other transistor (Q03
~ Qn3) and the other transistor (Q
One capacitor (Cx) commonly connected to the emitter of D3) and the fifth switching means of the plurality of amplifying means.
(S02 to Sn2) and the eighth switching means of the pseudo amplification means
Sixth switching means (S6) for connecting (SD2) to the fourth current source (Is), respectively, and the first, second, third and sixth switching means for reading and writing data. Sending means (OR) for sending an operation signal to (S3, S4, S5, S6), and the fourth and fifth amplifying means which are required, based on a given selection signal only when reading data. The switching means is provided with a selection means (SEL1) for transmitting an operation signal, and the seventh and eighth switching means (SD1, SD) of the pseudo amplification means are provided only when writing data.
It is achieved by sending an operation signal to 2).

Further, as shown in FIGS. 34 to 35, M
The read circuit of the R head connects one terminal of the magnetoresistive element to the base of one transistor (Q02 to Qn2),
The other terminal of this magnetoresistive element is connected to the bases of the other transistors (Q03 to Qn3), and the first switching means (S3) that shares the emitter of the one transistor (Q02 to Qn2) is used. The first current source (I1) is connected to the second current source (I2) via the second switching means (S4) which shares the emitter of the other transistor (Q03 to Qn3), A pre-stage amplifier configured to amplify a signal reproduced by the magnetoresistive effect element when the first and second switching means (S3) (S4) are operated, and the fourth switching means (S01 to Sn1). Transistors (Q01 to Qn1) to which a bias voltage is applied through to supply a current to the magnetoresistive effect element, and fifth switching means (S02) for connecting the magnetoresistive effect element to a fourth current source (Is). ~
Sn2) and a plurality of amplification means and a reference resistance (Rx)
One terminal of this transistor is connected to the base of one transistor (QD2), and the other terminal of this reference resistor (Rx) is connected to another transistor.
Is connected to the base of (QD3), the emitter of the one transistor (QD2) is connected to the first current source (I1) via the first switching means (S3), and the other transistor (QD3) is connected to the other transistor (Q1).
The emitter of D3) is connected to the second via the second switching means (S4).
Connected to the current source (I2) of the first and second switching means (S3)
A pseudo pre-stage amplifier configured to amplify the output of the reference resistance (Rx) when (S4) operates, and a seventh switching means (S
A bias voltage is applied via D1) to the reference resistor (Rx)
A transistor (QD1) that supplies current to the
Eighth switching means for connecting (Rx) to the fourth current source (Is)
(SD2) and a pseudo amplification means.

Then, the third switching means (S5)
When the third switching means (S5) is operated, the signal amplified by the pre-stage amplifier of each amplification means and the pseudo pre-stage amplifier of the pseudo amplification means are amplified. A post-stage amplifier (AMP) for further amplifying the signal, the one transistor (Q02 to Qn2) of the plurality of amplifying means and the emitter of the one transistor (QD2) of the pseudo amplifying means, and the plurality of amplifying means. The other transistor (Q03
~ Qn3) and the other transistor (Q
One capacitor (Cx) commonly connected to the emitter of D3) and the fifth switching means of the plurality of amplifying means.
(S02 to Sn2) and the eighth switching means of the pseudo amplification means
A sixth switching means (S6) for connecting (SD2) to the fourth current source (Is), respectively, and the first, second and sixth switching means (S3, S3) for reading and writing data. S4, S6) sending means (OR) for sending an operation signal, and an operation signal to the fourth and fifth switching means of the necessary amplifying means based on a given selection signal only when reading data. Selection means (S
EL1) is provided, an operation signal is sent to the seventh and eighth switching means (SD1, SD2) of the pseudo amplification means when writing data, and the third switching means when reading data.
This is achieved by sending an operation signal to (S5).

[0042]

With the above-described structure, the read circuit of the MR head shown in FIGS. 1 to 3 is designated while the data is being written after the data is read from the designated channel. Since one of the channels other than the other channel is operating, the electric charge of the capacitor Cx is not discharged, and the time T which cannot be used as the read state when the data is read by the designated channel again.
d can be shortened.

Further, the read circuit of the MR head shown in FIGS. 4 to 6 does not operate only the post-stage amplifier of the channel which is operated at the time of writing data, and therefore, the read circuits of FIGS.
As in the case shown in FIG. 3, it is possible to shorten the time Td during which the reading state cannot be used and to reduce the power consumption.

The read circuit of the MR head shown in FIGS. 7 to 9 operates the MR head bias circuits described in FIG. 39 for other channels except the designated channel while data is being written. The other circuits of the designated channel are operating in both reading and writing of data.

That is, since only the MR head bias circuit is switched, the number of switches to be switched is smaller than that shown in FIGS. 1 to 3, and it is not necessary to allow extra switching time. Therefore, the switching time should be shortened accordingly. Can be done.

Further, the read circuit of the MR head shown in FIGS. 10 to 12 can reduce the power consumption when writing data, as compared with the read circuit shown in FIGS. 7 to 9 because the post-stage amplifier does not operate.

Further, in the read circuit of the MR head shown in FIGS. 13 to 15, since the pseudo amplifying means is operated at the time of writing the data, the resistance value of the reference resistance Rx is set to the resistances Rmr0 to Rmrn of the magnetoresistive effect element. If it is set to the average value of, it is possible to reduce the voltage fluctuation of the capacitor Cx due to the switching at the time of reading and writing the data to 1/2 of the deviation of the resistance value of each magnetoresistive effect element, The switching time can be further shortened accordingly.

The MR head read circuits shown in FIGS. 16 to 18 are shown in FIGS. 13 to 1 when writing data.
Since the latter-stage amplifier does not operate, the power consumption can be reduced more than that shown in FIG.

In the read circuit of the MR head shown in FIGS. 19 to 21, the structure of the pseudo-amplifying means is simpler than that shown in FIGS. 13 to 18, and the switching speed at the time of reading or writing data is also increased. You can

The read circuit of the MR head shown in FIGS. 22 to 24 has resistors R3 and R more than those shown in FIGS.
4. Since the post-stage amplifier AMP, the switches S3 to S5 and the current sources I1 to I3 are shared by a plurality of amplifying means, the same effect as that shown in FIG. 1 to FIG. The time Td can be shortened.

The read circuit of the MR head shown in FIGS. 25 to 27 has resistors R3 and R more than those shown in FIGS.
4. Since the post-stage amplifier AMP, the switches S3 to S5, and the current sources I1 to I3 are shared by a plurality of amplifying means, the same effect as that shown in FIGS. 4 to 6 cannot be used economically, that is, the read state cannot be used. The time Td can be shortened and the power consumption can be saved.

In the read circuit of the MR head shown in FIGS. 28 to 30, only the MR head bias circuit other than the designated channel is operating at the time of writing data, so that the time Td that cannot be used as a read state is increased. Can be shortened and the power consumption can be minimized.

The read circuit of the MR head shown in FIGS. 31 to 33 has a plurality of resistors R3 and R4, a post-stage amplifier AMP, switches S3 to S5 and current sources I1 to I3 as compared with those shown in FIGS. Since the amplifying means and the pseudo amplifying means are commonly used, the same effect as that shown in FIGS. 13 to 15 can be economically realized.

Further, the read circuit of the MR head shown in FIGS. 34 to 36 is shown in FIGS.
The power consumption can be reduced as compared with that shown in (1) because the post-stage amplifier does not operate.

[0055]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1, 2 and 3 are block diagrams of circuits showing a first embodiment of the present invention. In this embodiment, the selection circuit SE
The operation of L0 and the operation of the switch S06 at the time of reading and writing of data are different from those of FIGS. 40 to 42 only in that the OR circuit 0R is provided, and the others are the same.

Therefore, the operation at the time of reading data is the same as the conventional one, but at the time of writing the data, the basic circuit of the head number other than the basic circuit of the head number selected at the time of the data reading is selected and operated. It is like this.

That is, when the read signal RG and the write signal WG are logic "1", the OR circuit OR sends the logic "1" to the switch S06, so that the switch S06 operates at the time of data read and at the time of writing. Is closed.

The selection circuit SEL0 sends a logic "1" to the signal lines G00 to G0N under the following conditions to operate the switches Sx1 to Sx5 of the selected basic circuit. For example, if there are eight basic circuits and the head number is HD # 00-
HD # 07, -sign is logic "0" and + sign is logic
Assuming "1", G00 = (-HD4) x (-HD2) x (-HD1) x (+ RG) + (+ HD4) x (+ HD2) x (+ HD1) x (+ WG)… (1) G01 = (-HD4) x (-HD2) x (+ HD1) x (+ RG) + (+ HD4) x (+ HD2) x (-HD1) x (+ WG) ... (2) G02 = (-HD4) x (+ HD2) x (-HD1) x (+ RG) + (+ HD4) x (-HD2) x (+ HD1) x (+ WG) ... (3) G03 = (-HD4) x (+ HD2) x (+ HD1) x (+ RG) + (+ HD4) ) × (−HD2) × (−HD1) × (+ WG) (4) G04 = (+ HD4) × (−HD2) × (−HD1) × (+ RG) + (−HD4) × (+ HD2) × (+ HD1 ) × (＋ WG)… (5) G05 = (＋ HD4) × (－HD2) × (＋ HD1) × (＋ RG) ＋ (－HD4) × (＋ HD2) × (－HD1) × (＋ WG)… (6) G06 = (+ HD4) x (+ HD2) x (-HD1) x (+ RG) + (-HD4) x (-HD2) x (+ HD1) x (+ WG) ... (7) G07 = (+ HD4) x (+ HD2) x ( + HD1) x (+ RG) + (-HD4) x (-HD2) x (-HD1) x (+ WG) (8) That is, when reading data, the read signal RG is logic "1".
Then, when the logic values shown in the equation (1) are input as the selection signals HDS1, HDS2, and HDS4, the logic "1" is sent to the signal line G00, and the write signal W
When G becomes logic "1" and the logic values shown in the equation (1) are input to the selection signals HDS1, HDS2, and HDS4, the signal line
Logic "1" is sent to G07.

Therefore, the data is read out from the head number HD.
The basic circuit of # 00 is executed, and the capacitor Cx is VQ02.
E-VQ03E (emitter voltage of transistor Q02-
It is charged by the voltage expressed by the emitter voltage of transistor Q03), and when writing data, head number HD
The basic circuit of # 07 operates to charge the capacitor Cx with the voltage represented by VQ72E-VQ73E.

Further, at the time of data reading, the read signal RG becomes the logic "1", and the selection signals HDS1, HDS2 and H
When the logical value shown in the equation (2) is input as DS4, the logical "1" is transmitted to the signal line G01, the write signal WG becomes the logical "1" at the time of data writing, and the selection signal HDS1,
When the logical value shown in equation (2) is input to HDS2 and HDS4, a logical "1" is sent to the signal line G06.

Therefore, the data is read by the head number HD
The basic circuit of # 01 is executed, and the capacitor Cx is VQ12.
It is charged by the voltage expressed by E-VQ13E, and at the time of writing data, the basic circuit of the head number HD # 06 operates to charge the capacitor Cx by the voltage expressed by VQ62E-VQ63E.

The same applies to the cases of the expressions (3) to (8), and detailed description thereof will be omitted. FIG. 37 is a waveform diagram for explaining the operation of FIGS. When reading data, the emitter voltage Q01E of the transistor Q01 and the transistor Q01
02 base and emitter voltages Q02B, Q02E,
Base and emitter voltage Q03 of transistor Q03
B and Q03E are the same as those in FIG.

When the basic circuit of head number HD # 07 operates as described above at the time of writing data, the transistor Q0
The emitter voltage of 1 and the base and emitter voltages of the transistor Q02 and the base and emitter voltages of the transistor Q03 decrease to near Vs again, but instead, the emitter voltage Q71E of the transistor Q71 and the base and emitter voltage of the transistor Q72 are changed. Q72B, Q7
2E and the base and emitter voltages Q73B and Q73E of the transistor Q73 increase respectively as shown in the figure.

Therefore, the difference between the collector voltage of the transistor Q02 and the collector voltage of the transistor Q03 and the difference between the collector voltage of the transistor Q72 and the collector voltage of the transistor Q73 are respectively VQ02C-VQ03 in FIG.
C and VQ72C-VQ73C, and the output VOUTP-VOUTN of the post-stage amplifier is, as shown in the figure, the fall of the read signal RG, the rise of the write signal WG, the rise of the read signal RG, and the rise of the write signal WG. It is disturbed at the time of switching shown by the drop, but the others are stable.

The voltage Vrd applied to both ends of the capacitor Cx at the time of reading is as described above: Vrd = VQ02E-VQ03E (9) The voltage Vw applied to both ends of the capacitor Cx at the time of writing.
As described above, t is Vwt = VQ72E-VQ73E (10) VQ02E = Vs-VBE (Q01) -Is * R01-VBE (Q02) ... (11) VQ03E = Vs-VBE (Q01) -Is * R01-Is * Rmr0-VBE (Q03) ... (12) VQ72E = Vs-VBE (Q71) -Is * R71-VBE (Q72) ... (13) VQ73E = Vs-VBE (Q71) -Is * R71-Is * Rmr7-VBE ( Therefore, from equations (9) to (14), Vrd = Is × Rmr0 + VBE (Q03) -VBE (Q02) Vwt = Is × Rmr7 + VBE (Q73) -VBE (Q72) Vrd-Vwt = Is × Rmr0 ＋ VBE (Q03) −VBE (Q02) −Is × Rmr7
−VBE (Q73) ＋ VBE (Q72) ＝ Is × (Rmr0 −Rmr7) ＋ [VBE (Q0
3) −VBE (Q73)] + [VBE (Q72) −VBE (Q02)] For LSI, etc., VBE (Q03) −VBE (Q73) and VBE (Q72) −VBE
(Q02) can be set to 0 as much as possible. Therefore, Vrd−Vwt = Is × (Rmr0−Rmr7), and the time of Td can be calculated within the range of the variation of the resistance value of the magnetoresistive effect element. It can be as close to 0 as possible.

FIGS. 4, 5, and 6 are block diagrams of circuits showing a second embodiment of the present invention. In this embodiment, the post-stage amplifiers AMP00 to AMP0n in the first embodiment are
The drive circuit of the switch Sx5 is different from the switches Sx1 to Sx4 so that the basic circuit of the head number selected at the time of data writing does not operate, and the switch Sx5 is selected and operated only at the time of data reading. The difference is that a selection circuit SEL1 is provided.

Therefore, the switches Sx1 to Sx4 are shown in FIGS.
Similar to the case of FIG. 3, the selection circuit SEL1 is operated by the selection signals sent by the selection circuit SEL0 with the logical values shown in the equations (1) to (8), and the selection circuit SEL1 is logically connected to the signal lines G10 to G1N under the following conditions. 1 "is sent and the switch S of the selected basic circuit
Operate x5.

For example, there are eight basic circuits, the head numbers are HD # 00 to HD # 07, and the-sign is logical.
Assuming that the "+" sign is a logical "1" with "0", G10 = (-HD4) x (-HD2) x (-HD1) x (+ RG) (15) G11 = (-HD4) x (- HD2) x (+ HD1) x (+ RG) ... (16) G12 = (-HD4) x (+ HD2) x (-HD1) x (+ RG) ... (17) G13 = (-HD4) x (+ HD2) x (+ HD1 ) × (＋ RG)… (18) G14 = (＋ HD4) × (−HD2) × (−HD1) × (＋ RG)… (19) G15 = (＋ HD4) × (−HD2) × (＋ HD1) × (＋ RG) (20) G16 = (+ HD4) x (+ HD2) x (-HD1) x (+ RG) ... (21) G17 = (+ HD4) x (+ HD2) x (+ HD1) x (+ RG) ... (22) That is, data At the time of reading, the read signal RG is logic "1".
Therefore, when the logical values shown in the equation (15) are input as the selection signals HDS1, HDS2, and HDS4, the logical "1" is transmitted to the signal line G10.

Therefore, the post-stage amplifier AMP00 of the head number HD # 00 operates at the time of reading the data, but at the time of writing the data, the logic "0" remains sent to the signal lines G10 to G1N. The post amplifier AMP07 of HD # 07 does not operate.

Further, at the time of data reading, the read signal RG becomes the logic "1", and the selection signals HDS1, HDS2 and H
When the logical value shown in equation (16) is input as DS4, a logical "1" is sent to the signal line G11.

Therefore, when the data is read, the post-amplifier AMP01 of the head number HD # 01 operates, but at the time of writing the data, the logic "0" remains sent to the signal lines G10 to G1N. The post amplifier AMP06 of HD # 06 does not operate.

The equations (17) to (22) are also the same as above, and detailed description thereof will be omitted. FIG. 38 is a waveform diagram for explaining the operation of FIGS. The emitter voltage of the transistor Q01 when reading data, the base and emitter voltage of the transistor Q02, the voltage of the base and emitter of the transistor Q03, the emitter voltage of the transistor Q71 when writing data, and the base and emitter voltage of the transistor Q72. And the base and emitter voltages of the transistor Q73 are the same as in FIG.

Since the post-amplifier AMP07 does not operate at the time of writing data, no current flows through the resistors R5 and R6 when the write signal WG becomes logic "1". Therefore, VO
The waveforms of UTP and VOUTN are as shown in the figure.
To VOUTP-VOUTN output the signal read by the magnetoresistive effect element only when reading data, and no output signal is sent when writing data.

Compared with the first embodiment, the Td time is slightly longer depending on the time characteristic of the post-stage amplifier, but the power consumption can be reduced. 7, 8 and 9 show the third embodiment of the present invention.
3 is a block diagram of a circuit showing an embodiment of FIG. In this embodiment, the switches Sx1 and Sx2 in the first embodiment are shown in FIG.
As in the case of FIG. 3, the switches Sx3, Sx4, and Sx5 are selected at the time of data reading and writing by operating with the selection signal sent by the selection circuit SEL0 with the logical values shown in the equations (1) to (8). A selection circuit SEL2 to be operated is provided, and only the MR head bias circuit is switched to another channel at the time of writing data to charge the capacitor Cx.

Therefore, the switches Sx1 and Sx2 are shown in FIGS.
Similar to the case of FIG. 3, the selection circuit SEL2 is operated by the selection signal transmitted by the selection circuit SEL0 with the logical values shown in the equations (1) to (8), and the selection circuit SEL2 is logically connected to the signal lines G20 to G2N under the following conditions. 1 "is sent and the switch S of the selected basic circuit
x3 to Sx5 are operated.

For example, there are eight basic circuits, the head numbers are HD # 00 to HD # 07, and the-sign is logical.
If it is "0" and the + sign indicates a logical "1", G20 = (-HD4) x (-HD2) x (-HD1) x [(+ RG) + (+ WG)]… (23) G21 = ( -HD4) x (-HD2) x (+ HD1) x [(+ RG) + (+ WG)] ... (24) G22 = (-HD4) x (+ HD2) x (-HD1) x [(+ RG) + (+ WG) ] (25) G23 = (-HD4) x (+ HD2) x (+ HD1) x [(+ RG) + (+ WG)] ... (26) G24 = (+ HD4) x (-HD2) x (-HD1) x [ (＋ RG) ＋ (＋ WG)]… (27) G25 ＝ （＋ HD4） × (－HD2） × (＋ HD1) × [(＋ RG） ＋ (＋ WG)]… （28） G26 ＝ (＋ HD4) × (＋ HD2) × (-HD1) x [(+ RG) + (+ WG)] ... (29) G27 = (+ HD4) x (+ HD2) x (+ HD1) x [(+ RG) + (+ WG)] ... (30) That is, when reading data , Read signal RG is logic "1"
Then, when the logical values shown in the equation (23) are input as the selection signals HDS1, HDS2 and HDS4, the logical "1" is transmitted to the signal line G20.

At the time of data writing, the write signal WG becomes the logic "1", and the selection signals HDS1, HDS2 and H
When the logical value shown in the equation (23) is input as DS4, the logical "1" is transmitted to the signal line G20.

Therefore, at the time of reading and writing data, the basic circuit of the head number HD # 00 operates, but at the time of writing data, a logic "0" is sent to the signal line G00 and a logic "0" is sent to the signal line G07. Since 1 ″ is sent, the MR head bias circuit of head number HD # 00 does not operate, but the MR head bias circuit of head number HD # 07 operates.

Since the same applies to the equations (24) to (30), detailed description thereof will be omitted. In this embodiment, the switch Sx1
Since only Sx2 and Sx2 are switched, the switching time is shortened as compared with the first embodiment, because it is not necessary to see extra switching time.

FIG. 10, FIG. 11 and FIG. 12 are block diagrams of circuits showing a fourth embodiment of the present invention. This embodiment is a combination of the second embodiment and the third embodiment, and the switches Sx1 and Sx2 are sent by the selection circuit SEL0 with the logical values shown in the equations (1) to (8). The switches Sx3 and Sx4 are operated by the selection signal, and the switches (23) to (30) are operated.
The switch Sx5 is operated by the selection signal sent by the selection circuit SEL2 with the logical value shown by the formula, and the switch Sx5 is operated by the selection signal sent by the selection circuit SEL1 with the logical value shown by the formulas (15) to (22).

Therefore, as compared with the third embodiment, it is possible to reduce the power consumption of the post-stage amplifiers AMP00 to AMP0n when writing data. 13, 14, and 15 are block diagrams of circuits showing a fifth embodiment of the present invention.

This embodiment is provided with a number of channels which requires a basic circuit having the same structure as the basic circuit of the first embodiment shown in FIGS. 1 to 3, and switches Sx1 to Sx5 are provided by the formulas (15) to (22) above. When the data is written, the switches SD1 to SD5 shown in FIG. 15 are operated by the selection signal sent by the selection circuit SEL1 with the logical value shown in FIG.
Head number H forming a pseudo basic circuit with x connected
The D # DMMY is operated.

In this embodiment, the resistance R of the magnetoresistive effect element is
By selecting and connecting mr0 to Rmrn and the resistance value of the reference resistance Rx, each resistance value of the reference resistance Rx is set to the average value of the resistance values of the magnetoresistive effect element, and thereby the terminal voltage fluctuation of the capacitor Cx. Can be reduced to 1/2 of the resistance deviation of the magnetoresistive effect element.

FIGS. 16, 17, and 18 are block diagrams of circuits showing a sixth embodiment of the present invention. This embodiment is shown in FIG.
From the pseudo basic circuit of the fifth embodiment shown in FIG. 5, as shown in FIG. 18, a post-stage amplifier AMP0D, a switch SD5,
By omitting the current source ID3, the power consumption at the time of writing data can be reduced as compared with the fifth embodiment.

FIG. 19, FIG. 20, and FIG. 21 are block diagrams of circuits showing a seventh embodiment of the present invention. This embodiment is shown in FIG.
From the pseudo basic circuit of the sixth embodiment shown in FIG. 8, the switches SD3 and SD4 and the current sources ID1 and I as shown in FIG.
Except for D2, the structure of the pseudo basic circuit is simple, and the switching speed at the time of reading or writing data can be increased because the number of switches is small.

FIGS. 22, 23 and 24 are block diagrams of circuits showing an eighth embodiment of the present invention. This embodiment is shown in FIG.
From the basic circuit of the first embodiment shown in FIG.
-Rn3, R04-Rn4, post-stage amplifier AMP00-A
MP0n, switches S03 to Sn3, S04 to Sn4
S05 to Sn5 and current sources I01 to In1 and I02 to I
As shown in FIG. 24, except for n2 and I03 to In3, resistors R3 and R4, switches S3, S4 and S5, current sources I1, I2 and I3, and a post-amplifier AMP are provided in a common part and shared by a plurality of basic circuits. It is something that is done.

The operation of the selection circuit SEL0 is the same as in the case of FIGS. 1 to 3, and as described in the first embodiment, when the basic circuit of the head number HD # 00 is selected at the time of reading data, the switch is switched. S01 and S02 operate, and at the time of data writing, the basic circuit of the head number HD # 07 is selected, the switches S71 and S72 operate, and the switches S3 to S6 operate at the time of data writing and reading. Therefore, the capacitor Cx is charged as in the first embodiment.

Therefore, the same effect as that of the first embodiment can be obtained with an economical structure. 25, 26 and 27
FIG. 11 is a block diagram of a circuit showing a ninth embodiment of the present invention.

In this embodiment, as in the case of the eighth embodiment,
From the basic circuit, the resistors R03 to Rn3, R04 to Rn4,
Post amplifier AMP00-AMP0n, switch S03-
Sn3, S04 to Sn4, S05 to Sn5 and current source I
27, except resistors 01 to In1, I02 to In2, and I03 to In3, resistors R3 and R4, switches S3, S4 and S5, current sources I1, I2 and I3, and a post-stage amplifier AMP are provided in the common part, as shown in FIG. It is designed to be shared by a plurality of basic circuits.

The operation of the selection circuit SEL0 is similar to that of the eighth embodiment, and the switch S5 is operated only by the read signal RG at the time of data reading. Therefore, compared with the eighth embodiment, It is possible to reduce the power consumption of the post-stage amplifier AMP when writing data.

The capacitor Cx is charged by the preamplifier operating during data writing and data reading, as in the eighth embodiment. 28, 29 and 30 are block diagrams of circuits showing a tenth embodiment of the present invention.

This embodiment is similar to the case of the eighth embodiment,
From the basic circuit, the resistors R03 to Rn3, R04 to Rn4,
Post amplifier AMP00-AMP0n, switch S03-
Sn3, S04 to Sn4, S05 to Sn5 and current source I
Except for 01 to In1, I02 to In2, and I03 to In3, resistors R3 and R4, switches S3, S4 and S5, current sources I1, I2 and I3, and a post-amplifier AMP are provided in the common part as shown in FIG. It is designed to be shared by a plurality of basic circuits.

Then, the switches S3, S4 and S5 are operated only by the read signal RG at the time of data read. Therefore, at the time of writing data, the current flows only in the magnetoresistive effect element of the channel other than the channel instructed to read the data, and the capacitor Cx
To charge. Therefore, compared with the eighth embodiment, the pre-stage amplifier and the post-stage amplifier AMP do not operate, so that the power consumption can be minimized.

FIGS. 31, 32 and 33 show the eleventh aspect of the present invention.
3 is a block diagram of a circuit showing an embodiment of FIG. In this embodiment, as in the case of the eighth embodiment, a resistor R03 is added to the basic circuit.
-Rn3, R04-Rn4, post-stage amplifier AMP00-A
MP0n, switches S03 to Sn3, S04 to Sn4
S05 to Sn5 and current sources I01 to In1 and I02 to I
Head numbers HD # DMM, excluding n2 and I03 to In3, and forming the pseudo basic circuit described in the fifth embodiment.
From the basic circuit of Y, the resistors RD3, RD4, the post-stage amplifier A
33. Except for MP0D, switches SD3, SD4, SD5 and current sources ID1, ID2, ID3, resistors R3 and R4, switches S3, S4 and S5, current sources I1, I2 and I3, and a post-stage amplifier are connected in common as shown in FIG. With AMP,
It is designed to be shared by a plurality of basic circuits and pseudo basic circuits.

The operation of the selection circuit SEL1 is the same as that of the fifth embodiment, and the switches S3, S4 and S5 have the write signal WG and the read signal R sent by the OR circuit OR.
Since G operates in both data writing and data reading, the same function as that of the fifth embodiment can be realized with an economical structure.

34, 35 and 36 show the twelfth aspect of the present invention.
3 is a block diagram of a circuit showing an embodiment of FIG. This embodiment differs from the eleventh embodiment in that the third switch S5 is operated by the read signal RG. Therefore, the eleventh
According to the embodiment described above, the post-stage amplifier AMP at the time of data writing
Power consumption can be reduced.

[0097]

As described above, according to the present invention, the electric charge of the capacitor is not discharged at the time of writing data, so that when the data is read by the designated channel again, the time during which the read state cannot be used can be shortened. I can.

Further, since the post-stage amplifier of the channel to be operated at the time of writing data is not operated, it is possible to shorten the time during which it cannot be used as the read state and to save the power consumption as in the above case.

Further, since only the MR head bias circuit can be switched, the number of switches to be switched is small, and it is not necessary to expect extra switching time, and the switching time can be shortened accordingly.

Further, since the pseudo amplification means is operated at the time of writing data, if the resistance value of the reference resistance is set to the average value of the resistance values of the magnetoresistive effect element, at the time of reading and writing of data. It is possible to reduce the voltage fluctuation of the capacitor due to the switching of 1 to 1/2 of the deviation of the resistance value of each magnetoresistive effect element, and the switching time can be further shortened accordingly.

Further, at the time of writing data, the power consumption can be reduced because the latter-stage amplifier of the pseudo-amplifying means does not operate. Further, since the structure of the pseudo-amplifying means can be further simplified, the switching speed at the time of reading or writing data can be increased.

Further, since the post-stage amplifier, the current source, the switch and the like are shared by a plurality of basic circuits, the above effect can be realized economically.

[Brief description of drawings]

FIG. 1 is a block diagram of a circuit showing a first embodiment of the present invention (No. 1)

FIG. 2 is a block diagram of a circuit showing the first embodiment of the present invention (Part 2).

FIG. 3 is a block diagram of a circuit showing the first embodiment of the present invention (part 3).

FIG. 4 is a block diagram of a circuit showing a second embodiment of the present invention (No. 1).

FIG. 5 is a block diagram of a circuit showing a second embodiment of the present invention (No. 2)

FIG. 6 is a block diagram of a circuit showing a second embodiment of the present invention (No. 3)

FIG. 7 is a block diagram of a circuit showing a third embodiment of the present invention (No. 1).

FIG. 8 is a block diagram of a circuit showing a third embodiment of the present invention (No. 2)

FIG. 9 is a block diagram of a circuit showing a third embodiment of the present invention (No. 3)

FIG. 10 is a block diagram of a circuit showing a fourth embodiment of the present invention (No. 1).

FIG. 11 is a block diagram of a circuit showing a fourth embodiment of the present invention (part 2).

FIG. 12 is a block diagram of a circuit showing a fourth embodiment of the present invention (part 3).

FIG. 13 is a block diagram of a circuit showing the fifth embodiment of the present invention (No. 1).

FIG. 14 is a block diagram of a circuit showing a fifth embodiment of the present invention (No. 2).

FIG. 15 is a block diagram of a circuit showing a fifth embodiment of the present invention (part 3).

FIG. 16 is a block diagram of a circuit showing a sixth embodiment of the present invention (No. 1)

FIG. 17 is a block diagram of a circuit showing a sixth embodiment of the present invention (part 2).

FIG. 18 is a block diagram of a circuit showing a sixth embodiment of the present invention (No. 3)

FIG. 19 is a block diagram of a circuit showing a seventh embodiment of the present invention (No. 1)

FIG. 20 is a block diagram of a circuit showing a seventh embodiment of the present invention (No. 2)

FIG. 21 is a block diagram of a circuit showing a seventh embodiment of the present invention (No. 3)

FIG. 22 is a block diagram of a circuit showing an eighth embodiment of the present invention (No. 1).

FIG. 23 is a block diagram of a circuit showing an eighth embodiment of the present invention (part 2).

FIG. 24 is a block diagram of a circuit showing an eighth embodiment of the present invention (part 3).

FIG. 25 is a block diagram of a circuit showing a ninth embodiment of the present invention (No. 1).

FIG. 26 is a block diagram of a circuit showing a ninth embodiment of the present invention (No. 2)

FIG. 27 is a block diagram of a circuit showing a ninth embodiment of the present invention (No. 3)

FIG. 28 is a block diagram (part 1) of a circuit showing a tenth embodiment of the present invention.

FIG. 29 is a block diagram of a circuit showing a tenth embodiment of the present invention (No. 2)

FIG. 30 is a block diagram of a circuit showing a tenth embodiment of the present invention (No. 3)

FIG. 31 is a block diagram of a circuit showing an eleventh embodiment of the present invention (No. 1).

FIG. 32 is a block diagram of a circuit showing the eleventh embodiment of the present invention (part 2).

FIG. 33 is a block diagram of a circuit showing an eleventh embodiment of the present invention (No. 3)

FIG. 34 is a block diagram (part 1) of a circuit showing a twelfth embodiment of the present invention.

FIG. 35 is a block diagram of a circuit showing a twelfth embodiment of the present invention (No. 2)

FIG. 36 is a block diagram of a circuit showing a twelfth embodiment of the present invention (No. 3)

FIG. 37 is a diagram for explaining the operation of FIGS. 1 to 3.

38 is a diagram for explaining the operation of FIGS. 4 to 6. FIG.

FIG. 39 is a diagram for explaining an example of a conventional MR head read circuit.

FIG. 40 is a block diagram (part 1) illustrating an example of a conventional technique.

FIG. 41 is a block diagram (part 2) illustrating an example of conventional technology.

FIG. 42 is a block diagram (part 3) illustrating an example of a conventional technique.

FIG. 43 is a diagram for explaining the waveform of each part when the read signal is turned on.

[Explanation of symbols]

 Q transistor R resistance I current source Cx capacitor Rmr resistance of magnetoresistive element OR OR circuit AMP amplifier SEL selection circuit S switch

Claims (7)

[Claims] 1. One of the terminals of the magnetoresistive effect element is connected to the base of one of the transistors (Q02 to Qn2), and the other terminal of the magnetoresistive effect element is connected to the other transistor (Q03 to Qn3).
Of the transistor (Q02
To Qn2) are connected to the first current source (I01 to In1) via the first switching means (S03 to Sn3), and the emitter of the other transistor (Q03 to Qn3) is connected to the second switching means. When the first and second switching means (S03 to Sn3) (S04 to Sn4) are operated by connecting to the second current source (I02 to In2) via (S04 to Sn4), the magnetoresistive effect The element is connected to a third current source (I03 to In3) through a third amplifier (S05 to Sn5) and a pre-stage amplifier configured to amplify a signal reproduced by the element, and the third selector.
When (S05 to Sn5) is operated, a bias voltage is applied via the second stage amplifier (AMP00 to AMP0n) that further amplifies the signal amplified by the previous stage amplifier and the fourth switching means (S01 to Sn1), and Transistors (Q01 ~
Qn1) and a plurality of amplifying means composed of a fifth switching means (S02 to Sn2) for connecting the magnetoresistive effect element to a fourth current source (Is). One of the transistors of the amplifying means (Q02 to Qn
One capacitor (C) commonly connected between the emitter of 2) and the emitter of the other transistor (Q03 to Qn3).
x), a sixth switching means (S06) for connecting each of the plurality of fifth switching means (S02 to Sn2) to the fourth current source (Is), and a sixth switching means (S06) for reading and writing data. 6 switching means (S06)
Based on the given selection signal, the sending means (OR) for sending the operation signal to the first to fifth switching means (S03 to Sn3) (S04 to Sn4) (S05 to Sn5) (S01 to Sn1) (S02 ~ Sn
Selection means (SEL0 to SEL2) that sends operation signals to 2) respectively
And an operating signal is sent to the first to fifth switching means of the required amplifying means at the time of reading the data, and other amplifying means excluding the necessary amplifying means at the time of writing the data. Of the operation signal to the first to fifth switching means, or when the data is read, the operation signal to the first, second, fourth and fifth switching means of the amplifying means which is required. At the same time as sending the operation signal to the third switching means of the necessary amplifying means, and when writing data,
The operation signal is sent to the first, second, fourth, and fifth switching means of the other amplification means except the required amplification means, or the required amplification means An operation signal is sent to the fourth and fifth switching means, and when writing data, an operation signal is sent to the fourth and fifth switching means of the other amplifying means except the necessary amplifying means, At the time of reading and writing data, an operation signal is sent to the first to third switching means of the necessary amplifying means, or at the time of reading data, the fourth and the fourth amplifying means of the necessary amplifying means. An operation signal is sent to the fifth switching means, and at the time of writing data, an operation signal is sent to the fourth and fifth switching means of the other amplifying means except the necessary amplifying means, and at the time of reading data. And when writing, the necessary amplification hand Of the MR head, wherein an operation signal is sent to the first and second switching means of the MR head and an operation signal is sent to the third switching means of the required amplifying means only when reading data. Readout circuit. 2. One terminal of the magnetoresistive effect element is connected to the base of one transistor (Q02 to Qn2), and the other terminal of the magnetoresistive effect element is connected to the other transistor (Q03 to Qn3).
Of the transistor (Q02
To Qn2) are connected to the first current source (I01 to In1) via the first switching means (S03 to Sn3), and the emitter of the other transistor (Q03 to Qn3) is connected to the second switching means. When the first and second switching means (S03 to Sn3) (S04 to Sn4) are operated by connecting to the second current source (I02 to In2) via (S04 to Sn4), the magnetoresistive effect The first pre-amplifier configured to amplify the signal reproduced by the element and the third current source (I03 to In3) through the third switching means (S05 to Sn5) are connected to the third current source (I03 to In3). When the switching means (S05 to Sn5) of No. 1 operate, the first post-stage amplifier (AMP00 to No. 00-) that further amplifies the signal amplified by the first pre-stage amplifier.
AMP0n), transistors (Q01 to Qn1) supplied with a bias voltage via the fourth switching means (S01 to Sn1) and supplying a current to the magnetoresistive effect element, and the magnetoresistive effect element
A plurality of amplifying means composed of the fifth switching means (S02 to Sn2) connected to the current source (Is) of the above, and one terminal of the reference resistance (Rx) to one transistor (QD2)
The other end of the reference resistor (Rx) to the base of another transistor (QD3), and the emitter of the one transistor (QD2) to the seventh switching means (SD3).
Is connected to a fifth current source (ID1) via a switch, and the emitter of the other transistor (QD3) is connected to a sixth current source (ID2) via an eighth switching means (SD4). When the 7th and 8th switching means (SD3) (SD4) operate, the second pre-stage amplifier configured to amplify the output of the reference resistance (Rx) and the 9th switching means (SD5) Connected to the 7th current source (ID3) via
When the ninth switching means (SD5) operates, a second post-stage amplifier (A) that further amplifies the signal amplified by the second pre-stage amplifier
MP0D), a transistor (QD1) supplied with a bias voltage through the tenth switching means (SD1) and supplying a current to the reference resistance (Rx), and the reference resistance (Rx) connected to the fourth current source. (I
and a pseudo amplification means composed of an eleventh switching means (SD2) connected to (s)), the one of the transistors (Q02 to Qn) of the plurality of amplification means.
2) and the one transistor (QD
One capacitor (Cx) commonly connected between the emitter of 2) and the emitters of the other transistors (Q03 to Qn3) of the plurality of amplifying means and the other transistor (QD3) of the pseudo amplifying means. ), And the fifth switching means (S02 to Sn2) of the plurality of amplifying means and the eleventh switching means (SD2) of the pseudo-amplifying means are respectively connected to the fourth current source (Is). 6 switching means (S0
6) and the sixth switching means (S06) when reading and writing data
And a first means for transmitting the operation signal to the first to fifth switching means of the amplification means, which is required, on the basis of the selection signal given at the time of reading the data. A selection means (SEL1) is provided, and when reading data, an operation signal is sent to the first to fifth switching means of the necessary amplifying means, and when writing data, the seventh amplifying means of the pseudo amplifying means. ~ 11th
A read circuit for an MR head, which sends an operation signal to the switching means (SD1 to SD5). 3. One of the terminals of the magnetoresistive effect element is connected to the base of one of the transistors (Q02 to Qn2), and the other terminal of the magnetoresistive effect element is connected to the other transistor (Q03 to Qn3).
Of the transistor (Q02
To Qn2) are connected to the first current source (I01 to In1) via the first switching means (S03 to Sn3), and the emitter of the other transistor (Q03 to Qn3) is connected to the second switching means. When the first and second switching means (S03 to Sn3) (S04 to Sn4) are connected to the second current source (I02 to In2) via (S04 to Sn4), the magnetoresistive effect is produced. The first pre-amplifier configured to amplify the signal reproduced by the element and the third current source (I03 to In3) through the third switching means (S05 to Sn5) are connected to the third current source (I03 to In3). Rear-stage amplifiers (AMP00-AMP0n) for further amplifying the signal amplified by the first front-stage amplifier when the switching means (S05-Sn5) of FIG.
A transistor (Q01 to Qn1) supplied with a bias voltage through the fourth switching means (S01 to Sn1) to supply a current to the magnetoresistive effect element, and the magnetoresistive effect element to a fourth current source ( A plurality of amplifying means composed of fifth switching means (S02 to Sn2) connected to (Is) and one terminal of the reference resistance (Rx) to one transistor (QD2)
The other end of the reference resistor (Rx) to the base of another transistor (QD3), and the emitter of the one transistor (QD2) to the seventh switching means (SD3).
Is connected to a fifth current source (ID1) via a switch, and the emitter of the other transistor (QD3) is connected to a sixth current source (ID2) via an eighth switching means (SD4). When the 7th and 8th switching means (SD3) (SD4) operate, the second pre-stage amplifier configured to amplify the output of the reference resistance (Rx) and the 9th switching means (SD1) are connected. A transistor (QD1) supplied with a bias voltage via the transistor (QD1) for supplying a current to the reference resistor (Rx), and a tenth switching means (SD2) for connecting the reference resistor (Rx) to the fourth current source (Is). ) And a pseudo-amplifying means including a plurality of amplifying means, the one of the transistors (Q02 to Qn
2) and the one transistor (QD
One capacitor (Cx) commonly connected between the emitter of 2) and the emitters of the other transistors (Q03 to Qn3) of the plurality of amplifying means and the other transistor (QD3) of the pseudo amplifying means. ), And the fifth switching means (S02 to Sn2) of the plurality of amplifying means and the tenth switching means (SD2) of the pseudo-amplifying means are respectively connected to the fourth current source (Is). 6 switching means (S0
6) and the sixth switching means (S06) when reading and writing data
And an selecting means (OR) for sending an operation signal to the first to fifth switching means of the amplifying means, which is required, based on a selection signal given when reading data. SEL1) are provided, an operation signal is sent to the first to fifth switching means of the necessary amplifying means at the time of reading data, and the seventh to tenth of the pseudo amplifying means at the time of writing data.
A read circuit for an MR head, wherein an operation signal is sent to the switching means (SD1 to SD4). 4. One of the terminals of the magnetoresistive effect element is connected to the base of one of the transistors (Q02 to Qn2), and the other terminal of the magnetoresistive effect element is connected to the other transistor (Q03 to Qn3).
Of the transistor (Q02
To Qn2) are connected to the first current source (I01 to In1) via the first switching means (S03 to Sn3), and the emitter of the other transistor (Q03 to Qn3) is connected to the second switching means. When the first and second switching means (S03 to Sn3) (S04 to Sn4) are operated by connecting to the second current source (I02 to In2) via (S04 to Sn4), the magnetoresistive effect The element is connected to a third current source (I03 to In3) through a third amplifier (S05 to Sn5) and a pre-stage amplifier configured to amplify a signal reproduced by the element, and the third selector.
When (S05 to Sn5) is operated, a bias voltage is applied via the second stage amplifier (AMP00 to AMP0n) that further amplifies the signal amplified by the previous stage amplifier and the fourth switching means (S01 to Sn1), and Transistors (Q01 ~
Qn1) and a plurality of amplifying means composed of a fifth switching means (S02 to Sn2) for connecting the magnetoresistive element to the fourth current source (Is), and one of the reference resistance (Rx). One transistor with one terminal (QD2)
An amplifier configured to connect the other terminal of the reference resistor (Rx) to the base of another transistor (QD3) and amplify the output of the reference resistor (Rx); A transistor (QD1), which is supplied with a bias voltage through the switching means (SD1) and supplies a current to the reference resistor (Rx), and the reference resistor (Rx) are connected to the fourth current source (Is). In a read circuit provided with a pseudo amplification means composed of an eighth switching means (SD2), the one of the transistors (Q02 to Qn) of the plurality of amplification means is provided.
2) and the one transistor (QD
One capacitor (Cx) commonly connected between the emitter of 2) and the emitters of the other transistors (Q03 to Qn3) of the plurality of amplifying means and the other transistor (QD3) of the pseudo amplifying means. ), And the fifth switching means (S02 to Sn2) of the plurality of amplifying means and the eighth switching means (SD2) of the pseudo-amplifying means are respectively connected to the fourth current source (Is). 6 switching means (S06)
And the sixth switching means (S06) when reading and writing data
And a selection means (OR) for transmitting an operation signal to the required third to fifth switching means of the amplification means based on the selection signal given when reading data. SEL1), and a selecting means (SEL2) for sending an operation signal to the first and second switching means of the amplifying means, which is required, based on a given selection signal when reading and writing data. When the data is read, an operation signal is sent to the first to fifth switching means of the required amplification means, and when the data is written, the first amplification means of the required amplification means is sent.
And a second switching means and a seventh and an eighth switching means (SD1, SD2) of the pseudo-amplifying means for sending operation signals to the MR head read circuit. 5. One terminal of the magnetoresistive element is connected to the base of one transistor (Q02 to Qn2), and the other terminal of the magnetoresistive element is connected to the other transistor (Q03 to Qn3).
Of the transistor (Q02
To Qn2) are connected to the first current source (I1) via the first switching means (S3) sharing the emitter, and the other transistor (Q
(03-Qn3) is connected to the second current source (I2) through the second switching means (S4) which shares the emitter, and the first and second switching means (S3) (S4) are operated. At this time, a bias voltage is applied through a pre-stage amplifier configured to amplify a signal reproduced by the magnetoresistive effect element and fourth switching means (S01 to Sn1), and a current is supplied to the magnetoresistive effect element. Transistor
(Q01 to Qn1) and the magnetoresistive effect element as a fourth current source (Is)
In a read circuit having a plurality of amplifying means composed of a fifth switching means (S02 to Sn2) connected to the third current source (I3) via a third switching means (S5) When the third switching means (S5) operates, a post-stage amplifier (AMP) that further amplifies the signal amplified by the pre-stage amplifier of each of the amplifying means, and the one transistor ( Q02 ~ Qn
One capacitor (C) commonly connected between the emitter of 2) and the emitter of the other transistor (Q03 to Qn3).
x), a sixth switching means (S6) for connecting each of the plurality of fifth switching means (S02 to Sn2) to the fourth current source (Is), and based on a given selection signal, Selection means (SEL0) for sending operation signals to the fourth and fifth switching means (S01-Sn1) (S02-Sn2), respectively, and the first, second and third for reading and writing data.
And send an operation signal to the sixth switching means (S3 to S6),
Alternatively, an operation signal is sent to the first, second and sixth switching means (S3, S4, S6), or an operation signal is sent to the sixth switching means (S6) (OR ), And, when data is read, an operation signal is sent to the fourth and fifth switching means of the required amplifying means, and when writing data, other amplification except for the necessary amplifying means is performed. An operation signal is sent to the fourth and fifth switching means of the means, or at the time of reading data, an operation signal is sent to the fourth and fifth switching means of the amplifying means which is required, Whether an operation signal is sent to the third switching means (S5) and, at the time of writing data, an operation signal is sent to the fourth and fifth switching means of other amplifying means except the necessary amplifying means. Or, at the time of reading data, the fourth and fifth switching means of the amplifying means required. The operation signal to the first, second and third switching means (S3, S4, S5), and at the time of writing the data, the other amplifying means except for the necessary amplifying means. A read circuit for an MR head, characterized in that an operation signal is sent to the fourth and fifth switching means of the amplifying means. 6. One of the terminals of the magnetoresistive effect element is connected to the base of one of the transistors (Q02 to Qn2), and the other terminal of the magnetoresistive effect element is connected to the other transistor (Q03 to Qn3).
Of the transistor (Q02
To Qn2) are connected to the first current source (I1) via the first switching means (S3) sharing the emitter, and the other transistor (Q
(03-Qn3) is connected to the second current source (I2) through the second switching means (S4) which shares the emitter, and the first and second switching means (S3) (S4) are operated. At this time, a bias voltage is applied through a pre-stage amplifier configured to amplify a signal reproduced by the magnetoresistive effect element and fourth switching means (S01 to Sn1), and a current is supplied to the magnetoresistive effect element. Transistor
(Q01 to Qn1) and the magnetoresistive effect element as a fourth current source (Is)
A plurality of amplifying means composed of the fifth switching means (S02 to Sn2) connected to and one terminal of the reference resistance (Rx) is one transistor (QD2)
The other end of the reference resistor (Rx) is connected to the base of another transistor (QD3), and the emitter of the one transistor (QD2) is connected to the first switching means (S).
3) is connected to the first current source (I1), and the emitter of the other transistor (QD3) is connected to the second current source (I2) via the second switching means (S4). , A pseudo pre-amplifier configured to amplify the output of the reference resistor (Rx) when the first and second switching means (S3) (S4) operate, and a seventh switching means (SD1) A bias voltage is applied via
And a pseudo-amplifying means comprising a transistor (QD1) for supplying a current to (Rx) and an eighth switching means (SD2) for connecting the reference resistance (Rx) to the fourth current source (Is). In a read circuit including: a third current source (I3) connected through a third switching means (S5), when the third switching means (S5) operates, the amplification means of The signal amplified by the pre-amplifier, the post-amplifier (AMP) that further amplifies the signal amplified by the pseudo-pre-amplifier of the pseudo-amplifying means, and the one transistor (Q02 to Qn of the plurality of amplifying means.
2) and the one transistor (QD
A capacitor (Cx) commonly connected between the emitter of 2) and the emitters of the other transistors (Q03 to Qn3) of the plurality of amplifying means and the other transistor (QD3) of the pseudo amplifying means. And a fifth switching means (S02 to Sn2) of the plurality of amplifying means and an eighth switching means (SD2) of the pseudo-amplifying means connected to the fourth current source (Is), respectively. Switching means (S6)
When reading and writing data, the first, second and third
And a sending means (OR) for sending an operation signal to the sixth switching means (S3, S4, S5, S6), and the necessary amplifying means based on a given selection signal only when reading data. Selection means (SEL1) for sending operation signals to the fourth and fifth switching means are provided, and the seventh and eighth switching means (SD1, SD2) of the pseudo amplification means operate only when writing data. A read circuit of an MR head, which is characterized by transmitting a signal. 7. One of the terminals of the magnetoresistive effect element is connected to the base of one of the transistors (Q02 to Qn2), and the other terminal of the magnetoresistive effect element is connected to the other transistor (Q03 to Qn3).
Of the transistor (Q02
To Qn2) are connected to the first current source (I1) via the first switching means (S3) sharing the emitter, and the other transistor (Q
(03-Qn3) is connected to the second current source (I2) through the second switching means (S4) which shares the emitter, and the first and second switching means (S3) (S4) are operated. At this time, a bias voltage is applied through a pre-stage amplifier configured to amplify a signal reproduced by the magnetoresistive effect element and fourth switching means (S01 to Sn1), and a current is supplied to the magnetoresistive effect element. Transistor
(Q01 to Qn1) and the magnetoresistive effect element as a fourth current source (Is)
A plurality of amplifying means composed of the fifth switching means (S02 to Sn2) connected to and one terminal of the reference resistance (Rx) is one transistor (QD2)
The other end of the reference resistor (Rx) is connected to the base of another transistor (QD3), and the emitter of the one transistor (QD2) is connected to the first switching means (S).
3) is connected to the first current source (I1), and the emitter of the other transistor (QD3) is connected to the second current source (I2) via the second switching means (S4). , A pseudo pre-amplifier configured to amplify the output of the reference resistor (Rx) when the first and second switching means (S3) (S4) operate, and a seventh switching means (SD1) A bias voltage is applied via
And a pseudo-amplifying means comprising a transistor (QD1) for supplying a current to (Rx) and an eighth switching means (SD2) for connecting the reference resistance (Rx) to the fourth current source (Is). In a read circuit including: a third current source (I3) connected through a third switching means (S5), when the third switching means (S5) operates, the amplification means of The signal amplified by the pre-amplifier, the post-amplifier (AMP) that further amplifies the signal amplified by the pseudo-pre-amplifier of the pseudo-amplifying means, and the one transistor (Q02 to Qn of the plurality of amplifying means.
2) and the one transistor (QD
A capacitor (Cx) commonly connected between the emitter of 2) and the emitters of the other transistors (Q03 to Qn3) of the plurality of amplifying means and the other transistor (QD3) of the pseudo amplifying means. And a fifth switching means (S02 to Sn2) of the plurality of amplifying means and an eighth switching means (SD2) of the pseudo-amplifying means connected to the fourth current source (Is), respectively. Switching means (S6)
And at the time of reading and writing data, the first, second and sixth
Of the switching means (S3, S4, S6) to output the operation signal
R), and a selecting means (SEL1) for sending an operation signal to the fourth and fifth switching means of the amplifying means, which is required, on the basis of a given selection signal only when reading data, When writing data, an operation signal is sent to the seventh and eighth switching means (SD1, SD2) of the pseudo amplification means, and when reading data, an operation signal is sent to the third switching means (S5). A read circuit of an MR head, characterized in that