JPH07311637A - Battery driven computer - Google Patents

Abstract

PURPOSE:To provide a battery driven computer capable of providing operation environment wherein the intention of an operator is reflected. CONSTITUTION:This computer has a power management unit (detecting means) which detects the quantity of electricity supplied from a battery, a setup button (setting means) 4 which sets a shift to a power-saving mode, and a CPU (control means) which judges whether or not the quantity of electricity detected by the power management unit is large enough to drive the computer when the shift to the power-saving mode is set and shifts to the power-saving mode when it is judged that the quantity of electricity is not sufficient. Thus the setup button 4 is provided to give the operator the right to select whether the shift to the power-saving mode is made or not, and the method of battery usage wherein the intention of the operator is reflected is obtained.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to battery-powered computers.

[0002]

2. Description of the Related Art Conventionally, in many portable computers,
It has been announced that it can be driven by a battery. It is conceivable that these computers may be in a state where the amount of electric power supplied from the battery is reduced and further operation cannot be continued during the operation by the battery.

When such a state is encountered, the following method has been used to prevent the currently executing process from abnormally ending and data loss.

(1) A warning is given to an operator visually or audibly. In this case, the operator is required to perform an operation of normally ending the currently executed process while the battery can be used.

(2) The power saving mode is automatically entered. Usually, a method that does not lose the data being processed is often adopted even when the power saving mode is entered.
Among the methods, a typical method is shown below.

Only a minimal amount of power is consumed from the battery in order not to lose the data currently being processed. At this time, the power supply to the device that consumes much power is stopped.

A secondary battery is used. A secondary battery, which is not used when the computer is in normal use, is used to provide a minimum amount of power to prevent data loss.

All data being processed is recorded in the non-volatile memory. All data currently being processed is recorded in a non-volatile memory (disk device etc.) in which recorded data is not lost even when power is not supplied. After recording, the power supply to all devices (except the device for detecting the return instruction from the power saving mode from the user) is stopped.

[0009]

Generally, in the case of this kind of computer, in order to avoid the processing from being interrupted carelessly even at the time when the battery remaining amount warning is issued, in reality, it takes more than several minutes. Can be operated.

Considering this point, the above two methods will be examined.

In the case of (1), in principle, when the operator receives a warning, as described above, the operation for preventing data loss is started. However, if it is clear that the current process will be finished in a short time, the final result can be obtained by continuing the process without interruption. On the other hand, if the power supplied from the battery becomes low when the operator is not near the computer, the operator will lose the data being processed. Method (2) is effective in avoiding the loss of this data. By adopting this method, the operator can avoid losing the data being processed in any case. However, as described in the examination of (1), even when it is known that the processing will be completed in a short time, the operator is forced to shift to the power saving mode, and the operation being executed is interrupted. Will end up. Then, the operation must be continued until a sufficient electric power is supplied, that is, until a commercial power source is obtained or a charged battery is obtained. Either way,
It is hard to say that the method reflects the intention of the operator.

Therefore, the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a battery-driven computer capable of providing an efficient working environment in which the operator's intention is reflected.

[0013]

According to a first aspect of the present invention, there is provided a battery-driven computer, which is a battery-driven computer that can be driven by a battery, and a detection unit that detects the amount of electric power supplied from the battery and consumes power in a normal state. When the setting means for setting the transition to the power saving mode with less power and the transition to the power saving mode is set by the setting means, the amount of power detected by the detecting means is sufficient for driving the computer. It is characterized by having a control means for shifting to a power saving mode when it is judged whether or not it is not sufficient.

A battery-driven computer according to a second aspect of the present invention has an instruction means for instructing a compulsory shift to the power saving mode, and the control means, when the compulsory shift to the power saving mode is instructed. It is characterized by shifting to the power saving mode regardless of the remaining battery level.

[0015]

According to the battery-driven computer of the first aspect, by providing the setting means, it is possible to give the operator the right to select whether or not to shift to the power saving mode. Can be used as a battery usage method. That is, when it is determined that the operator is likely to lose the data being processed, the power saving mode is set. Also, if the operator wants to use the computer to the limit of the battery,
Set to not automatically switch to power saving mode.

According to the battery-driven computer of the second aspect, when the operator gives an instruction to forcibly shift to the power saving mode, the computer shifts to the power saving mode and holds the data currently being processed. can do.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a front side external view showing a first embodiment of a battery-driven computer of the present invention, FIG. 2 its rear side external view, and FIG. 3 is a rear side external view with a lid 1a removed. .

This battery-driven computer has a computer main body 1, and on the front side of the computer main body 1, as shown in FIG. 1, a power switch 2 of this computer and a forced shift to a power saving mode. Power saving mode button (Suspend / Resu)
me Button 3 and a setup button (Setup B) as a setting means for setting the transition to the power saving mode.
4), keyboard 5, C that displays various information
A display unit 6 such as an RT display and an IC card insertion slot 7 are provided, and a detachable lid 1a is provided on the back side of the computer body 1 as shown in FIG. In FIG. 3, a rechargeable battery 8 is arranged as shown in FIG.

The power switch 2 is a push switch. The power switch 2 can be turned on by pressing it once when it is not turned on, and turned off by pressing it once while it is turned on.

The power saving mode button 3 is the same push switch as the power switch 2. This button 3 in normal operating condition
Press once to switch to the power saving mode. When the button 3 is pressed once in the power saving mode, the power saving mode can be returned to the normal operation mode. The power saving mode will be described later.

The setup button 4 can change the operating state of the computer without ending the processing currently being executed. By pressing this setup button 4 once during normal operation of the computer, the operating clock of the computer is changed, and the power saving mode is entered when the power supplied from the battery 8 becomes low. Whether or not it can be set.

FIG. 4 is an enlarged view of the keyboard 5.

This keyboard 5 is escaped (ES
C) key 50, left control (CTRL) key 51,
Left alt (ALT) key 52, right alt (ALT) key 53, right control (CTRL) key 54, left arrow key 55, down arrow key 56, up arrow key 57, right arrow key 58 and enter key 59. Is equipped with.

The left arrow key 55 and the right arrow key 58 are collectively referred to as "left and right arrow keys", and the down arrow key 56 and the up arrow key 57 are collectively referred to as "up and down arrow keys".

FIG. 5 is a view showing an example of a setup screen displayed on the display unit 6 by pressing the setup button 4.

In the figure, reference numeral 60 represents the state of execution speed of the selected computer. Although not shown here, "Low" can be selected in addition to "High". As is generally known, slowing down the execution speed of a computer has the effect of reducing the power consumption of the battery 8. Further, in the figure, reference numeral 61 indicates a state of whether or not to shift to the power saving mode when the amount of power from the battery 8 becomes very small. "High" is highlighted in 60, indicating that the execution speed of the computer can be changed at present. These settings are changed using the arrow keys 55, 56, 57 and 58 on the keyboard 5. By pressing the left and right arrow keys 55 and 58, "Hi
The selection of "gh" and "Low" can be switched.
Further, the up and down arrow keys 56 and 57 on the keyboard 5 described above.
By operating, the selection can be made by selecting "System Speed".
d ”to“ Suspend up on Battery ”
It can be changed to -low ". Although not shown, “Su
In a state in which "spend up Battery-low" is selected, "Enabled" is highlighted. "Suspend up Battery-1
For "ow", "Disabled" can be selected although it is not shown as "Enabled". "Enable
In "d", when the amount of electric power from the battery 8 becomes very small, the mode automatically shifts to the power saving mode. If "Disabled" is selected, the power saving mode is not entered even if the amount of power from the battery 8 is very small. By operating the up and down arrow keys 56 and 57 again, "System
"Speed" can be selected. The setup mode is ended by pressing the escape key 50 on the keyboard 5 described above.

An IC card that can be used by the computer by inserting it from the IC card insertion slot 7 is a card that operates in the same manner as a normal storage medium for storing data such as a floppy disk. Normally, this type of card uses an SRAM (random access memory that does not require a write operation at any time), and therefore has a backup battery for holding the data in the card. The IC card will be described later.

When the battery 8 has sufficient power stored therein, the computer can operate for about 2 to 3 hours without connecting the plug 1b to the outlet of the commercial power source. ing. If the plug 1b is connected to a commercial power outlet, the battery 8 is charged regardless of whether the power of the main body 1 is turned on. This battery 8 is removable. Therefore, it is possible to replace the fully charged battery 8 in place of the battery 8 that consumes power and cannot be supplied any more. The difference in operating time when the battery 8 is used depends on how much the movable part is used. In the case of this computer, the main cause is the usage status of the fixed disk device (HDD) 102 of FIG. 6 which will be described later.

FIG. 6 is a block diagram showing the control system of the computer.

This computer controls the operation of this computer, and at the same time, a CPU (central processing unit) as a control means for executing a shift to the power saving mode in a predetermined case.
100, IPM 101, fixed disk device (HDD) 1
02, chipset (M1219) 103, speaker 104, bus transceiver (ACT245) 105
a, 105b, chip set (M1215) 106, address mapping logic (ADDRESS MAPP)
ING LOGIC) 107, a power management unit (PMU) 108 as a detection means for detecting the amount of electric power from the battery 8, a program memory (BIOS)
109, memory module (SIMM: Single
Inline Memory Module) 110,
Floppy disk drive (FDD) 111, serial transfer port (SERIAL PORT) 112, parallel transfer port (PARALLEL PORT) 1
13, I / O controller (M5105) 114, keyboard controller (8751FA) 115, key data creation unit (8042) 116, display controller (VGA MODULE) 117, IC card controller (IC Card CONTROLLER) 118,
IC Card Socket (IC Card SOCKET)
119, SMI logic (SMI LOGIC) 12
0, memory clock generation unit (CMOS SRAM
The RTC) 121 and the keyboard (KB) 5 are provided.

BD is the data bus of the CPU 100, BA is the address bus of the CPU 100, CP as described above.
The UA is also the address bus of the CPU 100.

The IPM 101 monitors the address bus BA of the CPU 100, and when the change of the address bus BA and the CPU A is the same pattern, the CPU 10
By lowering the clock frequency of 0, power consumption is reduced.

The chip set 103 is a chip set for making this computer a so-called IBM compatible machine specification. The chipset 103 also drives the speaker 104. The speaker 104 is prepared to output a sound such as a buzzer.

The bus transceiver 105a is a bus transceiver which is a bidirectional buffer for the address bus.

The chipset 106 is the chipset 10
The same as 3.

The address mapping logic 107 generates address information which is input to the power management unit 108.

The power management unit 108 is
When there is no change in the address information from the address mapping logic 107, the DOZE mode in which the clock frequency of the CPU 100 is reduced to 1/8 of the normal frequency is executed, and when the computer is not operated for a certain period of time, the display unit 6 is displayed. The display control is performed to suppress the power consumption by turning off the display of, the remaining amount of the battery 8 is detected, the connection of the outlet of the commercial power source is detected, and the like.

The program memory 109 is a chip that stores a program of a part relating to basic input / output in the operation of the computer.

The memory module 110 is a module in which 4 MB of DRAM (Random Access Memory that requires occasional write operation) 110a that provides the main memory of the computer is mounted.

BHD and SD are local data buses and LA
SA is a local address bus.

The serial transfer port 112 has an RS23
It complies with 2C.

The parallel transfer port 113 complies with Centronics.

The I / O controller 114 includes the floppy disk drive 111 and the serial transfer port 1
12. It controls the parallel transfer port 113.

The keyboard controller 115 controls the keyboard 5 and creates information on the key pressed by the user. This keyboard controller 1
The key information created by 15 is the key data creation unit 11
6 is sent by the serial transfer method.

The key data creating unit 116 receives the data sent by the serial transfer method, creates the key data, and sends the key data to the local bus LASA.

The display controller 117 is a video graphic adapter (Video Graphic Ad).
control) to display an image on the display unit 6.

The IC card controller 118 controls the electrical connection of the IC card.

The IC card socket 119 is for inserting an IC card.

The SMI logic 120 has a high-order interrupt (SMI: System Management In).
). CPU100
Normally executes the program on the main storage unit 100a.
The SMI logic 120 generates a high-order interrupt (SMI) to change the computer settings, shift to the power saving mode, etc., even when the CPU 100 is executing a program on the main storage unit 100a. It is a thing. There are a plurality of SMIs, which are mutually exclusive. That is, while a certain SMI is generated and the processing of the SMI is in progress, the SMI cannot be generated even if the condition that another SMI can be generated is satisfied. Next SM
In order to generate I, the processing by the first SMI must be completed.

In the case of this computer, the power saving mode button 3
And pressing the setup button 4 causes SMI.
When the power saving mode button 3 is pressed, the power saving mode interrupt (Suspend
Button SMI), a setup interrupt generated by pressing the setup button 4 (SetupSM
The setup screen of FIG. 5 is displayed by the process of I). Also, when the amount of electric power from the battery 8 becomes low during driving by the battery 8, the battery low interrupt (Bat
tery Low SMI) occurs.

The memory clock generation unit 121 stores the contents set on the setup screen, and has a CMOS SRAM 121a held by a battery (not shown) different from the battery 8 shown in FIG.
al Time Clock) 121b.

The RTC 121b is for the CPU 100 to read date and time information when the computer is started. This RTC 121b is also a CMOS SRAM 121
It is operated by the same battery (not shown) as a. This battery (not shown) cannot be recharged.
The MOS SRAM 121a and the RTC 121b can be kept operating for about 5 years.

Here, the power saving mode will be described. The power saving mode is a mode provided for the purpose of extremely reducing power consumption. The condition for shifting to the power saving mode is that the power saving mode button 3 is pressed in the normal operation state or the amount of power of the battery becomes small.
Especially in the latter case, the transition to the power saving mode is automatically started. When the computer shifts to the power saving mode, it stops supplying power to functions other than those required for detecting the power saving mode button 3. Therefore, the power saving mode adopted in this computer is called “0V Suspend”. Of course, no power is supplied to the DRAM 110a for main memory. However, if the power supply to the DRAM 110a is stopped, the result of the processing being executed and the like also disappears. Therefore, the transition to power saving mode is DRA
All the information such as the contents on M110a and the contents of the registers of the CPU 100 are recorded in the fixed disk device 102. When returning from the power saving mode, the contents of the DRAM 110a, the contents of the register of the CPU 100, etc. recorded in the fixed disk device 102 immediately before the shift to the power saving mode are restored as described above. In this way, it is possible to completely return to the state before entering the power saving mode. In this way, when returning from the power saving mode, it is possible to return to the state before the power saving mode. Therefore, the return from the power saving mode is called Resume. Programs necessary for performing these processes are recorded in the program memory 109. Further, the storage area required to execute the program is SMM (System Management M).
A region called "emory" is used. When recording the contents of the DRAM 110a and the register of the CPU 100 in the fixed disk device 102, the address information of the recorded area is recorded in the CMOS SRAM 121a. At the beginning of recovery from the power saving mode, the CMOS SRAM12
The contents are read from 1a, and the contents are sequentially restored to the DRAM 110a and the register of the CPU 100, which are the areas in which the contents were originally stored.

FIGS. 7 and 8 show the transition to the power saving mode and the return from the power saving mode.

FIG. 7 shows the transition to the power saving mode. When the power saving mode button 3 is pressed, SMI occurs and a code different from the code currently being executed is executed. This code is the program memory (BIOS) 1
It corresponds to the code of the shaded part in 09. CP
The U100 executes the SMI for shifting to the power saving mode according to the code of the BIOS (FIG. 7, S1). First, the contents other than the area described as SMM in the DRAM 110a are recorded on the fixed disk 102 (FIG. 7, S2). Then, the content of the register of the CPU 100 is recorded (FIG. 7,
S3). When the recording is completed, the start address on the fixed disk device 102 is recorded in the CMOS SRAM 121a (S4 in FIG. 7). Furthermore, the end address is recorded (FIG. 7, S5). These start address and end address are used when returning from the power saving mode.

Next, FIG. 8 shows the return from the power saving mode. When the power saving mode button 3 is pressed, an SMI occurs, the shaded code in the program memory (BIOS) 109 is executed, and the return from the power saving mode is started (FIG. 8, S1). . First, CMOS S
A start address and an end address on the fixed disk device 102 are obtained from the RAM 121a (S2 in FIG. 8). The data on the fixed disk device 102 is read from the start address and continues until the end address. First of all, DRAM1
The contents of 10a are read out and returned to the DRAM 110a (FIG. 8, S4). Then, the value of the register of the CPU 100 is read and restored to the register (S in FIG. 8).
3). When the above process is completed, the state before the shift to the power saving mode can be returned as a result.

As is clear from the above description, since the contents of the DRAM 110a and the contents of the registers are stored in the fixed disk device 102 during the power saving mode, the information will not be lost even if the power supply is stopped.

Next, an IC card which can be connected to the computer embodying the present invention will be described with reference to FIGS. 9 to 14.

FIG. 9 is a top view of the IC card, FIG. 10 is a front view thereof, FIG. 11 is a bottom view thereof, and FIG.
FIG. 13 is a diagram for explaining the operation of the write inhibit switch 72, and FIG. 14 is a block diagram of the IC card.

SR where the IC card is a storage element
A memory card centered on AM.

This IC card has a thin and flat case 70.
And a 68-pin female connector 71 arranged on the upper end surface of the case 70, and a write protect switch (Write Protect Switch) arranged on the lower end surface.
ch) 72, a built-in button type built-in battery 73 for supplying electric power for holding the contents of the SRAM, which is a memory element, and a support 74 for pulling out the built-in battery 73 for replacement. It has and.

The write-inhibit switch 72 is provided for the purpose of preventing the contents from being erased by an inadvertent erase command, like a normal floppy disk.

In the state shown in FIG. 11, the write inhibit switch 72 allows writing and erasing without limitation. In the case of the state of FIG. 13, writing and erasing are prohibited. The state of FIG. 13 is said to be the state where the write inhibit switch 72 is on. On the contrary, the state of FIG. 11 is expressed as an off state.

As shown in FIG. 14, the IC card includes a memory IC (Memory IC) 75, a gate array (Gate Array) 76, a backup controller (BackUp control) 77, and a memory card detection unit (Memory Card Dete).
action) 78.

The memory IC 75 is a central storage element of this IC card. The data written in this is held.

The gate array 76 is the IC card controller 1 of FIG. 6 via the IC card socket 119 of FIG.
The IC card controls the transfer of data to and from the IC card 18.

The write protect switch 72 is as described above with reference to FIG. When the switch 72 is on, no writing or erasing operation can be performed on the memory IC 75.

The backup controller 77 outputs the power supply amount from the internal battery 73 to BVD1 and BVD2 as a digitized signal.

In the memory card detecting section 78, when this IC card is inserted into the IC card insertion slot 7 of the computer,
When it is connected to the IC card socket 119, it informs the computer that the memory card has a memory function.

Data is a data bus to which data is sent when writing data to and reading data from an IC card, Address is an address bus through which address information is exchanged, and CE (negative logic) is stored in the memory IC 75 via the gate array 76. Chip E for selecting
The enable signal and OE (negative logic) indicate that this IC card is in a data output state, Output Enable.
The le signal and WE (negative logic) are the Write Enable signal and RE indicating that the IC card is in a writing state.
G (negative logic) is a control line used when reading control information such as a card writing procedure from the IC card. When this control line is activated, the IC card allocates the above-mentioned data bus and address bus to the area in which the above-mentioned control information is recorded. The computer can refer to the above-mentioned control information instead of the contents of the memory IC 75. BVD
1 and BVD2 output the digitalized signal of the power supply amount of the backup power supply. CD1 (negative logic) and C
D2 (negative logic) is a card detection signal. Vcc is electric power supplied from the main body, and GND is ground.

If the computer is operated by using the electric power charged in the battery 8 shown in FIG. 3 without connecting the plug 1b to the commercial power outlet, the electric power charged in the battery 8 will be consumed in a few hours. Mostly consumed. In such a case, the battery low interrupt causes an SMI to save the contents of the DRAM 110a and the contents of the register and start the operation of shifting to the power saving mode.
It originates from logic 120. The detection that the remaining amount of power of the battery 8 necessary for the generation of the battery low interrupt is low is detected by the power management unit 1 of FIG.
Made by 08. When the remaining power of the battery 8 becomes low, the power management unit 108 sends a signal to the SMI logic 120. SMI logic 120
Generates an SMI for the CPU 100 as described above.

The processing after the occurrence of SMI will be described with reference to the flowchart of FIG.

When a battery low interrupt is generated, FIG.
61 “Suspend” set on the setup screen of
The setting of "upon Battery-low" is checked (S10). This setting is based on the CMOS SRA described above.
It is stored in the M121a. This setting is "Enable
"e", DRAM to execute the power saving mode
The contents of 110a and the contents of the register of the CPU 100 are recorded in the fixed disk device 102 (S11). When recording is completed, power saving mode (0V Suspend mode)
Enter (S12), and power saving mode (Suspen
d Mode) is continued (S13).

The 61 "Suspend up on Battery-lo" set on the setup screen of FIG.
When "w" is set to "Disable", the SMI is restored and the state before the normal SMI is generated is restored (S1).
4). After returning, go to step S15. In this case, processing can be performed as long as the power of the battery 8 can drive the computer. However, when the power supplied from the battery 8 becomes insufficient, the computer stops normal operation and the DRAM 110a being processed is being processed.
Loses the contents of.

Return from power saving mode (Resume)
Is performed by inserting a fully charged battery 8 or by connecting the plug 1b to an outlet of a commercial power source, and pressing the power saving mode button 3 after the computer is in a state in which it can supply the operable power. . Even if the power saving mode button 3 is pressed, the power saving mode cannot be restored unless a state in which sufficient power can be supplied.

The return from the power saving mode is explained by the flow chart of FIG. Power saving mode (0 V S
When the power saving mode button 3 is pressed during execution, a return interrupt (Resume SMI) is generated. However, in a state where no power is supplied from the battery 8, even if the power saving mode button 3 is pressed, the computer cannot operate at all. When the battery 8 supplies enough power to detect pressing of the power saving mode button 3, the process shown in the flowchart of FIG. 16 is started. If the power saving mode button 3 is pressed during execution of the power saving mode, a return interrupt occurs. In the next step S20 it is checked whether there is sufficient power to start the return. This is step S21
In order to drive the fixed disk device 102, which is a movable part and consumes a large amount of power. Step S2
When it is determined that there is not enough power to start the recovery at 0, the power saving mode (Suspend Mode)
Is continued (S24). If it is determined in step S20 that there is sufficient power, the CMOS SRAM of FIG.
The start address and the end address on the fixed disk device 102 stored in the memory 121a are read out, and the DRAM 1
The contents of 10a and the contents of the register are restored (S2
1). Then, the SMI is ended (S22). Then, the normal operation is started according to the restored contents of the DRAM 110a and the contents of the register (S23).

Even when sufficient power remains in the battery 8, the operator can shift to the power saving mode (0V Suspend) by pressing the power saving mode button 3. This is to prevent the operator from wasting power while not using the computer. Of course, after returning from the power saving mode, the work before that can be continued.

The shift to the power saving mode started by pressing the power saving mode button 3 has been described with reference to FIG.
It is a flowchart of.

Most of the processing is the same as the power saving mode started when the remaining power of the battery 8 is low. However, in the normal mode, the SMI started by the power saving mode button 3
Is a power saving mode interrupt. As I already explained,
Since the SMI operates exclusively, the power saving mode interrupt does not occur even if the power saving mode button 3 is intentionally pressed during the return interrupt.

Next, a second embodiment of the present invention will be described with reference to FIG. 17 and also with reference to FIG. FIG. 17 shows the battery 8
This is a screen displayed when the remaining amount of is low.

In the second embodiment, a means for notifying the operator when the remaining amount of power of the battery 8 is low is added to the first embodiment.

The first embodiment is the process in which the remaining power of the battery 8 becomes small and the signal is sent to the CPU 100 of FIG. 6 after being detected by the power management unit 108 to generate a battery low interrupt (Battry Low SMI). Similar to the example.

After the occurrence, a description will be added using the flowchart of FIG. When a battery low interrupt occurs,
Notify the operator that the remaining battery power is low (S
30). In this notification method, a warning sound such as a buzzer sound may be generated from the speaker 104, and the display unit 6 may display a warning sound.
A warning message 62 may be displayed as shown in FIG.
This warning message 62 is displayed for 1 second. After the display, the screen before the warning message 62 is displayed is displayed again. In either method, it is sufficient for the operator to recognize that the battery 8 has a low remaining power. Then step S3
In step 1, 61 "Su" set in the setup screen of FIG.
Check the setting of "send up on Battery Low". This setting is based on the CMOS SRAM described above.
It is stored in 121a. This setting is "Enable
In the case of "e", the contents of the main memory and the contents of the register of the CPU 100 are recorded in the fixed disk device 102 to execute the power saving mode (S32). After recording, enter the power saving (0V Suspend) mode (S3
3). And power saving mode (Suspend Mod
e) is continued (S34). The 61 "Suspend upon Batte" set in the setup screen of FIG.
When the setting of "ry-low" is "Disable", S
It returns from MI (S35) and returns to the operating state. Restarts the process that was being executed before the battery low interrupt. Then, the process proceeds to step S36. In this case, processing can be performed as long as the power of the battery 8 can drive the computer. However, when the power supplied from the battery 8 becomes insufficient, the computer stops normal operation and loses the contents of the main memory being processed. However, in the case of this computer, it takes about 10 minutes from the warning that the battery 8 is low to the time when the computer cannot actually operate.
The operator can stop the work and record the necessary contents of the main memory in the non-volatile memory (HDD, FD, etc.).

Next, a third embodiment of the present invention will be described with reference to FIGS. 19 and 20 and a flow chart of FIG. FIG. 19 is a screen displayed when the setup button 4 is pressed, and FIG. 20 is a screen asking whether to shift to the power saving mode.

When the remaining amount of the battery 8 becomes very small, the operator is notified at that time, and it is determined whether or not to shift to the power saving mode in the third embodiment. Is.

The process in which the remaining amount of the battery 8 becomes small, the signal is sent to the CPU 100 after being detected by the power management unit 108, and the battery low interrupt is generated is the same as in the first embodiment. Subsequently, description will be made with reference to the flowchart of FIG. When a battery low interrupt occurs, it notifies the operator. The method may be sound by the speaker 104 as shown in the second embodiment, or a message may be displayed on the display unit 6. After the warning message is displayed for 1 second, a message asking whether or not to shift to "0V Suspend" shown at 64 in FIG. 20 is displayed (S40). “YES” shown at 64 in FIG. 20 indicates that the power saving mode is entered. Here, when the operator presses the enter key 59, the process proceeds to step S41. When the operator presses the left arrow key 55 or the right arrow key 58, the "YE
The display of "S" changes to "NO". This is 0V Suspe
It means that it does not shift to nd. When the operator depresses the enter key 59 in this state, the step S41 is similarly performed.
Go to. By pressing the left arrow key 55 or the right arrow key 58 in the same manner while "NO" is displayed, the display of "NO" can be changed to "YES". In step S41 of FIG. 21, it is determined whether or not to shift to the power saving mode according to the operator's selection. When the operator selects "YES", the shift to the power saving mode is started. If the operator has selected "NO", the battery low interrupt is restored (S45) and the normal operation mode is returned to. If the operation is continued as it is, the battery runs out (S46).

When it is determined in step S41 that the shift to the power saving mode has been selected, the contents of the main memory and the contents of the register of the CPU 100 are recorded in the fixed disk device 102 in order to execute the power saving mode ( S42). When the recording is completed, the power saving mode is entered (S43). Then, the power saving mode is continued (S44).

When the setup button 4 is pressed in the third embodiment, the screen shown in FIG. 20 is displayed.
As shown in 63 of FIG. 19, the execution speed of this computer is selected as described in the first embodiment.

Next, a fourth embodiment of the present invention will be described with reference to FIGS. 22 and 23 and the flowchart of FIG. 22 is a front perspective view of the computer of the fourth embodiment, and FIG. 23 is a block diagram showing the control system of the fourth embodiment.

A switch 1 for setting whether or not to shift to the power saving mode when the remaining amount of the battery 8 becomes low.
The third embodiment is provided with 03a. As shown in FIG. 22, a suspend switch (Battery Low Suspend) 103a is provided on the front surface of the main body 1.
Was set up. FIG. 25 and FIG. 26 describe the usage state of the suspend switch 103a. When this suspend switch 103a is in the state of FIG. 25, it is in the open state, and when it is in the state of FIG. 26, it is in the connected state. When the suspend switch 103a is in the open state, the switch is pressed once to be in the connected state, and once in the connected state, the switch is in the opened state. The switch 103a can be operated regardless of the operating state of the computer. When the battery level becomes low in the connected state, a battery low interrupt is automatically generated, and the process of shifting to the power saving mode is started. This switch 103a is a chip set (M
1219) 103. In FIG. 23, Sus
Indicated as pend SW. Suspend switch 1
The CPU 100 detects the state of 03a and determines whether to shift to the power saving mode.

The process is shown in the flowchart of FIG.

The process in which the remaining amount of the battery 8 becomes small and the power management unit 108 detects the signal and then the signal is sent to the CPU 100 to generate the battery low interrupt is the same as in the first embodiment. Figure 24 after occurrence
The explanation will be added using the flowchart of FIG. When a battery low interrupt occurs, the operator is notified that the battery level is low (S50). This notification method is the same as in the second embodiment. Then, the suspend switch 103a
The status of is checked (S51). When this setting is ON, the contents of main memory, CPU
The contents of the register 100 are recorded in the fixed disk device 102 (S52). When the recording is completed, the power saving mode is entered (S53). Then, the power saving mode is continued (S5
4). When the setting of the suspend switch 103a is in the open state, the SMI is restored and the operating state is restored (S55).
Restarts the process that was being executed before the battery low interrupt. Then, the process proceeds to step S56. In this case, processing can be performed as long as the battery power can drive the computer.

According to this embodiment, the battery 8
The following effects can be expected by giving the operator the choice of whether or not to shift to the power saving mode when the remaining battery level becomes very low in a computer that can be driven by.

When the battery level becomes low, the computer has conventionally been forced to shift to the power saving mode, and the operator has to interrupt the work. Normally, a sufficient amount of power is left to avoid losing the data being processed due to careless battery exhaustion (a further 10 minutes or more of operation is possible even after it is determined that the battery level is low). . Therefore, even if it was known that the current work would be completed within a few minutes, the middle stage of the work was forced. However, by giving the operator the right to switch to the power saving mode or not, if the operator determines that there is a high possibility that the data being processed will be lost, the power automatically switches to the power saving mode. Set as. Further, when the operator wants to use the computer up to the limit of the battery 8, it is possible to provide an efficient work environment, such as setting not to automatically shift to the power saving mode. There is.

[0096]

According to the invention described in claim 1 described above in detail, since the operator is given the right to select whether or not to shift to the power saving mode, the efficiency reflecting the intention of the operator is reflected. It is possible to provide a battery-powered computer that can provide a specific work environment.

According to the second aspect of the invention, when the operator gives an instruction to forcibly shift to the power saving mode, the power saving mode is entered and the data currently being processed is held. be able to.

[Brief description of drawings]

FIG. 1 is a front side external view of a first embodiment.

FIG. 2 is a rear side external view of the first embodiment.

FIG. 3 is a rear side external view of the first embodiment with a lid removed.

FIG. 4 is an enlarged view of the keyboard.

FIG. 5 is a diagram showing an example of a setup screen.

FIG. 6 is a block diagram showing a control system of the first embodiment.

FIG. 7 is a diagram for explaining a method of shifting to a power saving mode.

FIG. 8 is a diagram for explaining a method of returning from the power saving mode.

FIG. 9 is a top view of the IC card.

FIG. 10 is a front view of an IC card.

FIG. 11 is a bottom view of the IC card.

FIG. 12 is a front view of the IC card showing a state where the support body is pulled out.

FIG. 13 is a diagram for explaining the operation of the write protect switch of the IC card.

FIG. 14 is a block diagram of an IC card.

FIG. 15 is a flowchart showing the operation of the first embodiment.

FIG. 16 is a flowchart showing the operation of the first embodiment.

FIG. 17 is a diagram showing an example of a display screen in the second embodiment.

FIG. 18 is a flowchart showing the operation of the second embodiment.

FIG. 19 is a diagram showing an example of a display screen in the third embodiment.

FIG. 20 is a diagram showing an example of a display screen in the third embodiment.

FIG. 21 is a flowchart showing the operation of the third embodiment.

FIG. 22 is a front side external view of the fourth embodiment.

FIG. 23 is a block diagram showing a control system of a fourth embodiment.

FIG. 24 is a flowchart showing the operation of the fourth embodiment.

FIG. 25 is a perspective view of relevant parts for explaining the state of the suspend switch according to the fourth embodiment.

FIG. 26 is a perspective view of a main part for explaining a state of the suspend switch according to the fourth embodiment.

[Explanation of symbols]

 1 Computer Main Body 3 Power Saving Mode Button (Instruction Means) 4 Setup Button (Setting Means) 8 Battery 100 CPU (Control Means) 108 Power Management Unit (Detection Means)

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Claims (2)

[Claims] 1. A battery-driven computer that can be driven by a battery, and a detection unit that detects the amount of power supplied from the battery, and a setting unit that sets a transition to a power-saving mode in which power consumption is lower than in a normal state. ,
When the shift to the power saving mode is set by this setting means, it is determined whether or not the amount of power detected by the detection means is sufficient for driving the computer, and when it is determined that the amount of power is not sufficient, A battery-driven computer, comprising: a control unit that shifts to a power saving mode. 2. When the forced shift to the power saving mode is instructed, the control unit saves power regardless of the remaining battery level. The battery-operated computer according to claim 1, wherein the battery-operated computer shifts to a power mode.