JPH0730599A - Detection circuit - Google Patents

Abstract

PURPOSE:To improve the deterioration in a code error rate due to noise and to enhance the tracking performance with respect to phase fluctuation of a carrier in the detection circuit demodulating a digital modulation signal. CONSTITUTION:In order to extract a carrier component of a reception signal 11, the reception signal S11 is given to a multiplier 11 and a delay circuit 12, in which the signal is delayed and detected and its detection output is given to a discrimination device 13, where a sign is discriminated and the discriminated sign is subject to differential coding by a differential coder 14 and its output S13 and a reception signal S11* whose delay is compensated are multiplied by a multiplier 16. A phase correction circuit 17 monitors its phase change to correct the signal so that a phase change in the output signal is continuous when a discontinuous phase change is detected. The carrier component is given to a filter 18, from which a recovered carrier signal S16 is obtained and a reception signal S11** whose delay is compensated is detected and discriminated for the sign by a multiplier 20 and a discrimination device 21.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention is used in digital communications. Particularly, it relates to a detection circuit for demodulating a digital modulation signal.

[0002]

2. Description of the Related Art As a circuit for detecting a digital phase modulation signal, a delay detection circuit and a synchronous detection circuit have been conventionally known. FIG. 5 shows a conventional block configuration of the differential detection circuit, and FIG. 6 shows a conventional block configuration of the synchronous detection circuit.

The differential detection circuit shown in FIG. 5 has a multiplier 31,
The delay circuit 32 and the determiner 33 are provided, and the received signal S11
The differentially encoded digital phase modulation signal is input as. The delay circuit 32 delays the reception signal S11 by one transmission symbol time. The multiplier 31 multiplies the output of the delay circuit 32 and the received signal S11. The determiner 33 is the multiplier 3
The output of 1 is determined and the demodulated signal is output.

The synchronous detection circuit shown in FIG. 6 has a multiplier 31,
Judgment device 33, carrier extraction circuit 34 and filter 35
And a digital phase modulation signal is input as the reception signal S11. The multiplier 31 multiplies (detects) the reception signal S11 and the reproduction carrier signal S31 output from the filter 35, and outputs a detection output signal S32. Judge 3
3 determines the detection output signal S32 and outputs "0" or "1". The carrier extraction circuit 34 extracts a carrier component from the detection output signal S32, and the filter 35 increases the SN ratio of the extracted carrier component and supplies it to the multiplier 31 as a reproduced carrier signal S31. Received signal S11
Is a differentially encoded digital phase modulated signal,
The output of the determiner 33 is supplied to the difference calculation circuit, and the differential logic is solved to obtain a demodulated signal.

Further, in the case of the synchronous detection circuit, in order to remove the phase uncertainty of the modulation, the phase uncertainty which corrects the modulation phase of the input signal to the carrier extraction circuit 34 by using the fixed pattern information of the preamble and the like. Add a removal circuit,
A phase uncertainty removing circuit may be added to correct the modulation phase in the output signal of the determiner 33 using the synchronization word information or the like.

[0006]

However, in the conventional differential detection circuit, since the received signal delayed by one transmission symbol time is used as the reproduced carrier signal, the code error rate is deteriorated by the noise component contained in the received signal. There was a problem. On the other hand, in the synchronous detection circuit, since the reproduction carrier signal whose SN ratio is increased by the filter is used for detection, deterioration of the code error rate due to noise components can be avoided, but multiplication is performed from the multiplier via the carrier extraction circuit and the filter. Due to the influence of the delay in the feedback loop returning to the device and the time constant of the filter, the followability to the carrier phase fluctuation due to fading or the like is deteriorated, which causes a problem that the code error rate is deteriorated.

It is an object of the present invention to solve the above problems, to improve the deterioration of the code error rate due to noise, and to provide a detection circuit having a high trackability with respect to carrier phase fluctuations.

[0008]

The detection circuit of the present invention comprises a carrier extracting means for extracting a carrier component from a digitally modulated received signal, and an unnecessary frequency component from the extracted carrier component to generate a reproduced carrier signal. In a detection circuit including a filtering means for outputting, a detecting means for detecting a received signal using the reproduced carrier signal, and a judging means for judging a sign from an output signal of the detecting means, the carrier extracting means is a receiving signal. Demodulating means for differentially detecting the signal to determine its code, encoding means for differentially encoding the output code of this demodulating means, and the output of this encoding means and the received signal are multiplied to extract the carrier component. And a multiplication means.

It is desirable to provide a phase detection / correction means for monitoring the phase change of the output signal of the carrier extraction means and correcting the phase change of the output signal to be continuous when a discontinuous phase change is detected. .

When the received signal is a differentially encoded digitally modulated signal, it is preferable to further include a difference calculation circuit for performing a difference calculation on the output code of the judging means.

A means for removing the uncertainty of the modulation phase of the output signal of the judging means or a means for removing the uncertainty of the modulation phase of the output signal of the demodulation means in the carrier reproducing means may be provided.

[0012]

[Function] The signal demodulated by the differential detection is differentially encoded,
The carrier component is extracted by multiplying it by the received signal. At this time, it is desirable to remove the phase discontinuity caused by the code error in the differential detection. The SN ratio is increased by passing the extracted carrier component through the filtering means to obtain a reproduced carrier signal. Detection and demodulation are performed using this reproduced carrier signal.

Since the reproduced carrier signal whose SN ratio is increased by the filtering means is used, the deterioration of the code error rate due to the noise component included in the received signal can be avoided. On the other hand, since there is no feedback loop in the circuit, it is possible to improve the followability with respect to carrier phase fluctuations due to fading or the like. Further, since there is no part that becomes a feedback loop, the influence of the time constant can be eliminated by adjusting the delay according to the time constant of the filter, and the followability can be further improved. At the same time, since there is no restriction by the time constant, the degree of freedom in the configuration of the filter increases.

[0014]

1 is a block diagram showing a detection circuit according to a first embodiment of the present invention.

The circuit of this embodiment is provided with a filter 18 as a filtering means for removing an unnecessary frequency component from the carrier component extracted from the digitally modulated received signal S11 and outputting a reproduced carrier signal, and uses this reproduced carrier signal. The multiplier 20 is provided as a detecting means for detecting the received signal by the receiver, and the determiner 21 is provided as a determining means for determining the sign from the output signal of the multiplier 20.

The feature of this embodiment is that the carrier component is extracted from the received signal S11. Therefore, the multiplier 11, the delay circuit 12, and the delay circuit 12 are provided as the demodulating means for detecting the received signal S11 by delay detection and determining the sign thereof. A determination unit 13 is provided, and a differential encoder 14 is provided as an encoding unit for differentially encoding the output code of the demodulation unit. The output of the differential encoder 14 is multiplied by the received signal to extract a carrier component. A phase detector for detecting the phase change of the output signal of the multiplier 16 and correcting the phase change of the output signal to be continuous when the discontinuous phase change is detected. This is because the phase correction circuit 17 is provided as a correction means. Multiplier 11, decision unit 13 and differential encoder 1
The delay circuit 15 delays the received signal S11 according to the delay time of 4 and the delay circuit 15 corresponding to the delay time of the multiplier 16, the phase correction circuit 17 and the filter 18.
And a delay circuit 19 for further delaying the output of.

A digital phase modulation signal as a reception signal S11 is input to this detection circuit and supplied to the multiplier 11 and the delay circuit 12. Multiplier 11 and delay circuit 1
2 delay-detects the received signal S11 and demodulates the signal S12.
Is output to the determiner 13. The determiner 13 determines the demodulated signal S
12 is determined to be a 0/1 code and output to the differential encoder 14. The differential encoder 14 differentially encodes the 0/1 code and outputs a coded signal S13.

The received signal S11 is also branched and supplied to the delay circuit 15. The delay circuit 15 receives the received signal S1
1 is delayed, and the reception signal S11 ^* is output in which the delay due to the multiplier 11, the determiner 13, and the differential encoder 14 is compensated.

The received signal S11 ^* is supplied to the differential encoder 14
Is input to the multiplier 16 together with the encoded signal S13 from The multiplier 16 extracts the carrier component by multiplying these two signals and outputs the extracted carrier signal S14 to the phase correction circuit 17. The phase correction circuit 17 monitors the phase change of the extracted carrier signal S14, and when it detects a point where the phase change becomes discontinuous, it judges that a phase discontinuity has occurred due to a code error at the time of differential detection, and the extracted carrier The phase of the signal S14 is 90 ° or −90 ° or 180 °
° Change. The output signal S15 of the phase correction circuit 17 is input to the filter 18, and the filter 18 raises the SN ratio of the output signal S15 and outputs it as a reproduced carrier signal S16.

The received signal S11 ^* is also branched and input to the delay circuit 19. The delay circuit 19 receives the received signal S1
1 ^* is further delayed to multiply multiplier 16 and phase correction circuit 17
And the delay due to the filter 18 is compensated, and the received signal S1
Output 1 ^** .

The received signal S11 ^** is input to the multiplier 20 together with the reproduced carrier signal S16. Multiplier 2
0 detects the reception signal S11 ^** by multiplying the reception signal S11 ^** by the reproduction carrier signal S16.
The output signal of the multiplier 20 is input to the determiner 21.
The determiner 21 determines this signal as a 0/1 code and outputs it as a demodulated signal.

FIG. 2 is a block diagram showing the detection circuit of the second embodiment of the present invention. In this embodiment, the received signal S11
Is a differentially encoded digital phase modulation signal, and is different from the first embodiment in that a differential operation circuit 22 for solving a differential logic is provided. The received signal S11 is differentially detected to demodulate the signal S
12, the received signal S11 ^** is multiplied by the reproduced carrier signal S16 to be detected by the same operation as in the first embodiment, and the 0/1 code is judged by the judging device 21. This 0
The differential arithmetic circuit 22 solves the differential logic of the / 1 code,
Output as a demodulated signal.

FIG. 3 is a block diagram showing the detection circuit of the third embodiment of the present invention. This embodiment differs from the first embodiment in that a phase uncertainty removing circuit 23 for removing the uncertainty of the modulation phase is provided. That is, the received signal S11 is delayed and detected to generate the demodulated signal S12, and the received signal S11 ^** is multiplied by the reproduced carrier signal S16 to be detected by the same operation as in the first embodiment, and the decision unit 21 determines 0. / 1 code is determined. The phase uncertainty removing circuit 23 removes the phase uncertainty included in the determined code. That is, the phase uncertainty removing circuit 23 removes the uncertainty of the modulation phase by using the synchronization word information included in the determined code.

FIG. 4 is a block diagram showing a detection circuit according to the fourth embodiment of the present invention. This embodiment differs from the third embodiment in that the uncertainty of the modulation phase is removed at the output of the differential encoder 14. That is, the reception signal S11 is subjected to delay detection to generate a demodulation signal S12, the determination unit 13 determines 0/1 code, and the differential encoder 14 performs differential encoding to obtain an encoded signal S13. The phase uncertainty removing circuit 24 removes the modulation phase uncertainty from the coded signal S13 using the preamble and other fixed pattern information and outputs the coded signal S13 ^* . The multiplier 16 produces the received signal S11 ^* and the encoded signal S13 ^* whose delays have been compensated by the delay circuit 15, the multiplier 11, the determiner 13, the differential encoder 14, and the phase uncertainty removing circuit 24. Multiply and extract the carrier component. Thereafter, a demodulated signal is obtained by the same operation as that of the first embodiment.

[0025]

As described above, the detection circuit of the present invention can detect a reproduction carrier whose filter has a higher SN ratio without using a feedback loop. Therefore, there is an effect that the deterioration of the code error rate due to noise can be improved, and a detection circuit having a high trackability with respect to the carrier phase fluctuation due to fading or the like can be realized.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a detection circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a detection circuit according to a second embodiment of the present invention.

FIG. 3 is a block configuration diagram showing a detection circuit according to a third embodiment of the present invention.

FIG. 4 is a block configuration diagram showing a detection circuit according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a conventional differential detection circuit.

FIG. 6 is a block configuration diagram showing a conventional synchronous detection circuit.

[Explanation of symbols]

 11, 16, 20, 31 Multiplier 12, 15, 19, 32 Delay circuit 13, 21, 33 Determiner 14 Differential encoder 17 Phase correction circuit 18, 35 Filter 22 Difference arithmetic circuit 23, 24 Phase uncertainty removal Circuit 34 Carrier extraction circuit

Claims (2)

[Claims] 1. Carrier extraction means for extracting a carrier component (S14) from a digitally modulated received signal, and filtering means (18) for removing an unnecessary frequency component from the extracted carrier component and outputting a reproduced carrier signal. In a detection circuit provided with a detection means (20) for detecting a received signal using the reproduced carrier signal, and a determination means (21) for determining a sign from the output signal of the detection means, the carrier extraction means comprises: Demodulation means (11 to 13) for delay-detecting the received signal to determine the code, encoding means (14) for differentially encoding the output code of the demodulation means, output of the encoding means and received signal And a multiplying means (16) for multiplying and by extracting a carrier component. 2. A phase detection correction means (17) for monitoring the phase change of the output signal of the carrier extraction means and correcting the phase change of the output signal so as to be continuous when a discontinuous phase change is detected. The detection circuit according to claim 1, further comprising: