JPH0730388A - Digitally controlled delay device and digitally controlled oscillation device - Google Patents

Abstract

PURPOSE:To obtain the oscillation device which can be controlled digitally. CONSTITUTION:The oscillation device is equipped with a data latch circuit 2 which outputs the high-order 17 bits and low-order 5 bits of external digital data CDI as control data CDH and CDL, a ring oscillator 4 which is constituted by connecting 32 inverting circuits in a ring shape and circulates pulse when a signal PI goes to a Hight level, a pulse selector 6 which takes pulses out of the inverting circuit at the position corresponding to the value of the CDL and outputs them as a clock signal CLK, and a down counter 8 which outputs a signal BOR when the counted value of the clock signal CLK coincides with the value of the CDH. Then an output control circuit 10 stops the ring oscillator 4 immediately once the signal BOR is outputted and places it in operation again after the elapse of a certain time T1 to generate an output pulse PO each time the signal BOR is outputted. Consequently, the output period of the output pulse PO can optionally be set with the digital data CDI.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital control delay device capable of digitally controlling a delay time, and a digital control oscillator device capable of digitally controlling an oscillation frequency using the digital control delay device.

[0002]

2. Description of the Related Art Conventionally, as a delay device capable of digital control, as disclosed in, for example, Japanese Patent Application Laid-Open No. 2-296410, a large number of delay elements composed of an integrating circuit and an inverting circuit (inverter) are continuously connected, There is known a delay device in which a signal to be delayed is input to the first-stage delay element and the output from each delay element is selectively taken out via a data selector.

[0003]

However, such a conventional delay device changes the delay time by selecting the delay element for extracting the delay signal from the continuously connected delay elements. As the variable range of 1 is increased, the number of delay elements increases, and there is a limit to increase the variable range of the delay time.

The present invention has been made in view of these problems, and provides a digital control delay device capable of digitally controlling the delay time in a wide range without increasing the number of delay elements, and the digital control delay device. It is an object of the present invention to provide a digitally controlled oscillator capable of digitally controlling the oscillation frequency by using the.

[0005]

That is, the invention as set forth in claim 1 made in order to achieve the above object is a digital control delay device capable of digitally controlling a delay time by inverting an input signal. A plurality of output inverting circuits are connected in a ring shape, and one of the inverting circuits is configured as a starting inverting circuit capable of controlling the inverting operation of the input signal by a control signal from the outside. A pulse circulation circuit that circulates a pulse signal with the start of the inverting operation of the startup inverting circuit, and digital data representing the connection position of a predetermined inverting circuit for extracting the pulse signal from the pulse circulation circuit from the external digital data. Pulse selecting means for selecting an inverting circuit corresponding to the pulse inverting circuit and extracting a pulse signal output from the selected inverting circuit, and the pulse selecting means. Counting to detect that a predetermined edge of the pulse signal taken out is detected, and that the count number has reached the digital data representing the number of revolutions of the pulse signal in the pulse circulation circuit in the digital data from the outside. And a means for outputting a detection signal when the count means detects that the count value has reached the digital data representing the number of revolutions, a digital control delay device comprising: According to a second aspect of the present invention, in the digital control delay device according to the first aspect, the pulse circulation circuit is composed of an even number of inverting circuits, and the pulse circulation circuit is arranged at equal intervals. Output terminals are provided for extracting output signals from the predetermined 2 ⁿ inverting circuits connected to each other, and the pulse select means is connected to the output terminals. The output signal from the output terminal is input in units of two in order from the one closer to the starting inverting circuit, and the signal closer to the starting inverting circuit or the one for starting is input based on 1-bit data from the outside. A lowermost select circuit group consisting of 2 ^n-1 select circuits that selectively outputs the signal not closer to the inverting circuit, and the output terminals of the lowermost select circuit group are sequentially connected in a hierarchical manner, Similarly to the above-mentioned select circuit, each of ⁿ selectable from 2 ⁿ⁻² to 1 select circuit that selectively outputs two input signals based on 1-bit data from the outside.
-1 upper select circuit group, and further, each bit from the least significant bit to the upper bit of the digital data representing the connection position of the inverting circuit is selected by each select circuit forming each select circuit group. The digital control delay device is characterized in that it is input to each select circuit in the order from the least significant select circuit group to the upper select circuit group consisting of the one select circuit as common 1-bit data to each select circuit. I am trying.

According to a third aspect of the present invention, there is provided a digital control oscillation device capable of digitally controlling an oscillation frequency, wherein the output means detects the digital control delay device according to the first or second aspect. When the signal is output, the operation of the starting inverting circuit is stopped, and after a lapse of a predetermined constant time, the starting inverting circuit is operated again to circulate the pulse signal in the pulse circulator circuit and to detect the detection signal. A gist of a digitally controlled oscillator characterized in that a circulating operation control means for outputting as an oscillation signal is provided.

[0007]

In the digital control delay device according to claim 1 configured as described above, when the control signal to be delayed is input from the outside, the inverting circuit for starting the pulse circulation circuit is input. The inversion operation of the signal is started, the output of each inversion circuit constituting the pulse circulation circuit is sequentially inverted, and the pulse signal circulates on the pulse circulation circuit.

Then, the pulse selecting means selects an inverting circuit corresponding to digital data representing a connection position of a predetermined inverting circuit for taking out a pulse signal from the pulse circulation circuit, from the digital data inputted from the outside,
The pulse signal output from the selected inverting circuit is taken out, the counting means counts a predetermined edge of the pulse signal taken out by the pulse selecting means, and the counted number is the pulse of the digital data inputted from the outside. It is detected that the digital data representing the number of circulations of the pulse signal in the circulation circuit has been reached. Then, when the count means detects that the count value has reached the digital data representing the number of revolutions, the output means outputs the detection signal.

That is, in the digital control delay device according to the first aspect, the time from the input of the control signal to the starting inverting circuit of the pulse circulation circuit to the output of the detection signal by the output means is the delay time. Therefore, this delay time is a fixed time (x · Td), the number of rounds N1 of the pulse signal in the pulse rounding circuit necessary to generate a predetermined edge counted by the counting means once, the total number of stages y of the inversion circuits constituting the pulse rounding circuit, and A fixed time (N1.y.Td) determined by the reversal operation time Td and the number of circulations N2 of the pulse signal counted by the counting means.
・ N2) and time (x ・ Td + N1 ・ y ・ T)
d * N2).

Therefore, according to the digital control delay device of the first aspect, the connection position of the inverting circuit for extracting the pulse signal and the number of rounds of the pulse signal counted by the counting means are determined by the digital data input from the outside. By changing it, it becomes possible to arbitrarily change the delay time of the detection signal with respect to the control signal.

As described above, the delay time of the detection signal is
The total number of connecting stages of the inverting circuit (x
+ N1 · y · N2), and the inversion operation time T of each inversion circuit
Although it is determined by d, as the inverting circuit, the one having an operation time of about 500 psec. is currently put into practical use, so that the delay time of the detection signal can be controlled with high resolution. That is, for example, the operating time of the inverting circuit is 500 pse
If the pulse signal is selectively taken out from each inverting circuit connected to the even-numbered stage or the odd-numbered stage counting from the startup inverting circuit, the delay time of 1 ns
It is possible to change in ec. units.

The controllable range of this delay time is
The minimum delay time of the pulse signal from the startup inverting circuit to the inverting circuit that extracts the pulse signal (if the pulse signal is extracted from the startup inverting circuit, the inverting operation time of the startup inverting circuit)
To the inverting circuit that extracts the pulse signal from the starting inverting circuit, the maximum delay time of the pulse signal (If the pulse signal is taken from the inverting circuit connected immediately before the inverting circuit for starting, Time to make one lap)
And a time obtained by multiplying the time interval at which an edge is counted by the counting means by the number of pulses that the counting means can count, up to a time obtained by adding the number of pulses that can be counted by the counting means without increasing the number of delay elements unlike the conventional delay device. The controllable range of the delay time can be set in a wide range.

Further, according to the digital control delay device of the first aspect, since the delay time is obtained by using only the inverting circuit forming the pulse circulation circuit, the inverting operation time Td is set in each inverting circuit. Even if there is a variation in, the delay time can be reliably increased / decreased in a stepwise manner corresponding to the digital data.

Further, according to the digital control delay device of the first aspect, an inverting circuit for taking out a pulse signal is first selected, and a predetermined edge of the pulse signal output from the selected inverting circuit is counted. Since the delay time is obtained by doing so, the above-mentioned effect can be obtained without particularly complicating the device configuration.

Here, as the configuration of the above-mentioned pulse selecting means, the output signals of a plurality of inverting circuits which are supposed to extract the pulse signals from the pulse circulation circuit in advance are connected to each other in a wired-OR format via a switching circuit. It is conceivable that a predetermined output signal is output to the counting means by decoding digital data from the outside and connecting only the switching circuit corresponding to the decoded value, but in this case, pulse select There is a problem that the circuit scale becomes large because the means must be provided with a decoder.

Therefore, in the digital control delay device according to the second aspect of the invention, the pulse circulation circuit is composed of an even number of inverting circuits, and the predetermined 2 ⁿ pieces are connected at equal intervals in the pulse circulation circuit. An output terminal for extracting an output signal from each of the inverting circuits is provided, and the pulse selecting means is further connected to the 2 ⁿ output terminals, and the output signal from the output terminal is closer to the starting inverting circuit. Two ^n-1 units each of which is sequentially input in units of 2 and selectively outputs a signal closer to the starting inverting circuit or a signal not closer to the starting inverting circuit based on 1-bit data from the outside. The lowest select circuit group composed of select circuits and the two signals input in the same manner as the select circuits constituting the lowest select circuit group are connected in hierarchical order to the output terminals of the lowest select circuit group. And each formed of the n-1 order select circuit group from the select circuit from 2 ^n-2 pieces of output alternatively to one based on the 1-bit data from the parts, and consists of digital data from the outside Each bit from the least significant bit to the most significant bit of the digital data representing the connection position of the inverting circuit is used as 1-bit data common to each select circuit constituting each select circuit group, and one bit from the least significant select circuit group is used. Input is made to each select circuit in order of the upper select circuit group including select circuits.

In the digital control delay device according to the second aspect of the present invention thus configured, the pulse selecting means is composed of n select circuit groups, and 2 ^{n-1 of the} select circuit groups. The lowest select circuit group consisting of individual select circuits is the first layer, that is, the lowest layer,
The upper select circuit group consisting of 2 ^n-2 select circuits is the second layer, the upper select circuit group consisting of 2 ^n-3 select circuits is the third layer, and so on. The upper select circuit group composed of the select circuits is the uppermost layer.

Then, the output signals of the predetermined 2 ⁿ inverting circuits connected at equal intervals in the pulse circulation circuit are supplied to the 2 ^n-1 select circuits in the lowermost layer via the output terminals. The select signal is input in units of two in order from the one closest to the inverting circuit for activation, and each select circuit inputs the input signal in units of two to the least significant bit of the digital data representing the connection position of the inverting circuit input from the outside. Based on the above, for example, when the bit is 0, the one closer to the startup inverting circuit is output, and conversely, when the bit is 1, the one not closer to the startup inverting circuit is output, and so on. .

On the other hand, in each of the 2 ^n-2 select circuits in the second layer, the output signal from each of the 2 ^n-1 select circuits in the lowermost layer corresponds to an inverting circuit close to the inverting circuit for activation. The signals are sequentially input in units of two, and each select circuit of the second layer inputs the input signal in units of two to the second bit of digital data representing the connection position of the inverting circuit input from the outside. Based on the above, just as in the case of the lowest layer, for example, when the second bit is 0, the one corresponding to the inverting circuit close to the activating circuit is output, and conversely when the second bit is 1, the inverting circuit for activating is output. Alternatively, output the one corresponding to the inverting circuit that is not near.

Then, each select circuit from the third layer to the uppermost layer inputs the output signal from the lower layer of its own in units of two, just like each select circuit of the second layer.
The input signal in units is selectively output based on each bit from the 3rd bit to the nth bit of the digital data, which represents the connection position of the inverting circuit input from the outside, and finally outputs the uppermost layer. The one select circuit outputs an output signal, that is, a pulse signal from the inverting circuit connected to the position corresponding to the digital data input from the outside.

More specifically, for example, when eight output terminals are provided in the pulse circulation circuit, the pulse select means has three select circuits each consisting of four, two and one select circuits. The circuit groups are hierarchically connected. Then, when "010" representing "2" is input from the outside as digital data representing the connection position of the inverting circuit, first, from each of the four select circuits in the lowermost layer, from the starting inverting circuit side, respectively. Counting 1,
Output signals from the 3rd, 5th and 7th output terminals are output,
Next, from each of the two select circuits in the second layer, output signals from the third and seventh output terminals counted from the starting inverting circuit side are output, and finally, in the third layer, that is, An output signal from the third output terminal counted from the start-up inverting circuit side is output from one select circuit in the uppermost layer. Similarly, when "110" representing "6" is input from the outside as digital data, the output from the 7th output terminal counted from the starting inverting circuit side is output from one select circuit in the uppermost layer. The signal is output. That is, each select circuit constituting the pulse select means outputs a signal closer to the inverting circuit for activation when each bit of the digital data inputted from the outside is 0, and vice versa.
When the signal closer to the inverting circuit for start-up is output at this time, the output signal having the number obtained by adding 1 to the value represented by the digital data is selected and the output signal is taken out.

Contrary to the above example, each select circuit constituting the pulse select means outputs a signal closer to the inversion circuit for activation when each bit of the digital data inputted from the outside is 1. On the contrary, even when the signal that is not close to the starting inverting circuit is output when each bit is 0, the output terminal closer to the starting inverting circuit is selected as the input digital data value is larger. Only the difference is that the output terminal is selected and the output signal is taken out in accordance with the digital data from the outside, just as in the case of the above example.

As described above, according to the digital control delay device of the second aspect, it is possible to deal with the digital data representing the connection position of the inverting circuit, which is input from the outside, without providing the pulse selecting means with a decoder. Since it becomes possible to select the inverting circuit to be output and take out the pulse signal output from the inverting circuit, the device can be configured without increasing the circuit scale.

According to the digital control delay device of the second aspect, the number of select circuits through which the pulse signal passes in the pulse select means is always the same until the pulse signal is taken out from the pulse circulation circuit. The delay time of the device can be reliably increased / decreased corresponding to the digital data without being affected by the delay time generated in the pulse selection means.

Further, in the digital control delay device according to the second aspect of the invention, the predetermined 2 ⁿ inversion circuits in the pulse circulation circuit selectively pulse according to the value of the digital data input from the outside. Since the signal is taken out, the lower n bits of the external digital data representing the delay time with respect to the control signal can be directly used as the digital data representing the connection position of the inverting circuit, and the external digital data can be used. The bits higher than the n-th bit can be used as they are as digital data representing the number of revolutions of the pulse signal.

Further, in the digital control delay device according to the second aspect of the invention, the pulse circulation circuit is composed of an even number of inverting circuits, and the pulse signal is taken out alternatively from the inverting circuits connected at equal intervals. Therefore, the delay between the inverting circuits for extracting the pulse signal becomes uniform, and the delay time of the detection signal with respect to the control signal can be controlled with uniform resolution.

Next, in a digital control oscillator according to a third aspect of the present invention, the digital control delay device according to the first or second aspect is provided with a loop operation control means, and the loop operation control means outputs the output means. When the detection signal is output, the operation of the startup inverting circuit in the pulse circulation circuit is stopped, and after a certain fixed time elapses, the startup inverting circuit is activated again to circulate the pulse signal in the pulse circulation circuit and detect it. The signal is output as an oscillation signal.

That is, in the digital control delay device according to the first aspect or the second aspect, the connection position of the inverting circuit for extracting the pulse signal and the number of revolutions of the pulse signal counted by the counting means are counted by externally input digital data. Since the delay time of the detection signal with respect to the control signal can be arbitrarily controlled by changing and, in the digitally controlled oscillator according to claim 3, each time the output means outputs the detection signal, only a predetermined fixed time is required. Repeat the operation of stopping the operation of the inverting circuit for start-up, once erasing the pulse signal in the pulse circulation circuit, and then operating the inverting circuit for start-up again to recirculate the pulse signal in the pulse circulation circuit. Control the detection signal output by the output means by using the digital control delay device according to claim 1 or 2. The time obtained by adding the predetermined constant time delay time with each other to be output as an oscillation signal with one period.

Therefore, according to the digital control oscillator of the third aspect, based on the digital data from the outside,
It becomes possible to control the output cycle of the detection signal, that is, the oscillation cycle in a wide range with the time resolution determined by the minimum variable time of the digital control delay device according to claim 1 or 2.

That is, the output frequency of the detection signal is determined by the number of revolutions of the pulse signal in the pulse circulation circuit if the connection position of the inverting circuit for extracting the pulse signal is fixed,
The more the number of turns, the lower the output frequency of the detection signal, and conversely, if the number of turns is reduced, the output frequency of the detection signal becomes a high frequency corresponding to the cycle of the pulse signal in the pulse circulation circuit. Therefore, the output frequency of the detection signal is roughly determined by the number of revolutions of the pulse signal, and the fine adjustment is performed by changing the connection position of the inverting circuit that extracts the pulse signal from the pulse circulation circuit. Can be digitally controlled with high resolution over a wide range of several Hz to several tens of MHz.

According to the digital control oscillator of the third aspect, as in the case of the digital control delay device of the first aspect or the second aspect, only the inverting circuit forming the pulse circulation circuit is used. Since the oscillation cycle of the detection signal is set by setting the oscillation cycle according to the digital data from the outside even if the inversion operation time Td varies among the inversion circuits forming the pulse circulation circuit. It is possible to surely increase or decrease in steps.

[0032]

Embodiments of the present invention will be described below with reference to the drawings. First, FIG. 1 is a block diagram showing the configuration of the digitally controlled oscillator according to the first embodiment.

As shown in FIG. 1, the digitally controlled oscillator of this embodiment has 22-bit digital data CDI and output pulse PO which represent a desired output period of a pulse signal (output pulse PO) output from the device and are described later. Control signal CDH (17
Bit) and CDL (5 bits) and a total of 32 inverting circuits are connected in a ring shape, and a pulse signal is circulated when a control signal PI, which will be described later, goes to a high level. A pulse signal is taken out from a ring oscillator 4 as a circuit and a predetermined inversion circuit in the ring oscillator 4 corresponding to the 5-bit control data CDL output from the data latch circuit 2, and the pulse signal is output as a clock signal CLK. The pulse selector 6 as the pulse selector and the clock signal CLK output from the pulse selector 6 counts the number of circulations of the pulse signal in the ring oscillator 4, and the count value is output from the data latch circuit 2. When it matches the 17-bit control data CDH, the detection signal BOR is set to low level. In output, the down-counter 8 as a count means and output means, the down counter 8
As soon as the detection signal BOR becomes low level, the ring oscillator 4 is stopped, the pulse signal is circulated again in the ring oscillator 4 after a predetermined fixed time, and the output pulse PO is output at the timing when the detection signal BOR becomes low level. And an output control circuit 10 as a circulating operation control means.

First, the ring oscillator 4 is constructed as shown in FIG. As shown in FIG. 2, the ring oscillator 4 includes two 2-input NAND gates NAND1 and 32 (hereinafter simply referred to as NAND gates) as inverting circuits.
And 30 inverters INV2 to 31. In each of these circuits, the output end of the previous stage is sequentially connected to the input end of the next stage in a ring shape, and the NAND gate NAND1 and the NAND gate NAND3 as the inverting circuit for activation are connected.
The control signal PI output from the output control circuit 10 is input to the input terminal that is not connected to 2 (hereinafter, this input terminal is referred to as a startup terminal), and the NAND gate NA
The output signal of the inverter INV18 is input to an input terminal of the ND32 that is not connected to the inverter INV31 (hereinafter, this input terminal is referred to as a control terminal). On the other hand, the output terminals of the inverting circuits connected to the odd-numbered stages counting from the NAND gate NAND1 have output terminals Q1 to Q1, respectively.
16 are provided, and these output terminals Q1 to Q16
Are sequentially connected to the pulse selector 6 as shown in FIG.

Here, the operation of the ring oscillator 4 thus constructed will be described with reference to FIG.
(A). First, in the initial state, that is, when the control signal PI from the output control circuit 10, which will be described in detail later, is at the Low level, the output P01 of the NAND gate NAND1 is at the High level. The output of the inverter becomes low level, and the output of the odd-numbered stage inverter becomes high level and becomes stable. In this initial state, the NAND gate NAND32
Since the output P18 of the inverter INV18 input to the control terminal of the
Only 32 is Hi even though it is connected to even-numbered stages
Output gh level. That is, with this configuration, both the input and output signals of the NAND gate NAND1 are
The control signal PI is set to Low level so that it becomes High level.
From the high level to the NAND gate NAN
D1 starts the inversion operation.

(B). Next, the control signal PI changes from Low to Hi.
When it changes to the gh level, the output P01 of the NAND gate NAND1 inverts from the High level to the Low level, so that the outputs of the succeeding inverters sequentially invert, and the output of the odd-numbered inverters changes from the High level to the Low level. The output of the inverter at the stage changes from Low to High level.
In the following description, the pulse signal generated by the change of the control signal PI and sequentially circulates on the ring oscillator 4 as a falling output of the odd-numbered inverting circuit and as a rising output of the even-numbered inverting circuit. Is called a main edge, and is indicated by a dot mark in FIG.

(C). When the main edge reaches the inverter INV18 and the output P18 of the inverter INV18 is inverted from low level to high level, the output level of the inverter INV31 is still at high level, so that the two input signals of the NAND gate NAND32 are both At the high level, the NAND gate NAND32 starts the inversion operation, and its output is inverted from the high level to the low level. In the following description, the main edge is input to the NAND gate NAND32 from the control terminal in this way, inverted by the NAND gate NAND32, and is output on the ring oscillator 4 as the rising output of the inversion circuit in the odd-numbered stage and in the even-numbered stage. An edge of a pulse signal that sequentially circulates as a falling output of the inverting circuit is called a reset edge, and is indicated by a cross mark in FIG. Then, this reset edge orbits on the ring oscillator 4 together with the main edge generated by the NAND gate NAND1.

(D). Also, the main edge after that,
Each of the following inverters from the inverter INV18 is sequentially inverted and transmitted, and the output of the inverter INV31 is output.
It is input to the NAND gate NAND32 by inverting from High level to Low level. At this time, the NAND gate N
Input signal of control terminal of AND32, that is, inverter I
Since the output signal of NV18 is High level,
The main edge is directly inverted by the NAND gate NAND 32 and each inverter after the NAND gate NAND 1, and is transmitted on the ring oscillator 4.

As described above, the main edge passes through the inverters INV19-INV31 to NAND gate NAND.
When reaching 32, the output signal of the inverter INV18 is still at the high level because the inverter INV19
While the number of inverters between ~ 31 is 13,
This is because the number of inverters including the NAND gates from the NAND gate NAND32 to the inverter INV18 is 19, so that the reset edge is faster than the reset edge is transmitted from the NAND gate NAND32 to the inverter INV18, and the main edge is the NAND gate NAND32.
Because it is input to.

(E). On the other hand, NAND gate NAND32
The reset edge generated by the NAND gate NA
The signal level of the control terminal of the NAND gate NAND32 is inverted from High to Low level after reaching the inverter INV18 again through each inverter including ND1. At this time, the input signal from the inverter INV31 of the NAND gate NAND32 is changed. , Because it is already at Low level due to the main edge, NAND gate NAN
The output of D32 does not change, and the reset edge is sequentially transmitted from the inverter INV18 to the NAND gate NAND32 by the normal route of the inverters INV19 to INV31.

(F). When the reset edge reaches the inverter INV31, the NAND gate NAND
The input signal from the inverter INV31 of 32 is inverted from Low level to High level. Also, almost at the same time,
The main edge reaches the inverter INV18, and the input signal of the control terminal of the NAND gate NAND32 is also inverted from Low to High level. This is the main edge
It starts from the NAND gate NAND1, goes around the ring oscillator 4 by a regular route, and then returns to the NAND gate NAN.
While passing through D1 and reaching the inverter INV18, the main edge of the reset edge is the NAND gate N.
It is generated by inverting operation of the NAND gate NAND32 after reaching the inverter INV18 from AND1.
This is because the total number of inverting circuits through which both edges pass until reaching the NAND gate NAND 32 is exactly the same as 50, such that the ring oscillator 4 makes one round along the regular route.

Here, in the ring oscillator 4 of the present embodiment, in the inverters INV19-31, the inversion response time of the even-numbered stage inverter is faster for the falling output than for the rising output, and conversely, for the odd-numbered stage. The inversion response time of the inverter is preset so that the rising output is faster than the falling output, and the reset edge is slightly faster than the main edge.
I'm trying to reach AND32.

Therefore, even if the output of the inverter INV31 is inverted from the low level to the high level by the reset edge, the input signal of the control terminal of the NAND gate NAND32 is still at the low level.
The output of the AND32 is not inverted, and the main edge reaches the inverter INV18 with a little delay, and the NAND gate NAN
The level of the input signal of the control terminal of D32 is from Low to High.
When inverted to the level, the output of the NAND gate NAND32 is inverted from the High level to the Low level.
The reset edge once disappears here and is regenerated by the main edge. And, in this way, the output of the NAND gate NAND32 is inverted by the main edge input from the control terminal, which is exactly the same operation as (c) above.

(G). After that, the operations of (d) to (f) are repeated, and the reset edge is regenerated every one revolution of the main edge, and the ring oscillator 4 orbits with the main edge. And the control signal PI
When becomes low level, such a series of operations is stopped and the state returns to the initial state (a).

As described above, normally, when an even number of inverting circuits are connected in a ring shape, the input / output of each inverting circuit becomes a different level and the entire circuit becomes stable. Since the oscillator 4 circulates two pulse edges (main edge and reset edge) having different generation timings on the same circulation, the NAND gate NAND1 is provided before the main edge generated by itself returns. The output is inverted by the reset edge, and the output of the NAND gate NAND32 is inverted by the main edge before the reset edge generated by itself is returned. It will orbit. Then, from each output terminal Q1 to Q16,
32 times the inversion operation time Td in each inversion circuit (32
-A pulse signal whose cycle is Td) is output.

Next, the data latch circuit 2 outputs the output pulse PO from the output control circuit 10 as shown in FIG.
External digital data C at the rising timing of
A latch circuit 2a composed of a number of D flip-flops DF corresponding to the number of bits of the digital data CDI, which latches each bit data (I1, ..., I22) of DI respectively.
And one D flip-flop DF that latches an enable signal EN from the outside at the rising timing of the output pulse PO, and one of two input signals described later according to the output signal ENABLE of the D flip-flop DF. Switching circuit 2b including selectors SL, the number of which corresponds to the number of bits of digital data CDI.
And a latch circuit 2c composed of a number of D flip-flops DF corresponding to the number of bits of the digital data CDI, which latches the output signal QIN of each selector SL in the switching circuit 2b at the rising timing of the output pulse PO,
It consists of

Then, each selector SL in the switching circuit 2b
The output signals QEXT of the respective D flip-flops DF forming the latch circuit 2a and the output signals of the respective D flip-flops DF forming the latch circuit 2c are input to the respective selectors SL. When the output signal ENABLE of the D flip-flop DF in 2b is 0 (Low level), the output signal from each D flip-flop DF forming the latch circuit 2c is output, and conversely, the output signal ENABLE is 1 (High level). Level), the output signal QEXT from each D flip-flop DF forming the latch circuit 2a is output. Therefore, the output signal ENA is supplied to each D flip-flop DF that constitutes the latch circuit 2c.
When BLE is 0, its own output signal is input, and conversely, when the output signal ENABLE is 1, each D flip-flop D that constitutes the latch circuit 2a.
The output signal QEXT from F is input.

In the data latch circuit 2 thus configured, as shown in FIG. 4, the D flip-flop DF of the latch circuit 2a for latching the lower 5 bits (I1 to I5) of the digital data CDI is respectively provided. The output signals (D1 to D5) of the corresponding D flip-flops DF of the latch circuit 2c are output to the pulse selector 6 as 5-bit control data CDL, and the digital data CD
It corresponds to the D flip-flop DF of the latch circuit 2a that latches the upper 17 bits (I6 to I22) of I,
The output signal (D6 to D22) of each D flip-flop DF of the latch circuit 2c is output to the down counter 8 as 17-bit control data CDH.

Here, the basic operation of the data latch circuit 2 will be described with reference to FIG. As shown in FIG. 5, first, when the control data CDH and CDL whose data value is DATA1 is output from the latch circuit 2c, the data value of the external digital data CDI changes from DATA1 to DATA2 at an arbitrary timing. Then, the latch circuit 2a latches the digital data CDI at the rising timing of the output pulse PO and outputs it as the output signal QE.
Output as XT. Therefore, the data value of the output signal QEXT changes to DATA2 at the rising timing of the first output pulse PO after the change of the digital data CDI.

Here, the enable signal EN from the outside is
At the low level, the output signal ENABLE of the D flip-flop DF in the switching circuit 2b becomes the low level, so that the selector SL in the switching circuit 2b operates in the latch circuit 2b.
The output signal from c is output as the output signal QIN. Therefore, the data value is still D from the latch circuit 2c.
The control data CDH and CDL of ATA1 are output.

After that, the enable signal EN from the outside
When it becomes High level, the D flip-flop DF in the switching circuit 2b latches the enable signal EN at the rising timing of the output pulse PO and outputs it as the output signal E.
Output as ENABLE, so output signal ENABLE
Changes to High level. Then, the selector SL in the switching circuit 2b outputs the output signal QEX whose data value is DATA2.
T is output as the output signal QIN.

Then, when the output pulse PO rises next, the latch circuit 2c latches and outputs the output signal QIN having the data value DATA2. Therefore, the control data C
The data values of DH and CDL change to DATA2. That is, the data latch circuit 2 of this embodiment directly outputs the upper 17 bits and the lower 5 bits of the externally input digital data CDI as the control data CDH and CDL. When the CDI changes, the control data CDH corresponding to the change,
The CDL is not immediately output, but is output in response to the enable signal EN from the outside and in synchronization with the output pulse PO. This is to prevent the control data CDH and CDL from being changed when the ring oscillator 4 is performing the circulating operation of the pulse signal as described later.

Then, as shown in FIG. 6, the pulse selector 6 inputs the output signals from the output terminals Q1 to Q16 provided in the ring oscillator 4 in order from Q1 in units of two, respectively. Eight selectors S that selectively output signals according to the second bit D2 of the control data CDL
A first selector group 6a composed of L and a first selector group 6a
The four selectors SL which respectively input the output signals from the respective selectors SL configuring the above in units of two and selectively output the respective signals in accordance with the third bit D3 of the control data CDL.
The output signal from each of the second selector group 6b and the selector SL that constitutes the second selector group 6b is input in units of two, and each signal is selected according to the fourth bit D4 of the control data CDL. Output signals from the third selector group 6c composed of two selectors SL and the selectors SL constituting the third selector group 6c are input, and each signal is input to the fifth bit D5 of the control data CDL. One selector 6 as a fourth selector group that selectively outputs according to
d and an inversion operation time Td that is almost the same as the inversion circuit that constitutes the ring oscillator 4, and an inverter INV40 that inverts and outputs the output signal from the selector 6d, and an inversion operation time (2 times that of the inverter INV40). The inverter INV41 having Td) for inverting and outputting the output signal from the selector 6d, and the output signals from the inverter INV40 and the inverter INV41 are input, and the input signal is input according to the first bit D1 of the control data CDL. And a selector 6e that selectively outputs the data.

The selectors SL constituting the first selector group 6a to the third selector group 6c and the selector 6d as the fourth selector group have bits (D2 to D5) of the corresponding control data CDL respectively. 6, the input signal on the left side in FIG. 6, that is, the output terminals Q1 to Q1
It is connected so as to output a signal corresponding to the smaller number 6 (1 to 16). Therefore, the control data CDL
When the predetermined bit of 1 is 1, the input signal on the right side in FIG. 6 is output.

On the other hand, the selector 6e controls the control data CDL.
When the first bit D1 of 0 is 0, the inverter INV4
On the contrary, when the first bit of the control data CDL is 1, the output signal from the inverter INV41 is output to the down counter 8 as the clock signal CLK. Therefore, a signal obtained by further inverting the output of the inverting circuit connected to the odd-numbered stage in the ring oscillator 4 is output as the clock signal CLK, and the above-mentioned main edge circulating on the ring oscillator 4 is the clock signal CLK. Will appear as the rising edge of.

In the pulse selector 6 thus configured, for example, when "10010" representing "18" is input as the control data CDL, first, each of the eight selectors SL of the first selector group 6a becomes Control data CDL
Since the second bit D2 of 1 is 1, the output terminals Q2, Q4, Q6, Q8, Q10, Q12, Q14 and Q, respectively.
The output signal from 16 is selected and output, and then each of the four selectors SL of the second selector group 6b outputs the control data CD.
Since the third bit D3 of L is 0, among the output signals from the first selector group 6a, output terminals Q2, Q6, Q
The output signals from Q10 and Q14 are selected and output.
Then, each of the two selectors SL of the third selector group 6c
However, since the fourth bit D4 of the control data CDL is 0, the output signals from the output terminals Q2 and Q10 are selected and output from the output signals from the second selector group 6b. Since the fifth bit D5 of the control data CDL is 1, the selector 6d selects the output signal from the output terminal Q10 among the output signals from the third selector group 6c and outputs it.

The output signal from the output terminal Q10 is the inverter INV40 or the inverter INV41.
However, in this case, since the first bit D1 of the control data CDL is 0, the selector 6e outputs the output signal of the inverter INV40 to the down counter 8 as the clock signal CLK. .

That is, when "10010" representing "18" is input as the control data CDL, the value "9" represented by the 4-bit data from the second bit D2 to the fifth bit D5 is 1 The output signal from the output terminal Q10 (the output signal from the inverter INV19 connected to the 19th stage in the ring oscillator 4) having the number added with is taken out, inverted by the inverter INV40, and output to the down counter 8. It will be. Therefore,
In this case, the control signal PI from the output control circuit 10
The delay time Ta from the change to the high level until the rising edge appears in the clock signal CLK is the inversion operation time (20 · Td) of approximately 20 inversion circuits that form the ring oscillator.

Further, when "10011" representing "19" is input as the control data CDL, the inverter IN having the double inversion operation time by the selector 6e.
Since V41 is selected, the above-mentioned delay time Ta becomes the inversion time (21 · Td) of approximately 21 inversion circuits that form the ring oscillator 4.

That is, in the present embodiment, the time obtained by multiplying the value obtained by adding 2 to the value represented by all the 5-bit data of the control data CDL and the inversion operation time Td of the inversion circuit constituting the ring oscillator 4 is multiplied. , The delay time Ta from the change of the control signal PI to the high level to the change of the clock signal CLK to the high level.

In this embodiment, the pulse selector 6
Is composed mainly of the 15 selectors SL and 6d because the circuit scale becomes large when it is formed as a well-known decoder center. On the other hand, the down counter 8 is configured as a known counter having a preset terminal PRE as shown in FIG. 1, and the output pulse PO output from the output control circuit 10 is input to the preset terminal PRE. ing. Then, the output pulse P
1 from the data latch circuit 2 when O is high level
The 7-bit control data CDH is preset as a count value, and the count value is decremented by 1 at each rising edge of the clock signal CLK output from the pulse selector 6, and when the count value becomes 0, the high level changes to the low level. The detection signal BOR that changes to is output.

Then, as shown in FIG. 1, the output control circuit 10 inverts the detection signal BOR from the down counter 8 and outputs the inverted signal INV42 and the inverter INV.
The output signal Q of the D flip-flop D-FF1 and the D flip-flop D-FF1 having the high active clear terminal CLR in which the output signal of V42 is input as a clock and the data input terminal D is pulled up to the high level Delay line 12 for delaying and outputting
And an inverter I that inverts the output signal from the delay line 12.
NV43, a NAND gate NAND44 for inputting the output signal QDB of the inverter INV43 and the output signal Q of the D flip-flop D-FF1, and a NAND gate NAND
A NAND gate NAND45 for inputting an output signal QO of 44 and an oscillation start signal PS from the outside, and a NAND gate N
A buffer BF that receives the output signal PRI of the AND45, increases the load driving capability, and outputs the output pulse PO.
And an output signal PRI and an output pulse PO, and outputs a control signal PI to the ring oscillator 4.
OR1, a delay line 14 that delays and outputs the output pulse PO by a predetermined time T2, an inverter INV46 that inverts the output signal from the delay line 14, and an inverter INV46.
Of the NOR gate NOR2 which receives the output signal and the output pulse PO from the same and outputs the clear signal CLR of the D flip-flop D-FF1.

In this output control circuit 10, when the oscillation start signal PS input from the outside is at the low level, the output signal PRI of the NAND gate NAND45 becomes Hi.
At the gh level, the buffer BF outputs the high-level output pulse PO, and the NOR gate NOR1 outputs the low-level control signal PI to the ring oscillator 4 to stop the operation of the ring oscillator 4. And
When the oscillation start signal PS becomes high level, the output pulse P
When O changes to Low level, the control signal PI changes to High.
Since the level changes, a pulse signal composed of a main edge and a reset edge circulates on the ring oscillator 4 as shown in FIG.

After that, the main edge circulates on the ring oscillator 4 and the pulse selector 6 outputs the clock signal CL.
K is output, and the down counter 8 outputs the detection signal BOR.
Is output, the D flip-flop D-FF1 latches the falling edge of the detection signal BOR via the inverter INV42, and the output signal Q becomes High level. As a result, the output signal Q of the NAND gate NAND44
Since O becomes Low level, the output pulse PO changes to High level and the control signal PI changes to Low level, and the operation of the ring oscillator 4 is stopped.

In this state, when the time determined by the delay time T1 of the delay line 12 elapses, the output signal QDB of the inverter INV43 changes to the low level, so that the output signal QO of the NAND gate NAND44 becomes high.
After returning to the level, the output pulse PO changes to the Low level again, and the control signal PI changes to the High level,
As a result, the pulse signal circulates again on the ring oscillator 4.

When the output pulse PO changes from the high level to the low level as described above, the delay line 14 and the inverter INV46 cause the NOR gate NOR2 to output:
For a time determined by the delay time T2 of the delay line 14,
Since the high level CLR signal will be output,
The D flip-flop D-FF1 is cleared, and its output signal Q returns from the high level to the low level.

Here, the overall operation of the digitally controlled oscillator configured as described above will be described with reference to FIG. The data latch circuit 2 outputs control data CDH having a data value of nH and control data CDL having a data value of nL in advance. Further, in FIG. 7, DCOU represents the count value of the down counter 8.

As shown in FIG. 7, the oscillation start signal PS is low.
When it is at the level, the output pulse PO becomes High level, and the value nH of the control data CDH at that time is preset in the down counter 8 as a count value. Further, the control signal PI becomes low level, and the ring oscillator 4 stops the circulation operation of the pulse signal.

When the oscillation start signal PS is changed to the high level, the output pulse PO changes to the low level and the control signal PI changes to the high level, and the ring oscillator 4 starts the circulation operation of the pulse signal. Then, the oscillation operation of the device starts. After that, when a time Ta1 obtained by multiplying a value obtained by adding 2 to the value nL of the control data CDL by the inversion operation time Td of the inversion circuit (the NAND gate and the inverter) configuring the ring oscillator 4, the clock output from the pulse selector 6 is output. The first rising edge occurs in the signal CLK, and the count value of the down counter 8 changes from nH to nH-1.

The output pulse PO changes from high level to low level.
When it changes to the level, the clear signal CLR in the output control circuit 10 becomes the high level for the delay time T2 of the delay line 14, the D flip-flop D-FF1 is cleared, and the output signal Q thereof is fixed to the low level.

After that, the pulse selector 6 outputs the clock signal CLK having one cycle of the main edge on the ring oscillator 4 (32.Td) as one cycle, and goes down every time the clock signal CLK rises. The count value DCOU of the counter 8 decreases. When the count value DCOU becomes 0, the detection signal BOR from the down counter 8 changes to Low level, the output pulse PO changes to High level, and the control signal P
I becomes Low level, and the circulating operation of the pulse signal of the ring oscillator 4 is temporarily stopped.

Here, before the output pulse PO changes from Low level to High level, external digital data CDI
However, the value of the upper 17 bits is mH and the value of the lower 5 bits is m
As shown in FIG. 5, each selector S in the switching circuit 2b of the data latch circuit 2 receives a high level enable signal EN from the outside as shown in FIG.
When the value of the L output signal QIN has already changed corresponding to the changed digital data CDI, as shown in FIG. 7, the data is output at the timing when the output pulse PO changes from Low to High level. The values of the control data CDH and CDL output from the latch circuit 2 change to mH and mL, respectively, and the setting of the pulse selector 6 is changed, and mH is preset in the down counter 8 as a count value. .

After that, when the delay time T1 of the delay line 12 of the output control circuit 10 elapses, the output pulse PO is output again.
When the level of the control signal PI changes to the High level and the ring oscillator 4 restarts the pulse signal circulating operation, the value m of the control data CDL is changed as described above.
When a time Ta2 obtained by multiplying the value obtained by adding 2 to L to the inversion operation time Td of the inversion circuit that constitutes the ring oscillator 4, the clock signal CLK rises, and thereafter, the main edge makes one round on the ring oscillator 4. Every time, the count value of the down counter 8 decreases, and the output pulse PO changes to High level again.

That is, in the digitally controlled oscillator of this embodiment, the inversion operation time Td of the inversion circuit constituting the ring oscillator 4 is equal to the value obtained by adding 2 to the value of the control data CDL.
Multiplied by the value obtained by subtracting 1 from the value of the control data CDH multiplied by the number of all inversion circuits of the ring oscillator 4 and its inversion operation time Td, and the delay time of the delay line 12 in the output control circuit 10. The output pulse PO changes to the High level every time when T1 and T1 are added, and this cycle becomes the oscillation cycle of the device.

As described above, according to the digitally controlled oscillator of this embodiment, the output cycle of the output pulse PO can be arbitrarily adjusted by changing the digital data CDI input from the outside. Moreover, the output cycle can be roughly determined by the count number of the down counter 8, that is, the upper 17 bits of the digital data CDI, and the output terminals Q1 to Q16 of the ring oscillator 4 and the pulse selector 6 can be determined by the lower 5 bits of the digital data CDI. The inverters INV40 and INV41 can be arbitrarily selected and finely adjusted in units of the inversion operation time Td of one inversion circuit. Therefore, the output circumference period of the output pulse PO can be digitally controlled in a wide range and with high resolution. Becomes

Further, in the digitally controlled oscillator of this embodiment, the inverting circuit (the NAND gate and the inverter) forming the ring oscillator 4 and the inverting circuit (inverters INV40, INV41) in the pulse selector 6 are used in common. The output cycle of the output pulse PO is adjusted, and the pulse signal generated by the ring oscillator 4 passes through the pulse counter 6 before being output as the clock signal CLK to the down counter 8. Since the number is always the same (five in this embodiment), the output cycle of the output pulse PO is set to the digital data CD.
It is possible to surely increase / decrease in a stepwise manner corresponding to the value of I.

Furthermore, in the digital control delay device of this embodiment, the ring oscillator 4 is composed of 32 inverting circuits, and the odd-numbered 16th stages connected at equal intervals.
Since the pulse signals are selectively taken out only from the inversion circuits, the time difference between the pulse signals becomes uniform, and the output cycle of the output pulse PO can be controlled with uniform resolution.

In the digital control delay device of this embodiment, the output terminal Q1 for extracting the pulse signal is output.
Since ~ Q16 is selected and the main edge of the pulse signal output from the output terminal is counted to obtain the output cycle of the output pulse PO, the above is described without making the device configuration particularly complicated. You will be able to obtain the effect of.

As shown in FIG. 1, in the output control circuit 10 of this embodiment, the output signal PRI of the NAND gate NAND45 and the output pulse PO are input to the NOR gate NOR1 to output the control signal PI. This is because the ring oscillator 4 is immediately stopped by the rising of the output signal PRI and the ring oscillator 4 is re-activated by the falling of the output pulse PO as shown in FIG. This is to set a longer time from when it reaches High level again. As a result, the maximum oscillation frequency of the device is set larger by ensuring the switching time of the setting performed by the down counter 8 and the pulse selector 6 without increasing the delay time T1 of the delay line 12 more than necessary. I am able to do it.

In addition, in the digitally controlled oscillator of this embodiment, of the 32 inversion circuits constituting the ring oscillator 4, only 16 inversion circuits connected to odd-numbered stages are selectively pulse signals. The pulse signal output from the adjacent inverting circuit is
This is because the edges are opposite in direction, and both edges cannot be counted by the down counter 8.

Therefore, usually, the minimum time difference between the pulse signals taken out from the ring oscillator 4 is the inversion operation time (2 · Td) for two inversion circuits, so the resolution capable of controlling the oscillation frequency is 2 · Td. It will be,
In the digitally controlled oscillator of this embodiment, the pulse selector 6 is operated according to the first bit D1 of the control data CDL.
By switching the inverters INV40 and INV41 inside, the control resolution is improved to the inversion operation time Td for one inversion circuit.

Next, a digitally controlled oscillator according to the second embodiment will be described with reference to FIGS. 8 and 9. The digital control oscillator of the second embodiment is different from the digital control oscillator of the first embodiment described above only in the configuration of the output control circuit, and the other parts are exactly the same.

That is, as shown in FIG. 1, the output control circuit 10 in the digital control oscillator of the first embodiment has the following configuration.
The delay line 14, the inverter INV46, and the NOR gate N
Although the configuration is such that the D flip-flop D-FF1 is cleared by OR2, the output control circuit 20 in the digital control oscillator of the second embodiment is similar to that shown in FIG.
As shown in FIG. 6, instead of the D flip-flop D-FF1, a D flip-flop D-F2 whose clear terminal is Low active is provided and
An output signal Q of F2 and a signal QD obtained by delaying the output signal Q by a delay line 12 for a predetermined time T1 are input to a NAND gate NAND46, and the NAND gate NAND4 is supplied.
AND gate AND of 6 output signal and output pulse PO
Input to, and the output signal as a clear signal CLR,
It is configured to output to the D flip-flop D-FF2.

In the digitally controlled oscillator configured as described above, as shown in FIG. 9, when the detection signal BOR from the down counter 8 changes from the High level to the Low level, the output signal Q of the D flip-flop D-FF2 is output. Is Low
From the Low level to the High level, and after a lapse of time T1, the output signal QD of the delay line 12 changes from the Low level to the High level. Then, the clear signal CLR immediately changes from the High level to the Low level, and the D flip-flop D-FF2
Is cleared and the output signal Q of the D flip-flop D-FF2 becomes low level, the clear signal CLR is immediately output.
The clear operation of the D flip-flop D-FF2 is performed such as returning to the high level.

According to the digital control oscillator of the second embodiment, the D flip-flop D-FF2 can be cleared without providing the delay line 14 unlike the output control circuit 10 of the first embodiment. Therefore, the output cycle of the output pulse PO can be controlled with a simpler device configuration.

In the digital control oscillators of the first and second embodiments, the ring oscillator 4 is composed of an even number of inverting circuits, but the ring oscillator is composed of an odd number of inverting circuits. May be. Therefore, as a third embodiment, a digitally controlled oscillator in which the ring oscillator is composed of 15 inverting circuits will be briefly described. The digitally controlled oscillator according to the present embodiment has substantially the same configuration as the digitally controlled oscillators according to the first and second embodiments, except that the configuration of the ring oscillator and the pulse selector and the digital data CDI from the outside are used. The only difference is that a data conversion circuit for converting into 30-ary digital data and outputting to the data latch circuit 2 is provided.

First, as shown in FIG. 10, the ring oscillator 22 in the digitally controlled oscillator according to the third embodiment has a NAND gate NAND 1 and a NAND gate NAND 1 as an inversion circuit for activation.
In the case of the first and second embodiments, fifteen inverting circuits composed of four inverters INV are connected in a ring shape, and the input terminal of the NAND gate NAND on the side opposite to the inverter INV is used. Similarly to the control signal PI
Has been entered. Further, in this embodiment, the output terminals Q1 to Q15 are provided in the order of every other inverting circuit in the ring oscillator 22.

In this way, the output terminals Q1 to Q15 are set to 1
Every other inverting circuit is provided in order of the first and second
This is because, as in the case of the embodiment, the pulse signals output from the adjacent inversion circuits have opposite edge directions. In the ring oscillator 22 configured as above, when the control signal PI is at the low level, the output of the NAND gate NAND is forcibly set to the high level, the output of the inverter INV of the next stage becomes the low level, and the inverter INV of the next stage further. The inversion circuit sequentially inverts so that the output of the
A signal having the same level as the output signal is input to the ring oscillator 22, and the ring oscillator 22 stabilizes in this state.

When the control signal PI changes to the high level, the NAND gate NAND starts the inverting operation, and the inverting operation time Td in each inverting circuit is about 15 times (1
When 5 * Td) has passed, a signal having the same level as the output signal is input to the NAND gate NAND, and the output level of the NAND gate NAND is inverted again. Therefore, each of the output terminals Q1 to Q15 of the ring oscillator 22 outputs a pulse signal having a period (30.Td) which is twice the period (15.Td) as one cycle.

On the other hand, the pulse selector in the digitally controlled oscillator of this embodiment has the same structure as the pulse selector 6 shown in FIG. 6, but the ring oscillator 22 does not have the output terminal Q16. In the first selector group 6 instead of the output terminal Q16.
It is configured to input to a.

Then, the additionally provided data conversion circuit converts the digital data CDI from the outside into, for example, "1".
0 ... 00,11110 "becomes" 10 ... 01,000,000 "
In the known configuration, the data is converted into 30-ary digital data and output to the data latch circuit 2.

In such a digital control oscillator, although the data conversion circuit for converting the digital data CDI must be provided as described above,
As in the case of the second embodiment, the output cycle of the output pulse PO is controlled in units of the inversion operation time Td in the inversion circuit constituting the ring oscillator 22 according to the value of the digital data CDI from the outside. Can be done.

As described above, according to the digitally controlled oscillators of the above-described first to third embodiments, the oscillation cycle (that is, the oscillation frequency) of the output pulse PO is set by the digital data CDI input from the outside. However, since the oscillation frequency is determined by the circulation operation of the pulse signal in the ring oscillators 4 and 20, the inverting operation of the inverting circuits (nand gates and inverters) configuring the ring oscillators 4 and 20 is possible. If the time Td fluctuates, it becomes impossible to accurately control the oscillation frequency according to the value of the digital data CDI.

However, since the digitally controlled oscillator of the above-mentioned embodiment can control the oscillation period digitally, the oscillation period of the output pulse PO from the digitally controlled oscillator and the reference of the output pulse from the reference oscillator such as the crystal oscillator. Oscillation can be achieved by comparing the cycle with preset correction data corresponding to the ratio and correcting the digital data CDI input from the outside by this correction data and inputting it to the data latch circuit 2. It becomes possible to easily and surely correct the frequency. Hereinafter, an example of the correction data calculation device for obtaining this correction data will be described with reference to FIGS. 11 and 12.

As shown in FIG. 11, this correction data operation device includes pulse phase difference encoding circuits 81 and 82 for encoding the phase difference of the input pulse, and pulse phase difference encoding circuit 81,
Correction value calculation circuit 83 for calculating correction data Do based on the coded data from 82. One pulse phase difference coding circuit 81 has a reference pulse PA from a reference oscillator such as a crystal oscillator. The output pulse PO from the digitally controlled oscillator of the above embodiment is input, and the other pulse phase difference encoding circuit 82 receives a reference pulse PA from a reference oscillator such as a crystal oscillator and a delay of this reference pulse PA for a predetermined time. The generated reference pulse PB is input. The output pulse PO input to the pulse phase difference encoding circuit 81 is output from the digital control oscillator to the digital data C so that the oscillation cycle becomes the same as the reference pulse PA.
This is a signal when DI is input and operated.

The pulse phase difference encoding circuits 81,
As shown in FIG. 12, reference numeral 82 includes a ring delay pulse generation circuit 84 in which an OR gate OR, a NAND gate NAND, and an even number of inverters INV are connected in a ring shape, a counter 86, a pulse selector 88, and an encoder 90. ing. This pulse phase difference encoding circuit 81,
Reference numeral 82 denotes a circuit previously proposed by the applicant of the present application in Japanese Patent Application No. 2-15865, etc., and operates as follows.

That is, each pulse phase difference encoding circuit 81,
In 82, the reference pulse PA is applied to the input terminal of the OR gate OR of the ring delay pulse generating circuit 84. Then, from the middle of the ring delay pulse generation circuit 84, a plurality of delay pulses whose delay time is determined by the number of stages of the inverter INV through which the reference pulse PA has passed are output and input to the pulse selector 88. Further, another input pulse PO or PB is input to the pulse selector 88, and when this pulse PO or PB is input, only the input from the ring delay pulse generation circuit 84 of the stage to which the reference pulse PA reaches is input. The pulse selector 88 selects and outputs a signal corresponding to the selected input to the encoder 90. Then, the encoder 90 outputs a binary digital signal corresponding to the input. Further, since the output of the inverter INV at the final stage of the ring delay pulse generation circuit 84 is connected to the OR gate OR, the reference pulse PA returns to the OR gate OR with a delay time due to all the circuits forming the ring, and as a result, The reference pulse PA circulates in the ring delay pulse generation circuit 84. Counter 8
6 is connected to the final stage inverter INV output in order to count the number of revolutions, and outputs the count result as the upper bit of the output of the encoder 90.

As a result, as shown in FIG. 11B, the time difference between the pulses PA and PO, or the pulses PA and PB is changed to the digital value DAO or DAB by the outputs from the pulse phase difference encoding circuits 81 and 82. It will be obtained as. Since the configurations of the pulse phase difference encoding circuits 81 and 82 are described in detail in Japanese Patent Application No. 2-15865, the description thereof will be omitted.

As described above, the pulse phase difference encoding circuit 81 obtains the digital value DAO representing the time difference between the output pulse PO from the digitally controlled oscillator and the reference pulse PA from the reference oscillator such as a crystal oscillator, and the pulse position The phase difference encoding circuit 82 obtains a digital value DAB representing the time difference between the reference pulse PA and the reference pulse PB. Then, of the digital values DAB and DAO thus obtained, the digital value DAB
Represents the input time difference between the reference signals PA and PB having the same period, and the time difference is also known, so that the obtained digital value DAB can be used as reference time data. On the other hand, since the digital value DAO simply represents the time difference between the rising of the reference pulse PA and the rising of the output pulse PO, it is not possible to directly obtain the deviation of the cycle between the reference pulse PA and the output pulse PO from the digital value DAO. .

Therefore, in the correction value calculation circuit 83, first, the difference between the digital values DAO1 and DAO2 obtained twice continuously by the pulse phase difference encoding circuit 81 is calculated to determine the period of the output pulse PO with respect to the reference pulse PA. A digital value ΔDAO (= DAO2-DAO1) corresponding to the time difference is obtained. If the digital value ΔDAO is positive, the cycle of the output pulse PO is longer than that of the reference pulse PA, and conversely, if ΔDAO is negative, the cycle of the output pulse PO is shorter than that of the reference pulse PA.

Then, using the digital value DAB and the known time TAB represented by the digital value DAB, this digital value ΔDAO is time difference data accurately representing the time difference between the output pulse PO and the output pulse PA. TAO (= TAB ・ △ D
AO / DAB), the time difference data TAO is added to the reference oscillation period TA of the reference pulse PA to obtain the actual oscillation period TO (= TA + TAO) of the output pulse PO, and the reference oscillation period TA is obtained from this oscillation period TO. The correction data Do (= TA / TO) is obtained by dividing.

As a result, for example, when the digital control oscillator is operated by the digital data CDI in the oscillation cycle of 1000 nsec. In order to obtain the correction data using the reference oscillator of the oscillation frequency 1 MHz (oscillation cycle 1000 nsec.), When the oscillation cycle of is 800 nsec., -200 nsec. Is obtained as the time difference data TAO, and the oscillation cycle TO is the value TAO and the reference oscillation cycle TA (=
1000 nsec.) To 800 nsec., And 1.25 (= 1000/800) is obtained as the correction data Do.

Therefore, when the digital control oscillator is subsequently operated, the value CCDI (= Do.CDI) obtained by correcting the digital data CDI with the correction data Do is input to the data latch circuit 2 to convert the digital data CDI into the digital data CDI. The output pulse PO can be generated with a corresponding oscillation period.

Next, in the digitally controlled oscillator of the above embodiment, the digital data C input to the data latch circuit 2 is input.
Since the oscillation frequency can be digitally controlled up to a high frequency region of several tens of MHz by DI, it can be applied to a high frequency PLL used in a communication device, a motor control device, or the like. For example, as shown in FIG. As described above, the frequency control oscillator 92 is the digital control oscillator of the above embodiment, the phase comparator 94 is the pulse phase difference encoding circuit shown in FIG. 12, and the loop filter 96 is a well-known digital filter. If comprised, a high frequency digital PLL which does not require an A / D converter etc. can be comprised.

Incidentally, FIG. 13B is a time chart showing the operation of this digital PLL.
The phase difference between the output pulse PO from the reference pulse PC and the reference pulse PC input from the outside is detected by the phase comparator 94 as a digital value D.
The digital value DA obtained as A is converted into a digital value DB by the loop filter 96 and input to the frequency variable oscillator 92. As a result, the output pulse PO is controlled by the reference pulse PC. . In such a PLL, it is not necessary to correct the oscillation frequency control data because the inverter inversion time fluctuation of the ring oscillator of the digitally controlled oscillator described above is automatically corrected (because feedback is applied).

The digital control oscillator which can control the output period (oscillation frequency) of the output pulse PO according to the external digital data CDI has been described above. However, in the digital control oscillator of the above embodiment, the oscillation is performed. From the outside, the time from the change of the start signal PS to the high level until the detection signal BOR output from the down counter 8 changes to the low level, that is, the time until the output pulse PO changes to the high level Digital data of CDI
Since it is obtained corresponding to the value of
If a latch circuit for latching the rising edge of is provided, the delay time from the change of the oscillation start signal PS to the High level to the change of the output pulse PO to the High level is converted to the digital data CDI from the outside. A digitally controlled delay device that can be controlled accordingly can be obtained. Further, even if the latch circuit is not provided as described above, for example, in the digital control oscillator of the above embodiment, the output control circuits 10 and 20 are excluded, and the oscillation start signal PS from the outside is controlled by the control signal PI. Instead of directly inputting to the ring oscillators 4 and 20, the oscillation start signal PS
The inverted signal of the data latch circuit 2 and the down counter 8
May be input to. In this case, the delay time from the change of the oscillation start signal PS to the high level until the detection signal BOR from the down counter 8 becomes the low level is the delay time.

According to the digital control delay device thus constructed, the delay time can be controlled in a wide range without increasing the number of delay elements as in the conventional delay device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digitally controlled oscillator according to a first embodiment.

FIG. 2 is a configuration diagram showing a configuration of a ring oscillator 4 of the first embodiment.

FIG. 3 is a time chart showing the operation of the ring oscillator 4 of the first embodiment.

FIG. 4 is a configuration diagram showing a configuration of a data latch circuit 2 of the first embodiment.

FIG. 5 is a time chart showing the operation of the data latch circuit 2 of the first embodiment.

FIG. 6 is a configuration diagram showing a configuration of a pulse selector 6 of the first embodiment.

FIG. 7 is a time chart showing the overall operation of the digitally controlled oscillator according to the first embodiment.

FIG. 8 is a block diagram showing a configuration of a digitally controlled oscillator according to a second embodiment.

FIG. 9 is a time chart showing the overall operation of the digitally controlled oscillator according to the second embodiment.

FIG. 10 is a configuration diagram showing a configuration of a ring oscillator 22 used in the digitally controlled oscillator according to the third embodiment.

FIG. 11 is an explanatory diagram showing a configuration and an operation of a correction data calculation device that obtains correction data for correcting the oscillation cycle of the digitally controlled oscillator according to the embodiment.

FIG. 12 is a circuit diagram showing a configuration of pulse phase difference encoding circuits 81 and 82 of the correction data operation device.

FIG. 13 is an explanatory diagram showing the configuration and operation of a digital PLL using the digitally controlled oscillator according to the embodiment.

[Explanation of symbols]

2 ... Data latch circuit 4, 22 ... Ring oscillator
6 ... Pulse selector 6a ... 1st selector group 6b ... 2nd selector group
6c ... Third selector group 6d, 6e, SL ... Selector 8 ... Down counter 10, 20 ... Output control circuit

Claims (3)

[Claims] 1. A digital control delay device capable of digitally controlling a delay time, wherein a plurality of inverting circuits for inverting and outputting an input signal are connected in a ring shape, and one of the inverting circuits is for input signals. A pulse revolving circuit configured as a starting reversing circuit capable of controlling the reversing operation by a control signal from the outside, and revolving the pulse signal with the start of the reversing operation of the starting reversing circuit by the input of the control signal; A pulse select for selecting the inverting circuit corresponding to the digital data representing the connection position of a predetermined inverting circuit for taking out the pulse signal from the pulse circulating circuit in the digital data and taking out the pulse signal output from the selected inverting circuit Means for counting predetermined edges of the pulse signal taken out by the pulse selecting means, Counting means for detecting that the digital data representing the number of revolutions of the pulse signal in the pulse circuit is reached, and the count value of the counting means reaches the digital data representing the number of revolutions. A digital control delay device, comprising: an output unit that outputs a detection signal when the fact is detected. 2. The digital control delay device according to claim 1, wherein the pulse circulation circuit is composed of an even number of inverting circuits, and a predetermined number of 2 ⁿ are connected at equal intervals in the pulse circulation circuit. Output terminals for extracting output signals from the respective inverting circuits, the pulse selecting means is connected to the output terminals, and two output signals from the output terminals are provided in order from the one close to the starting inverting circuit. 2 ^{n -1} select circuits that input in units and selectively output a signal closer to the starting inverting circuit or a signal not closer to the starting inverting circuit based on 1-bit data from the outside. And the output terminals of the lowest select circuit group, which are sequentially connected in a hierarchical manner, and two signals inputted in the same manner as the above select circuit are converted into 1-bit data from the outside. 2 to output Hazuki alternatively
^n- 1 each consisting of ^n-2 to 1 select circuits
Individual high-order select circuit groups, and each bit from the least significant bit to the high-order bit of the digital data representing the connection position of the inversion circuit is common to the select circuits forming each of the above select circuit groups. 1-bit data is input to each select circuit in the order from the least significant select circuit group to the upper select circuit group consisting of the one select circuit. 3. A digital control oscillator capable of digitally controlling an oscillation frequency, wherein the digital control delay device according to claim 1 or 2 is for starting when the detection signal is output by the output means. The operation of the inverting circuit is stopped, and the inverting circuit for starting is operated again after a lapse of a predetermined fixed time to circulate the pulse signal in the pulse circulator circuit, and at the same time, the circulator operation control means for outputting the detection signal as an oscillation signal. A digitally controlled oscillator, characterized by being provided.