JPH07297834A - Self-routing switch - Google Patents

Abstract

PURPOSE:To shorten the delay by preventing collision of cells in the output end of the input-stage switch of a banyan type self-routing switch used in an ATM exchange. CONSTITUTION:In 4-input and 4-output self-routing switch 1000 where a 2-input and 2-output unit switch consists of two stages of an input-stage switch 110 and an output-stage switch 120, the output-stage switch 120 consists or output switches 121A and 122A of a system A and output switches 121B and 122B of a system B, thus giving the duplex constitution to the output-stage switch 120 of the self-routing switch 1000.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Banyan type self-routing switch used in an ATM switch.

ATM (Asynchronous Transfer Mode) communication is a broadband and high-speed communication method, and its development for practical use is rapidly progressing. Similar to packet communication, this is a communication method in which the information to be communicated is divided into bit strings of a certain length, a header is provided at the beginning, and address information indicating the destination is added to the header for transfer. Such a unit of transfer of information is called a cell, and normally, one cell is composed of 53 octets of 5 octets in the header part and 48 octets in the information part.

When communication is carried out by this ATM system, a small number of cells are allocated to voice communication with a small amount of information such as a telephone, and many cells are used for communication with a large amount of information such as television image transmission. By allocating the cells to perform communication, it becomes possible to construct a communication network capable of flexibly coping with various services.

FIG. 7 shows a unit switch of a Banyan type self-routing switch. The figure shows a 2-input, 2-output unit switch 100. The switching operation of the unit switch 100 is performed according to the information written in the header portion of the cell as described above. Here, when the designation of the header section is "0", the unit switch 100 is switched to the output terminal 1 side, the input cell is output to the output terminal 1, and when the designation of the header section is "1", The unit switch 100 is switched to the output terminal 2 side, and the input cell is output to the output terminal 2. In this way, the cells input from the arbitrary input terminals 1 and 2 can be output to the arbitrary output terminals 1 and 2 by designating the header section.

When a Banyan network is constructed by providing a plurality of such Banyan type self-routing switches,
There is a need for self-routing switches that are collision free.

[0006]

2. Description of the Related Art FIG. 8 is a block diagram for explaining a conventional example. In the figure, 1000a is the unit switch described in FIG.
This is an example of a self-routing switch which is used individually and has a 4 × 4 matrix configuration. 110a is an input switch 1
An input stage switch composed of 11, 112, 120a
Is an output stage switch composed of output switches 121 and 122, and has four input terminals and four output terminals, respectively. In the figure, cells input from arbitrary input terminals 1 to 4 perform communication by outputting to arbitrary output terminals 1 to 4 according to the designation of the header section.

[0007]

In the above-mentioned conventional example, cells having different destinations may collide at the output ends of the input switches 111 and 112 of the input stage switch 110a. For example, when the destination of the cell input from the input terminals 1 and 2 is the output terminal 1, the input cell is output to the upper output end of the input switch 111 shown in the figure, and a collision occurs at this output end. . When such a cell collision occurs, one cell is stored in a buffer memory (not shown), the other cell is sent to the output stage switch 120a, and then the cell stored in the buffer memory. Is taken out and sent to the output stage switch 120a. When a cell collision occurs, cell delay occurs in the self-routing switch 1000a by performing such an operation.

The present invention aims to realize a self-routing switch with a small delay by preventing cell collision at the output terminal of the input stage switch of the self-routing switch.

[0009]

FIG. 1 is a block diagram for explaining the principle of the present invention. 1000 is 2 described in FIG.
This is a four-input, four-output self-routing switch in which a unit switch 100 having two inputs and two outputs is used, and an input stage switch 110 and an output stage switch 120 have a two-stage configuration.

In the present invention, the output stage switch 120 of the self-routing switch 1000 is replaced by the A system output switches 121A and 122A and the B system output switch 121B.
122B, which is a duplicated configuration.

In the figure, a to f are links connecting the input stage switch 110 and the output stage switch 120, the output end of the input stage switch 110 is the A system of the output stage switch 120,
The B system is connected in parallel.

Further, the output switches 121A and 121B of the output stage switch 120 and the output switch 122A,
The output terminals of 122B are connected in parallel.

Further, in the output stage switch 120, buffer memories B1 to Bn for each input terminal, each output terminal, and each delay quality class are provided, and when outputting, the output control unit 1
The control of 30 prevents the cells from colliding at the time of output by configuring to output from the cell having the higher delay quality class.

[0014]

Operation: The input switch 11 in the input stage switch 110
In 1 and 112, from the destination of the input cell and the delay quality class, the cell is output stage switch 120,
Header conversion is performed so as to specify to which output terminal the data is output. During this header conversion, cells of the same class input from the same input terminal are output stage switch 12
In order to prevent inversion when output from 0 and to simplify the control, cells of the same class input from the same input terminal are header-converted so that they take the same routing. Done. In this way, the cells are sent to the output stage switch 120 corresponding to the header converted by the input stage switch 110.

In the present invention, the input stage switch 110
When the cells are sent from the output stage switch 120 to the output stage switch 120, the output stage switch 120 has a dual structure, so that no cell collision occurs at the output end of the input stage switch 110.

Further, in the present invention, the output stage switch 120
Buffer memories B1 to Bn for each input terminal, each output terminal, and each delay quality class are provided therein, and the buffer memory B1 in which the cell is to be stored from the header of the cell sent from the input stage switch 110. ~ Bn is determined and the cell is stored in the buffer memory Bi.

When outputting the stored cells, for the same output terminal, 2 (the number of input terminals) × the number of classes × 2 (the number of systems of multiplexed output stage switches, in this case, 2 by duplication) ) Buffer memories, the output control unit 130 controls to select and output one of them.

In this way, it is possible to prevent cell collision at the output end of the input stage switch 110 and the output end of the output stage switch 120.

[0019]

FIG. 2 is a diagram for explaining an embodiment of the present invention.
In the figure, the delay quality class of the cell is two classes, and the cells of the delay quality class from the input terminals 1, 3, and 4 to the output terminal 1 and the cells of the delay quality class from the input terminal 2 to the output terminal 2 are simultaneously It is an embodiment showing the operation of the self-routing switch 1000 when inputting.

FIG. 3 is a diagram for explaining the input stage switch of the embodiment of the present invention. FIG. 3 shows the input stage switch 110 of FIG.
The operation of the part is described. Input stage switch 1
Reference numeral 10 is composed of input switches 111 and 112 having the same configuration. 10 of the input switches 111 and 112
Is a header conversion unit, and 20 is a switch unit (shown as SW unit in the figure).

In the figure, cells A, C of the delay quality class from the input terminals 1, 3 and 4 to the output terminal 1 are inputted.
D and the header of the cell B of the delay quality class input from the input terminal 2 are buffer memories B1, B2, B4, B1 in which the respective cells should be stored in the output stage switch 120 in the respective header conversion units 10.
It is converted into the number 5, (1), (2), (4), (15).

Then, according to the converted header, the buffer memories B1, B2, B4, B1 in the switch unit 20 are obtained.
Link a to the output stage switch 120 accommodating 5,
It is sent by e, f, and b. In the figure, the solid lines indicate links to which cells are transmitted, and the broken lines indicate links to which cells are not transmitted.

FIG. 4 is a diagram for explaining the output stage switch of the present invention, and FIG. 4 is a diagram for explaining the operation of the output stage switch 120 of FIG. The output stage switch 120 has a dual configuration and includes output switches 121A and 121B and output switches 122A and 122B. However, in this embodiment, since there is no cell output to the output terminals 3 and 4, the output switch 122A is , 122B are omitted in the figure. The output switches 121A and 121B have the same configuration, and the switch unit 30 and the eight buffer memories Bi are provided.
Is equipped with.

For example, the buffer memory B1 has an input terminal 1
That stores cells of the delay quality class that are input from the input terminal 3 and that are output to the output terminal 1, and that the buffer memory B2 that stores cells of the delay quality class that are input from the input terminal 3 and output to the output terminal 1 The buffer memory B13 stores cells of the delay quality class which are input from the input terminal 1 and output to the output terminal 1, and the buffer memory B14 is input from the input terminal 3.
The cell of the delay quality class output to the output terminal 1 is stored, and thus the buffer memory Bi for storing the cell is determined by the input terminal, the delay quality class, and the output terminal.

In this embodiment, the cells A and C input to the output switch 121A from the links a and e are transferred from the header of the switch unit 30 to the buffer memories B1 and B2 provided for each delay quality class and each input terminal. Each is switched and stored.

Similarly, the cells D and B input to the output switch 121B from the links b and f are stored in the buffer memories B4 and B15, respectively. FIG. 5 is a diagram for explaining an output cell according to the embodiment of the present invention. In the present embodiment, under the control of the output control unit 130, the delay quality class cells A, C, and D are sequentially output to the output terminal 1, and the delay quality class cell B is output to the output terminal 2.

FIG. 6 is a diagram for explaining the output control unit of the present invention. The output control unit 130 corresponds to the buffer memories B1 to B8 and corresponds to the buffer storage cell number counters BC1 to BC8.
And a priority input terminal designating section TS and a table T.

In the output control unit 130, the buffer memory B
Count the number of cells stored in 1 to B8,
The table T determines the buffer memory Bi in which the cells to be output are stored according to the pattern of the presence / absence of cells stored in each of the buffer memories B1 to B8.

The table T is set in the output order such that cells having a higher delay quality class are sequentially output, and the input terminals 1 to 4 in the input stage switch 110 are set.
The priority input terminal designating section TS is provided so that the priority can be changed in order to eliminate the unfairness caused by the above.

In this embodiment, the cells A and C are stored in the buffer memories B1 and B2, and the cells D and B are stored in the buffer memories B4 and B15, as described with reference to FIG. In this way, the count value of the buffer storage cell number counter BCi corresponding to the buffer memory Bi in which cells are accumulated becomes “1”. Here, priority is given to the input terminal 1 from the priority input terminal designating section TS (the order of priority is the input terminal 1,
2 and 3 ...). The cells to be output from these values and table T are determined. At this time, the table T is output from the cell having the higher delay quality class.

With respect to the output terminal 1, it is the input terminal 1 that has been given priority, so the buffer memory B1,
B2, B3, B4, B5, B6, B7, and B8 are output in this order, but in this embodiment, the cells are stored in the buffer memories B1, B2, and B4. The memories B1, B2, B4 are designated. Similarly, the buffer memory B15 is designated from the output terminal 2, and nothing is designated to the output terminals 3 and 4.

By sequentially outputting the cells in the buffer memory Bi designated by the output control unit 130 in this manner, the cells A, C and D are output to the output terminal 1 in the order of the output terminal 2
, Cell B is output at the same timing as cell A.

[0033]

According to the present invention, since the output stage switch has a dual structure, it is possible to prevent cell collision at the output end of the input stage switch and to perform communication with less delay.

A delay quality class is set in the cell,
By providing a buffer memory corresponding to the input terminal, the delay quality class, and the output terminal and controlling the output order of the cells by the output control unit, it is possible to prevent the cell collision.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating an embodiment of the present invention.

FIG. 3 is a diagram illustrating an input stage switch according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating an output stage switch according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating an output cell according to an embodiment of the present invention.

FIG. 6 is a diagram illustrating an output control unit according to an embodiment of the present invention.

[Fig. 7] Unit switch of Banyan type self-routing switch

FIG. 8 is a block diagram illustrating a conventional example.

[Explanation of symbols]

1000, 1000a Self-routing switch 100 Unit switch 110, 110a Input stage switch 111, 112 Input switch 120, 120a Output stage switch 121, 122, 121A, 121B, 122A, 12
2B output switch 130 output control unit 10 header conversion unit 20, 30 switch unit B1 to Bn buffer memory BC1 to BC8 buffer storage cell number counter T table TS priority input terminal designation unit a to f link

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location 9466-5K H04L 11/20 C

Claims (4)

[Claims] 1. A 2-input, 2-output unit switch (10
0) is a four-input, four-output self-routing switch (1000) having a two-stage configuration of an input stage switch (110) and an output stage switch (120), wherein the output stage switch (120) is an A-system output. Switch (121A, 122A) and B-system output switch (12
1B, 122B), and has a dual structure. 2. The self-routing switch according to claim 1, wherein the output stage switch (120) is provided with a buffer memory (B1 to Bn) corresponding to a delay quality class. switch. 3. The self-routing switch according to claim 1, wherein the buffer memories (B1 to Bn) in the output stage switch (120) correspond to destinations, input terminals, and delay quality classes. The self-routing switch described in 2. 4. The self-routing switch according to claim 1, further comprising an output control unit (130) for designating an output order of cells from the buffer memories (B1 to Bn). Routing switch.