JPH07296587A - Standby current control circuit - Google Patents

Abstract

PURPOSE:To realize a stand-by current control circuit reducing a standby current while realizing a low voltage and a high speed. CONSTITUTION:Sources of driver transistors DT1, DT2 of an SRAM cell are connected to a negative side source common wiring Vss1, and a substrate is connected to a substrate potential line VPWL, and the negative side source common wiring VSS1 and the substrate potential line VPWL are connected actuatedly by an NMOS transistor NT11 held to a non-conductive state by a chip enable signal CE at a standby time. Then, by connecting a resistance element R11 between the negative side source common wiring VSS1 and the ground GND, a subthreshold leakage current IL flowing through the driver transistors DT1, DT2 is made to flow through the resistance element R11 at the stand-by time, and a potential difference is given between the source and the substrate, and the threshold voltage VTH of the driver transistors DT1, DT2 is raised by a substrate bias effect. Thus, the subthreshold leakage current IL is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a standby current control circuit for controlling a standby current of an SRAM cell or the like.

[0002]

2. Description of the Related Art With the recent progress of miniaturization processing technology, for example, an MO that constitutes a memory transistor such as SRAM.
The channel length (L length) of SFET (hereinafter referred to as MOS transistor) was about 1 μm, but 0.5 μ
m, 0.3 μm, 0.25 μm, which tends to be significantly shortened. As a result, the level of the power supply voltage V _CC is changed from general 5V to 3V, 2V, or 1.5V due to the breakdown voltage and the like.
It is necessary to lower the voltage, and along with this, technological development for lowering the power supply voltage is being actively conducted.

[0003]

By the way, even in the above-mentioned situation of lowering the power supply voltage, it is necessary to maintain the high operation speed of the device. Therefore, it is necessary to lower the threshold voltage V _TH of the MOS transistor. is there.

However, when the threshold voltage V _TH of the MOS transistor is simply lowered, the so-called subthreshold leakage current I of the MOS transistor is accordingly accompanied.
There is a problem that L will increase on the contrary. This problem will be described in more detail with reference to FIGS. 6 and 7.

FIG. 6 is a characteristic diagram showing the relationship between the threshold voltage V _TH and the subthreshold leakage current IL in a MOS transistor. In FIG. 6, the horizontal axis represents the threshold voltage (gate-source voltage V _GS ), the vertical axis represents the subthreshold leakage current IL, and the vertical axis represents the logarithmic (Log) scale.

FIG. 7 shows an equivalent circuit of a general TFT load type SRAM of the CMOS system. In FIG. 7, B, B Is a bit line, WL is a word line, V _CC is a power supply voltage, WT1 and WT2 are word transistors, DT
1 and DT2 are driver transistors, LT1 and LT2 are load transistors, and ND1 and ND2 are storage nodes.

In this SRAM, the sources of the driver transistors DT1 and DT2 and the substrate are connected to a common negative source common line V _SS1 , and the source side potential of the driver transistors DT1 and DT2 is equal to the substrate potential. By holding at, high speed operation is achieved.

As shown in FIG. 6, when the threshold voltage of a MOS transistor drops from V _TH2 to V _TH1 , for example,
Since the slope of the leak current characteristic does not change, the subthreshold leak current increases from IL2 to IL1.

When this principle is applied to the SRAM cell of FIG. 7 and examined, in the SRAM cell, the driver transistor DT2 connected to the storage node ND2 held at the high level (H) is connected to the SRAM transistor in the standby state. Subthreshold leak current IL flows. But,
Since the sources of the driver transistors DT1 and DT2 and the substrate are connected to the common negative-side source common line V _SS1 , the source of the driver transistor DT2 and the substrate have the same potential, and the so-called substrate bias effect is not exhibited. , The threshold voltage of the driver transistor DT2 does not change. Therefore, in the SRAM cell in which the threshold voltage is set low so as to maintain the high speed operation while realizing the low voltage, the subthreshold leakage current IL is not proportional to the decrease but is inversely proportional to the decrease in the threshold voltage. And increase. The standby current of the SRAM cell is dominated by the sub-threshold leakage current of the driver transistors DT1 and DT2.
In the RAM, the standby current increases in inverse proportion to the decrease in the threshold voltage.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a standby current control circuit capable of reducing the standby current while realizing low voltage and high speed.

[0011]

To achieve the above object, the present invention has a transistor whose threshold value rises when a potential difference occurs between the substrate and the source, and controls the leak current flowing through the transistor during standby. The standby current control of the integrated circuit includes resistance means for connecting the substrate potential of the transistor and the source wiring, and potential holding means for holding the substrate potential and the source wiring potential at the same potential during non-standby.

Further, in the standby current control circuit of the present invention, the potential holding means has a switching element which operatively connects the substrate potential and the source wiring in accordance with the activation signal. Further, the potential holding means has a switching element that bypasses the resistance means according to a start signal and operatively connects the substrate potential and the source wiring. Further, the standby current control circuit of the present invention has a switching element that operatively connects the substrate potential and the resistance means in the standby state in response to the start signal.

A standby of an integrated circuit which includes a transistor which is connected between the positive and negative power supplies of the present invention and whose threshold value rises when a potential difference occurs between the substrate and the source and which controls a leak current flowing through the transistor during standby. The current control has resistance means for connecting the source common wiring of the integrated circuit and the substrate potential, and the resistance means is a P-channel MOS transistor provided between the positive power supply and the positive side source common wiring of the transistor. And an N-channel MOS transistor provided between the negative power source and the negative-side source common wiring, the gate of the P-channel MOS transistor is connected to the negative-side source common wiring, and the N-channel MOS transistor is connected to the negative-side source common wiring.
The gate of the channel MOS transistor is connected to the positive-side source common line.

Further, the standby current control of the present invention includes a switching circuit which operatively connects the positive power supply and the positive side source common wiring and the negative power supply and the negative side source common wiring in non-standby according to the start signal. Have.

[0015]

According to the standby current control circuit of the present invention, when a leak current flows through the transistor during standby, the current flows through the resistance means, causing a potential difference between the source wiring and the substrate potential, which becomes a substrate bias. The threshold of the transistor rises. As described above, the leak current is greatly reduced as the threshold voltage rises during standby.

During non-standby, that is, during normal operation, the switching element is rendered conductive in response to, for example, a chip enable signal as a start signal, the substrate potential and the source wiring potential are held at the same potential, and a high-speed read operation is performed. Is maintained.

Further, according to the standby current control circuit of the present invention, the gate of the P-channel MOS transistor is connected to the negative-side source common wiring, and the gate of the N-channel MOS transistor is connected to the positive-side source common wiring. The current flowing through the integrated circuit causes the voltage of the positive-side source common wiring to drop and the voltage of the negative-side source common wiring to rise. When the voltage of the negative-side source common wiring increases, the on-resistance of the P-channel MOS transistor increases, and the power supply current to the positive-side source common wiring decreases. As a result, the on-resistance of the N-channel MOS transistor increases and the leak current decreases. At this time, the potential of the negative-side source common line drops. As the potential of the negative-side source common wiring drops, the on-resistance of the P-channel MOS transistor decreases, and the power supply current to the positive-side source common wiring increases. As described above, during standby, the power supply current is controlled to a constant value by the self-bias by the feedback loop described above, and the leak current is effectively suppressed.

On the other hand, during operation, the negative power supply and the negative-side source common wiring and the positive power supply and the positive-side source common wiring are held at the same potential by the start signal, and the high-speed read operation is maintained.

[0019]

First Embodiment FIG. 1 shows an SRAM cell array according to the present invention.
Circuit diagram showing a first embodiment of a standby current control circuit for
Is. In FIG. 1, B, B Is a bit line and WL is a
, CL1, CL2, ..., CLn are SRAM cells,
V_PWLIs the substrate potential line, V_SS1Is the negative side source common wiring, V
_CCIs the power supply voltage, 10 is the standby current control circuit
Is showing.

SRAM cells CL1, CL2, ..., CLn
Is the same as the cell of FIG.
1, DT2, load transistors LT1 and LT2, and word transistors WT1 and WT2.
The sources of the driver transistors DT1 and DT2 of the SRAM cells CL1, CL2, ..., CLn are connected to the negative-side source common line V _SS1 respectively, and the substrate is connected to the substrate potential line V _PWL .

Other connection relations are the same as those of the SRAM cell of FIG. That is, the storage node ND1 is formed by the connection midpoint between the drains of the driver transistor DT1 and the load transistor LT1, and the storage node ND2 is formed by the connection midpoint between the drains of the driver transistor DT2 and the load transistor LT2. The gates of the driver transistor DT1 and the load transistor LT1 are connected to each other, and the midpoint of the connection is connected to the storage node ND2. The gates of the driver transistor DT2 and the load transistor LT2 are connected to each other, and the midpoint of the connection is connected to the storage node ND1. The sources of the load transistors LT1 and LT2 are connected to the supply line of the power supply voltage V _CC . Further, the word transistor WT1 is connected between the storage node ND1 and the bit line B, and the storage node ND2 and the bit line B are connected. A word transistor WT2 is connected between
The gates of the word transistors WT1 and WT2 are connected to the word line WL, respectively.

The standby current control circuit 10 includes a negative side saw.
Common wiring V_SS1And ground line GND
Resistance element R₁₁And the negative source common wiring V_SS1And circuit board
Position V_PWLAs a switching element connected between
NMOS transistor NT ₁₁Consists of and
It Then, the substrate potential line V_PWLOne end of the resistor element R₁₁
And the ground line GND. Well
NMOS transistor NT₁₁The gate is chip enable
Connected to the input line of the bull signal CE, chip enable
Signal CE is supplied at a low level (GND level)
It is kept in a non-conducting state during standby and is at a high level.
(V_CCLevel) is maintained during operation
To be done.

Resistance element R₁₁Is, for example, a diffusion layer, or
Realized by polysilicon or MOS transistor
Wear. FIG. 2 shows a resistance element R formed by using a diffusion layer.₁₁of
The example of a layout pattern is shown. E.g. stamba
A current IL is 0.5 μA, diffusion layer sheet resistance (ρ_S)
Is 100Ω and the width (W) is 0.5 μm. Substrate bias
V_SL(IL • Rs and Rs are resistor elements R₁₁Resistance value)
When it is set to 0.5V, the resistance element R₁₁Resistance value Rs, diffusion
The layer length L is calculated as follows. Rs = V_SL/IL=0.5 V / 0.5 μA = 1 MΩ L = (Rs / ρ_S) .W = 5 mm In this case, as shown in FIG.
Formed terminal T₁, T ₂With a space of 1 μm
Patterning by bending back 50 times with a length of 00 μm
And can be formed compactly.

When the resistance element R ₁₁ is composed of MOS transistors, the channel width W and the channel length L are set.
Is selected to a size that can realize a desired resistance value, and the gate voltage is also set to a potential that can realize a desired resistance value.

Next, the operation of the above configuration will be described. During standby, the chip enable signal CE is applied to the gate of the NMOS transistor NT ₁₁ of the standby current control circuit 10 at low level. This allows the NMOS
Since the transistor NT ₁₁ is held in the non-conducting state, the substrate is connected to the negative-side common wiring V _SS1 to which the sources of the driver transistors DT1 and DT2 of the SRAM cells CL1, CL2, to CLn are connected. The substrate potential line _VPWL is held in an electrically disconnected state and separated. In standby, the word line WL is set to low level. As a result, the negative-side source common line V _SS1 is connected to the resistance element R ₁₁ , and the substrate potential line V _PWL is kept connected to the ground line.

[0026] In this state, the flow subthreshold leakage current IL to the driver transistor DT1 or DT2 is connected to a storage node ND1 that is held at a high level, the current IL resistive element R ₁₁
Through to the ground GND. On the other hand, since no current flows through the substrate (P well) of driver transistor DT1 or DT2, the substrate potential is held at the ground level.

Therefore, the driver transistor DT1
Alternatively, a potential difference is generated between the source of DT2 and the substrate (P well), and this becomes a substrate bias, and the threshold voltage V _TH of the driver transistors DT1 and DT2 changes from V _TH1 to V _TH1.
Rise to _TH2 .

The change in threshold voltage ΔV _TH due to the substrate bias effect is given by the following equation. ΔV _TH = K {(V _SL + 2ψ) ^1/2 − (2ψ) ^1/2 } (1) Here, K is a substrate effect constant and is given by the following equation. K = (2ε ₀ ε _si qN) ^1/2 / C _{OX Further} , ψ is the difference between the Fermi level and the central level of the forbidden body, and is given by the following equation. ψ = {(kT) / q] ln (N / ni) where k is the Boltzmann constant, T is the absolute temperature, q is the elementary charge of electrons, N is the impurity concentration of the substrate, and ni is the intrinsic carrier concentration. There is.

Thus, the threshold voltage V
_{As TH} increases by ΔV _TH , the subthreshold leakage current IL greatly decreases from IL1 to IL2, as shown in FIG.

On the other hand, during operation, the chip enable signal CE is at a high level and the standby current control circuit 1
0 is applied to the gate of the NMOS transistor NT ₁₁ . As a result, the NMOS transistor NT ₁₁ is held in the conductive state, so that the SRAM cells CL1, CL are
2, to CLn driver transistors DT1 and D
The negative-side source common line V _SS1 to which the source of T2 is connected and the substrate potential line V _PWL to which the substrate is connected are held in an electrically connected state. As a result, the negative source common wiring V _SS1
The substrate potential line V _PWL is held at the same potential, and the high speed read operation is maintained.

As described above, according to this embodiment,
The sources of the driver transistors DT1 and DT2 of the SRAM cell are connected to the negative-side source common line V _SS1 , the substrate is connected to the substrate potential line V _PWL , and the negative-side source common line V _{SS1 is connected.}
The substrate potential line V _PWL is operatively connected by the NMOS transistor NT ₁₁ which is held in the non-conduction state by the chip enable signal CE in the standby state, and a resistance is provided between the negative side source common line V _SS1 and the ground GND. Element R ₁₁
By connecting the sub-threshold leak current IL flowing through the driver transistors DT1 and DT2 to the resistance element R ₁₁ during standby, a potential difference is generated between the source and the substrate, and the substrate bias effect causes the driver transistors DT1 and DT2 to operate. Since the threshold voltage V _TH is increased, there is an advantage that the standby current can be reduced while realizing low voltage and high speed.

[0032]

[Embodiment 2] FIG. 3 is a circuit diagram showing a second embodiment of a standby current control circuit for an SRAM cell array according to the present invention. The present embodiment is different from the above-described first embodiment in that both ends of the resistance element R ₁₁ are bypassed during operation and the negative-side source common wiring V _SS1 is connected to the ground GND without the resistance element R ₁₁ . This is because the NMOS transistor NT ₁₂ is provided.

According to the present embodiment, the same effects as those of the above-described first embodiment can be obtained, and at the same time, the negative-side source common wiring V _SS1 and the substrate potential line V _PWL are surely kept at the same potential. It can be held, and stable high-speed read operation can be realized.

[0034]

Third Embodiment FIG. 4 is a circuit diagram showing a third embodiment of the standby current control circuit for SRAM cell array according to the present invention. The present embodiment is different from the above-described first embodiment in that an inverter IN ₁₁ is connected to the connection line between the substrate potential line V _PWL and the connection midpoint of the NMOS transistor NT _{11 and} the connection point of the resistance element R ₁₁ and the ground GND. The NMOS transistor NT ₁₃ which is turned on / off by the inverted chip enable signal CE supplied to the gate via the
The substrate potential line V _PWL is connected to the ground GND via the NMOS transistor NT ₁₃ only in the standby mode.

During operation in this configuration, the chip enable
The NMOS signal NT is supplied by the bull signal CE.₁₃Is non-leading
The NMOS transistor NT is kept in the open state.₁₁and
NT ₁₂Is held in the conductive state,
Through wiring V_SS1And substrate potential line V _PWLAnd through one route
Connected to the ground line. Therefore, according to this embodiment,
If so, the same effect as the effect of the first embodiment described above can be obtained.
Of course, the negative source common wiring V during operation_SS1When
Substrate potential line V_PWLCan be held at the same potential without fail and during operation
Stable high-speed reading that can surely prevent the occurrence of substrate bias
The protruding operation can be realized.

[0036]

Fourth Embodiment FIG. 5 is a circuit diagram showing a fourth embodiment of the standby current control circuit for SRAM cell array according to the present invention. The difference between this embodiment and the second embodiment described above is that the resistance element is constituted by an NMOS transistor RNT ₁₁ .
The reason is that feedback is applied so that the resistance value increases due to the current flowing through the circuit during standby.

Specifically, the negative-side source common wiring V_SS1When
Ground GND and input according to chip enable signal CE
NMOS transistor RNT that is operatively connected₁₁Set up
K, each SRAM cell CL₁, CL₂,…, CLn load
Transistor LT₁, LT₂Common source
Wiring V_CC1Connected to the positive side source common wiring V_CC1When
Power supply voltage V_CCBetween the supply line and the PMOS transistor
Star PT₁₁And PT ₁₂Are connected in parallel and NMO for resistance
S transistor RNT₁₁The gate of the positive side source common wiring
V_CC1Connected to the PMOS transistor PT₁₁The gate of
To the negative source common wiring V_SS1Connect to the PMOS transistor
Dista PT₁₂Reverses the gate of the chip enable signal CE
Phase signal CE It is connected to the input line of
It

During standby in this configuration, the standby
At the time of bypass, the chip enable signal CE is at low level
NMOS transistor of standby current control circuit 10c
NT ₁₁, NT₁₂Applied to the gate of the
Bell signal CE Is the PMOS transistor PT₁₂The game
Applied to the As a result, the NMOS transistor N
T₁₁, NT₁₂And PMOS transistor PT₁₂Is non-leading
It is kept open. As a result, each SRAM cell CL
1, CL2, ..., CLn driver transistors DT1
And negative side source common wiring to which the sources of DT2 are connected
V_SS1And the substrate potential line V to which the substrate is connected_PWLIs electricity
Are kept disconnected and separated. Also, Stan
At the time of bypass, the word line WL is set to the low level.
As a result, the negative side source common wiring V_SS1Is a resistance element R₁₁To
Connected to the substrate potential line V_PWLIs connected to the ground line
Is retained.

In this state, since the positive-side source common wiring V _DD1 is at the level of approximately V _CC , the resistance NM is used.
The on-resistance of the OS transistor RNT ₁₁ decreases and the OS transistor RNT ₁₁ becomes conductive. At this time, the subthreshold leakage current IL flowing through the driver transistor DT1 or DT2 connected to the storage node ND1 or ND2 held at the high level is the resistance NMOS transistor RN.
It flows through T ₁₁ to the ground GND. On the other hand, since no current flows through the substrate (P well) of driver transistor DT1 or DT2, the substrate potential is held at the ground level.

Therefore, the driver transistor DT1
Alternatively, a potential difference is generated between the source of DT2 and the substrate (P well), and this becomes a substrate bias, and the threshold voltage V _TH of the driver transistors DT1 and DT2 changes from V _TH1 to V _TH1.
Rise to _TH2 . At this time, the negative-side source common wiring V _SS1
Since the potential of is increased, the on-resistance of the PMOS transistor PT ₁₁ whose gate is connected to the negative-side source common line V _SS1 increases, and the so-called power supply current to the positive-side source common line V _CC1 decreases. As a result, the on-resistance of the resistance NMOS transistor RNT ₁₁ increases and the subthreshold leakage current IL decreases. At this time, the potential of the negative-side source common line V _SS1 drops. As the potential of the negative-side source common wiring V _SS1 drops, P
The on resistance of the MOS transistor PT ₁₁ decreases, and the power supply current to the positive-side common source wiring V _CC1 increases. As described above, during standby, the power supply current is controlled to have a constant value by the self-bias by the feedback loop described above, and the subthreshold leakage current IL is effectively suppressed.

On the other hand, during operation, the chip enable
When the bull signal CE is high level, the standby current control circuit 1
0c NMOS transistor NT₁₁, NT₁₂At the gate of
The low-level signal CE applied to the opposite phase Is PMO
S transistor PT₁₂Applied to the gate of. By this
NMOS transistor NT₁₁, NT₁₂And PMO
S transistor PT₁₂Is held in conduction?
From the SRAM cells CL1, CL2, ..., CLn.
The sources of the inverter transistors DT1 and DT2 are connected.
Negative source common wiring V_SS1And the board to which the board is connected
Plate potential line V_PWLAnd is kept electrically connected and powered
Voltage V_CCSupply line and positive source common wiring V_CC1Tomo
It is kept electrically connected. As a result, the negative source
Common wiring V_SS1And substrate potential line V_PWL, And power supply voltage V
_CCSupply line and positive source common wiring V_CC1Is the same potential
, And the high-speed read operation is maintained.

According to the present embodiment, when the channel length of the transistor is miniaturized, the subthreshold leak current flowing during standby can be effectively suppressed.

[0043]

As described above, according to the present invention,
There is an advantage that the standby current can be reduced while realizing low voltage and high speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a standby current control circuit for an SRAM cell array according to the present invention.

FIG. 2 is a diagram showing a layout pattern example of a resistive element formed using a diffusion layer.

FIG. 3 is a circuit diagram showing a second embodiment of a standby current control circuit for an SRAM cell array according to the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of a standby current control circuit for an SRAM cell array according to the present invention.

FIG. 5 is a circuit diagram showing a fourth embodiment of a standby current control circuit for an SRAM cell array according to the present invention.

FIG. 6 is a characteristic diagram showing a relationship between a threshold voltage and a subthreshold leak current in a MOS transistor.

FIG. 7 is a general TFT load type SR based on a CMOS system.
The equivalent circuit of AM is shown.

[Explanation of symbols]

B, B Bit lines WL ... Word lines CL1, CL2, ..., CLn ... SRAM cells DT1, DT2 ... Driver transistors LT1, LT2 ... Load transistors WT1, WT2 ... Word transistors V _PWL ... Substrate potential line V _SS1 ... Negative source common wiring V _CC1 ... Positive side common source wiring V _CC ... Power supply voltage 10 ... Standby current control circuit R ₁₁ ... Resistor element RNT ₁₁ ... Resistance NMOS transistors NT _{11 to} NT ₁₃ ... NMOS transistors PT ₁₁ , PT ₁₂ ... PMOS transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H03K 17/687 H03K 3/356 E 9473-5J 17/687 Z

Claims (6)

[Claims] 1. A standby current control of an integrated circuit, comprising: a transistor whose threshold value rises when a potential difference occurs between a substrate and a source, and controlling a leak current flowing through the transistor during standby. A standby current control circuit having a resistance means for connecting a substrate potential and a source wiring, and a potential holding means for holding the substrate potential and the source wiring potential at the same potential when not in standby. 2. The standby current control circuit according to claim 1, wherein the potential holding means includes a switching element that operatively connects the substrate potential and the source wiring in response to a start signal. 3. The standby current according to claim 1, wherein the potential holding means has a switching element that bypasses the resistance means according to a start signal and operatively connects the substrate potential and the source wiring. Control circuit. 4. The standby current control circuit according to claim 1, 2 or 3, further comprising a switching element which operatively connects the substrate potential and the resistance means in standby in response to a start signal. 5. A standby current control of an integrated circuit, which includes a transistor connected between positive and negative power supplies and having a threshold value increased when a potential difference occurs between a substrate and a source, for controlling a leak current flowing through the transistor during standby. And a resistance means for connecting the source common wiring of the integrated circuit and the substrate potential, wherein the resistance means is a P channel MOS transistor provided between the positive power source and the positive side source common wiring of the transistor. , An N-channel MOS transistor provided between the negative power supply and the negative-side source common wiring, the gate of the P-channel MOS transistor is connected to the negative-side source common wiring, and the gate of the N-channel MOS transistor is Standby current control circuit connected to the positive source common wiring. 6. The standby current according to claim 5, further comprising a switching circuit that operatively connects the positive power supply and the positive-side source common wiring and the negative power supply and the negative-side source common wiring in non-standby according to the start signal. Control circuit.