JPH07288986A - Abnormality detection circuit for power converter - Google Patents

Abstract

PURPOSE:To obtain a highly reliable abnormality detection circuit for power converter without dupulicating the detector by detecting abnormality of the detector. CONSTITUTION:Inverter currents IAU, IAV, IAW detected through current detectors 601U, 601V, 601W for respective phases are added at an inverted adder comprising an operational amplifier 805 and resistors R11, R12, R13, R14. Output Ve from the operational amplifier 805 is compared at a comparator 812a with an output VRA from a reference voltage generator 813a and also compared at a comparator 812b with an output VRB from a reference voltage generator 813b. Outputs from the comparators 812a and 812b are summed logically at an OR circuit 807 and an output signal therefrom is employed as a detector abnormality signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an abnormality detecting circuit for a power converter configured to generate a polyphase AC output.

[0002]

2. Description of the Related Art FIG. 15 is an overcurrent protection circuit for a conventional three-phase inverter shown in, for example, Japanese Patent Publication No. 57-14114 as an abnormality detection circuit for a conventional power converter. It is shown based on. In the figure, 1 is a three-phase inverter, 601U, 601V, 60
1W is a current detector for each phase inverter current IAU, IAV, IAU, 801 is a rectifier circuit for converting AC to DC,
Reference numeral 802 is a comparator, and 803 is a reference voltage generator that generates a voltage VH according to the maximum current value that the inverter element can allow.

Next, the operation will be described. Inverter currents IAU, IAV, IAW of each phase are detected by a current detector 601.
U, 601V, 601W detected, the inverter current is rectified by the rectifier circuit 801, the reference voltage generator 80 set to the maximum current value that the inverter element can allow.
The comparator 8 compares the output voltage VH of No. 3 and the output of the rectifier circuit 801.
02, the inverter currents IAU, IAV of each phase,
When the IAW exceeds the maximum current value that the inverter element can tolerate due to a short circuit on the load side, the comparator 802 outputs an overcurrent signal, and the overcurrent signal performs a protective operation.

[0004]

Since the conventional overcurrent protection circuit of the inverter is constructed as described above, it is impossible to judge the failure of the current detector, and when the current detector fails, the power converter. It is impossible to determine whether is abnormal or the current detector is defective. Therefore, conventionally, when this inverter overcurrent protection circuit is used in a system that requires high reliability, it is possible to reduce the failure probability of the detector in order to improve the reliability and to judge the abnormality of the detector. As described above, the detector to the protection circuit are duplicated, but especially in a large capacity system or the like, the current detector has a large outer shape and is expensive, so that the outer shape of the device becomes large, There was a problem that the cost would go up.

The present invention has been made in order to solve the above-mentioned problems, and an abnormality of the detector can be determined, and thus reliability of the power converter can be reduced without duplicating the detector. An object of the present invention is to obtain an abnormality detection circuit for a power converter that can detect an abnormality.

[0006]

In the abnormality detecting circuit for a power converter according to claim 1 of the present invention, the outputs of the detectors for detecting the output currents of the respective phases of the power converter are added, and the added value is calculated. Compare with a predetermined value.

In the abnormality detecting circuit of the power converter according to the second aspect of the present invention, the outputs of the detectors for detecting the line-to-line output voltages of the power converter are added, and the added value is compared with a predetermined value. .

In the abnormality detecting circuit of the power converter according to claim 3 of the present invention, the output of each phase output current or each line output voltage detector is added by an adder composed of an operational amplifier and a resistor. Is.

In the abnormality detecting circuit of the power converter according to the fourth aspect of the present invention, the output of the detector of each phase output current or each line output voltage and the predetermined fixed bias voltage are supplied to the operational amplifier and the resistor. The addition is performed by the adder configured as described above.

In the power converter abnormality detection circuit according to the fifth aspect of the present invention, the outputs of the detectors of the output currents of the respective phases or the output voltages of the respective lines are added by a plurality of resistors.

In the abnormality detecting circuit for a power converter according to a sixth aspect of the present invention, the output of the detector of each phase output current or each line output voltage and a predetermined fixed bias voltage are added by a plurality of resistors. To do.

In the abnormality detecting circuit for a power converter according to claim 7 of the present invention, the output of the detector for each phase output current or each line output voltage is output by one A / D converter and a multiplexer having a plurality of channels. , Digitize and detect the abnormality of the detector with a microprocessor or the like.

In the abnormality detecting circuit of the power converter according to the eighth aspect of the present invention, the output of the detector of each phase output current or each line output voltage is digitized by a plurality of A / D converters, and the The processor or the like detects an abnormality in the detector.

In the abnormality detecting circuit of the power converter according to claim 9 of the present invention, the converter current, the output voltage and the load current of the power converter are detected by the detector, and the value corresponding to the differential value of the output voltage is detected. Then, the converter current detected by the detector and the load current are added, and the added value is compared with a predetermined value.

In the abnormality detecting circuit of the power converter according to the tenth aspect of the present invention, the value corresponding to the differential value of the output voltage, the converter current and the load current detected by the detector are supplied to the operational amplifier and the resistor. The addition is performed by the configured adder.

In the abnormality detecting circuit of the power converter according to the eleventh aspect of the present invention, the value corresponding to the differential value of the output voltage, the converter current detected by the detector, and the load current are fixed to a predetermined value. The bias voltage is added by an adder composed of an operational amplifier and a resistor.

In the abnormality detecting circuit for a power converter according to a twelfth aspect of the present invention, the value corresponding to the differential value of the output voltage, the converter current detected by the detector, and the load current are added by a plurality of resistors. To do.

In the abnormality detecting circuit for a power converter according to a thirteenth aspect of the present invention, a value corresponding to the differential value of the output voltage, the converter current detected by the detector, and the load current are fixed to predetermined values. The bias voltage is added by a plurality of resistors.

In the abnormality detecting circuit of the power converter according to the fourteenth aspect of the present invention, a value corresponding to the differential value of the output voltage, the converter current detected by the detector, and the load current are combined into one A / D. A converter and a multiplexer having a plurality of channels are used to digitize the signal, and a microprocessor or the like detects an abnormality in the detector.

In the abnormality detecting circuit for a power converter according to a fifteenth aspect of the present invention, a value corresponding to the differential value of the output voltage, the converter current detected by the detector, and the load current are output as a plurality of A / D signals. It is digitized by a converter, and an abnormality of the detector is detected by a microprocessor or the like.

[0021]

In the abnormality detecting circuit for the power converter according to the first aspect of the present invention, if the added value of the outputs of the detectors for detecting the output currents of the respective phases of the power converter is equal to or more than a predetermined value, the detector is detected. It can be judged as abnormal.

In the abnormality detecting circuit for a power converter according to a second aspect of the present invention, if the added value of the outputs of the detectors for detecting the line-to-line output voltages of the power converter becomes a predetermined value or more, the detector It can be judged as abnormal.

In the abnormality detecting circuit of the power converter according to the third aspect of the present invention, the outputs of the detectors of the output currents of the respective phases or the output voltages of the lines are added by an adder composed of an operational amplifier and a resistor. , It is possible to easily detect the abnormality of the detector.

In the abnormality detecting circuit of the power converter according to the fourth aspect of the present invention, the output of the detector of each phase output current or each line output voltage and a predetermined fixed bias voltage are provided by an operational amplifier and a resistor. Since addition is performed by the configured adder, an abnormality in the operational amplifier can be detected.

In the abnormality detecting circuit of the power converter according to the fifth aspect of the present invention, since the outputs of the detectors of the output currents of the respective phases or the output voltages of the lines are added by a plurality of resistors,
The abnormality of the detector can be detected more easily.

In the abnormality detecting circuit for a power converter according to a sixth aspect of the present invention, the output of the detector for each phase output current or each line output voltage and a predetermined fixed bias voltage are added by a plurality of resistors. Therefore, the disconnection of the wiring can be detected.

In the abnormality detecting circuit for a power converter according to claim 7 of the present invention, the output of the detector for each phase output current or each line output voltage is output by one A / D converter and a multiplexer having a plurality of channels. , Digitizing, and detecting abnormalities of the detector with a microprocessor, etc.,
Outliers can be changed easily.

In the abnormality detecting circuit of the power converter according to the eighth aspect of the present invention, the output of the detector of each phase output current or each line output voltage is digitized by a plurality of A / D converters, and the Since the processor detects the abnormality of the detector, the abnormality of the A / D converter can be detected.

In the abnormality detecting circuit of the power converter according to claim 9 of the present invention, the output current, the output voltage, and the load current of the power converter are detected by the detector, and the detected value is determined as a value corresponding to the differential value of the output voltage. If the added value of the converter current detected by the detector and the load current exceeds a predetermined value, it can be determined that the detector is abnormal.

In the abnormality detecting circuit of the power converter according to the tenth aspect of the present invention, the value corresponding to the differential value of the output voltage, the converter current and the load current detected by the detector are supplied to the operational amplifier and the resistor. Since the addition is performed by the configured adder, it is possible to easily detect the abnormality of the detector.

In the abnormality detecting circuit of the power converter according to the eleventh aspect of the present invention, the value according to the differential value of the output voltage, the converter current detected by the detector, and the load current are fixed to a predetermined value. Since the bias voltage is added by the adder composed of the operational amplifier and the resistor, the abnormality of the operational amplifier can be detected.

In the abnormality detecting circuit for a power converter according to a twelfth aspect of the present invention, the value corresponding to the differential value of the output voltage, the converter current detected by the detector, and the load current are added by a plurality of resistors. Therefore, the abnormality of the detector can be detected more easily.

In the abnormality detecting circuit of the power converter according to the thirteenth aspect of the present invention, the value corresponding to the differential value of the output voltage, the converter current detected by the detector, and the load current are fixed to a predetermined value. Since the bias voltage is added by a plurality of resistors, disconnection of wiring can be detected.

In the abnormality detecting circuit for a power converter according to a fourteenth aspect of the present invention, a value corresponding to the differential value of the output voltage, the converter current detected by the detector, and the load current are combined into one A / D. Since the converter and the multiplexer having multiple channels digitize the signal and the microprocessor detects the abnormality of the detector, the abnormal value can be easily changed.

In the abnormality detecting circuit for a power converter according to a fifteenth aspect of the present invention, a value corresponding to the differential value of the output voltage, the converter current detected by the detector, and the load current are output as a plurality of A / D signals. Since it is digitized by the converter and the abnormality of the detector is detected by the microprocessor or the like, the abnormality of the A / D converter can be detected.

[0036]

【Example】

Example 1. FIG. 1 is a block diagram showing the first embodiment. In the figure, reference numeral 1 denotes a power converter, which is a three-phase inverter having a full bridge configuration in this example. 601U, 601V,
601W is the inverter current IAU, IAV, IA of each phase
W current detector, 802 is a comparator, 803 is a voltage VH corresponding to the maximum current value that the inverter element can tolerate.
, A reference voltage generator 805, an operational amplifier 805, R1
1, R12, R13 and R14 are resistors, and the operational amplifier 805 and the resistors R11, R12, R13 and R14 form an inverting adder. Further, 813a is a reference voltage generator that generates the voltage VRA, 813b is a reference voltage generator that generates the voltage VRB, and 812a and 812b are comparators.

Next, the operation of the first embodiment will be described with reference to FIG. In this embodiment, the current detector 601 for each phase
Inverter current I detected at U, 601V, 601W
The AU, IAV, and IAW are connected to the operational amplifier 805 and the resistor R1.
The output Ve of the operational amplifier 805 and the output VRA of the reference voltage generator 813a are compared by the comparator 812a, and the output Ve of the operational amplifier 805 and the reference voltage are added. Generator 813b
Of the output V RB of the comparator 812b and the comparator 812b.
The OR circuit 807 takes the logical sum of the outputs of a and the comparator 812b, and the output of the OR circuit 807 is used as the detector abnormality signal. In the above configuration, the resistors R11, R12, R1
3, R14, operational amplifier 805, comparators 812a and 81
2b, reference voltage generators 813a and 813b, OR circuit 8
Reference numeral 07 constitutes the determination means of claim 1.

For example, the current detectors 601U, 60 for each phase
When 1V and 601W are normal for all three phases, the relationship between the outputs of the current detectors 601U, 601V, and 601W for each phase is

IAU + IAV + IAW = 0

Therefore, the output Ve of the operational amplifier 805 forming the inverting adder becomes Ve = 0. In addition,
Here, it is considered that the ground fault in the power converter is unlikely to occur, and it is not necessary to consider the ground fault problem here.
However, a ground fault may occur outside the power converter (on the load side), but in this case as well, the voltage, current, and detector on the power converter side are not affected. The above also applies to the case of the voltage described later. On the other hand, on the other hand,
Of the current detectors 601U, 601V, 601W for each phase,
When the current detector for one phase becomes abnormal, the current detector for each phase 6
The relation of the output of 01U, 601V, 601W is

IAU + IAV + IAW ≠ 0

Therefore, the output Ve of the operational amplifier 805 forming the inverting adder becomes Ve ≠ 0. Therefore, if the output Ve ≠ 0 of the operational amplifier 805, it can be considered that the detector is abnormal, but in reality, since the detector has a detection error,
Outputs VRA and VRB of the reference voltage generators 813a and 813b are positive and negative voltages ± VSE (VRA = + VSE, VRB = -V) according to the error.
SE) may be compared by the comparator 812a and the comparator 812b. That is, the comparator 812a outputs a signal when Ve becomes + VSE or more, and the comparator 812b outputs Ve.
Outputs a signal when becomes -VSE or less.

In the configuration of the first embodiment, the current detector 601
An abnormality of the current detector can be detected without duplicating U, 601V, and 601W.

Example 2. FIG. 2 is a block diagram showing the second embodiment. 2, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. The difference from the first embodiment is that a bias voltage generator 82 for generating a voltage of VB is provided.
3 and the resistor R15 are added, and the other points are those of the first embodiment.
Is the same as. That is, in the second embodiment, the determining means is configured by adding the bias voltage generator 823 and the resistor R15 to the determining means of the first embodiment.

In FIG. 2, the bias voltage generator 823
The output Ve of the operational amplifier 805 that constitutes the inverting adder is

Ve = IAU + IAV + IAW + VB

It becomes Therefore, the current detector 601 for each phase
When U, 601V, and 601W are normal for all three phases, the relationship between the outputs of the current detectors 601U, 601V, and 601W for each phase is

IAU + IAV + IAW = 0

Therefore, the output Ve of the operational amplifier 805 forming the inverting adder becomes Ve = VB. However, when the current detector for one phase of the current detectors 601U, 601V, 601W for each phase becomes abnormal, the relationship between the outputs of the current detectors 601U, 601V, 601W for each phase becomes

IAU + IAV + IAW ≠ 0

Therefore, the output Ve of the operational amplifier 805 forming the inverting adder becomes Ve ≠ VB. Further, when a failure such as the output of the operational amplifier 805 becomes 0V, the output Ve of the operational amplifier 805 becomes Ve ≠ VB.
Therefore, if the output Ve of the operational amplifier 805 is Ve ≠ VB, it can be considered that the detector is abnormal. However, in reality, since the detector has a detection error, the reference voltage generators 813a and 813 are present.
The outputs VRA and VRB of b are voltages (VRA = + VSE + V) obtained by adding positive and negative voltages ± VSE according to the error to the bias voltage VB.
B, VRB = -VSE + VB), and the comparators 812a and 812b may be compared as in the first embodiment.

In the configuration of the second embodiment, similarly to the first embodiment, the abnormality of the current detector can be detected without duplicating the current detectors 601U, 601V and 601W, and further, the abnormality of the operational amplifier 805. (When the output of the operational amplifier 805 becomes 0 due to the abnormality of the operational amplifier 805) can be detected.

Example 3. Next, FIG. 3 is a block diagram showing a third embodiment. In FIG. 3, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. Example 1
The difference is that in the first embodiment, the judging means adds the inverter currents of the respective phases by the inverting adder composed of the resistor and the operational amplifier, whereas in the third embodiment, the resistor R2 is added.
This is a point in which the inverter current of each phase is added by 1, R22, and R23, and the other points are the same as in the first embodiment. That is, in the third embodiment, the resistors R21, R22, R23, the comparators 812a and 812b, and the reference voltage generators 813a and 81.
3b and the OR circuit 807 constitute the judgment means of claim 3.

The resistors R21, R22 and R23 are connected to R21 =
When R22 = R23, the voltage Ve at the butt point of the resistors R21, R22, and R23 is

Ve = (IAU + IAV + IAW) / 3

It becomes Therefore, the current detector 601 for each phase
When U, 601V, and 601W are normal for all three phases, the relationship between the outputs of the current detectors 601U, 601V, and 601W for each phase is

IAU + IAV + IAW = 0

Therefore, the resistors R21, R22, and R23 are
The voltage Ve at the matching point is Ve = 0. But,
Of the current detectors 601U, 601V, 601W for each phase,
When the current detector for one phase becomes abnormal, the current detector for each phase 6
The relation of the output of 01U, 601V, 601W is

IAU + IAV + IAW ≠ 0

Therefore, the voltage Ve at the matching point of the resistors R21, R22 and R23 is Ve ≠ 0. So Ve
If Ve ≠ 0, it may be considered that the detector is abnormal, but in reality, the detector has a detection error, and therefore the reference voltage generator 8
Outputs VRA and VRB of 13a and 813b are positive and negative voltages ± VSE (VRA = + VSE, VRB = -VSE) according to the error,
The comparators 812a and 812b may be compared as in the first embodiment.

In the configuration of the third embodiment, as in the first embodiment, the abnormality of the current detector can be detected without duplicating the current detectors 601U, 601V, 601W, and the circuit configuration is simple. Can be

Example 4. Next, FIG. 4 is a block diagram showing a fourth embodiment. 4, parts corresponding to those in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted. Example 4
The third embodiment is different from the third embodiment in that a bias voltage generator 833 for generating a voltage of VB and a resistor R24 are added to the judging means shown in the third embodiment to constitute the judging means. Same as 3.

The resistors R21, R22, R23 and R24 are
If R21 = R22 = R23 = R24, the resistance R21,
The voltage Ve at the matching point of R22, R23, and R24 is

Ve = (IAU + IAV + IAW + VB) / 4

It becomes Therefore, the current detector 601 for each phase
When U, 601V, and 601W are normal for all three phases, the relationship between the outputs of the current detectors 601U, 601V, and 601W for each phase is

IAU + IAV + IAW = 0

Therefore, the resistors R21, R22 and R2 are
3, the voltage Ve at the matching point of R24 is Ve = VB / 4
Becomes However, the current detectors 601U and 601 for each phase
Of the V and 601W, if the current detector of one phase becomes abnormal,
The relationship between the outputs of the current detectors 601U, 601V, and 601W of each phase is

IAU + IAV + IAW ≠ 0

Therefore, the resistors R21, R22, R23, R
The voltage Ve at the matching point of 24 is Ve ≠ VB / 4. Further, when the wiring from the matching point of R21, R22, R23, and R24 to the comparators 812a and 812b is broken, the input voltage Va of the comparators 812a and 812b is Va.
≠ Ve. Therefore, if Va is not equal to VB / 4, it may be considered that the detector is abnormal or the wiring is broken. However, in reality, the detector has a detection error.
Outputs VRA and VRB of 13a and 813b are bias voltage V
A voltage (VRA = + VSE + VB / 4, which is a value obtained by dividing B by 4 (VB / 4) and adding positive and negative voltages ± VSE according to the error, (VRA = + VSE + VB / 4,
VRB = -VSE + VB / 4), and the comparison between the comparators 812a and 812b may be performed in the same manner as in the first embodiment.

In the configuration of the fourth embodiment, an abnormality of the current detector can be detected with a simple circuit configuration without duplicating the current detectors 601U, 601V and 601W as in the third embodiment. Also, the disconnection of the wiring to the comparator (when the potential becomes 0 due to the disconnection of the wiring) can be detected.

Example 5. FIG. 5 is a block diagram showing the fifth embodiment. 5, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. The fifth embodiment differs from the first embodiment in that the judging means shown in the first embodiment further includes a multiplexer 809 and an A / D converter 810, and the output of the current detector is digitized. Is the same as in the first embodiment.

In FIG. 5, the inverter current I of each phase is
AU, IAV, IAW are switched by a multiplexer 808 and digitized by an A / D converter 809.
Detection is performed by the microprocessor.

Current detectors 601U, 601V, 601W
The error of is different in the error range depending on the rating, accuracy, etc. of the detector, so the value of the reference voltage generator must be changed, but it is digitized by the A / D converter and detected by the microprocessor. Therefore, the detected value can be easily changed.

In the configuration of the fifth embodiment, the abnormality of the current detector can be detected without duplicating the current detectors 601U, 601V, 601W as in the first embodiment, and the abnormality detection value can be detected. It can be easily changed.

Example 6. FIG. 6 is a block diagram showing the sixth embodiment. 6, parts corresponding to those in FIG. 5 are designated by the same reference numerals, and detailed description thereof will be omitted. The sixth embodiment differs from the fifth embodiment in that the judging means of the sixth embodiment uses A / D converters 809a, 809b and 809c for each inverter current.
Is the same as that of the fifth embodiment except that the output of the detector is digitized.

In FIG. 6, the inverter current I of each phase
A / D converters 809a, 8 for each AU, IAV, IAW
09b and 809c perform digitization, and the microprocessor performs detection.

In the sixth embodiment, A / D converters 809a and 809b for digitizing the inverter current of each phase,
Even if one A / D converter of 809c becomes abnormal, IAU + IAV + IAW ≠ 0. In this case, since the microprocessor 850 obtains the output for each A / D converter, it is possible to detect an abnormality in the A / D converter.

In the configuration of the sixth embodiment, the abnormality of the current detector can be detected without duplicating the current detectors 601U, 601V and 601W as in the fifth embodiment. It can be easily changed, and in addition, an abnormality of the A / D converters 809a, 809b, 809c can be detected.

Example 7. Next, FIG. 7 is a block diagram showing a seventh embodiment. 7, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. Example 1
The difference is that the number of detectors is changed and the abnormality detection method of the detectors is changed depending on the control system of the inverter.

In FIG. 7, reference numeral 1A is a main circuit of the power converter, which is a single-phase switching element S1 as shown in FIG.
-S4 full bridge inverter, 1-2KH
An example thereof is PWM modulation with a triangular wave carrier of about z or more. Reference numerals 2 and 3 denote a filter reactor and a capacitor, 4 a load, 601 a detector of the inverter current IA, 602 a detector of the load current IL, and 603 a detector of the output voltage VC. In the figure, numbers in the 900s indicate that they are components of the control circuit. That is, 90
Reference numeral 1 is an AC sine wave reference voltage generation circuit, and 902 is a current reference command value Ic * = wCp to be passed through a capacitor advanced by 90 ° with respect to the AC sine wave reference voltage Vc = Esinwt.
An Ecoswt generation circuit, 903 is a clock generator that serves as a time base for these reference values, 910 is a voltage control amplifier, 905 is a limiter that limits the inverter current command value IA * to a value equal to or less than the allowable current of the inverter, and 906 is a current control amplifier. , 908 are PWM modulation circuits, and 909, 911 are adder / subtractors.

Further, in FIG. 7, reference numerals in the 800s indicate that they are constituent elements of the abnormality detection circuit of the detector. That is, 800 is a differentiator, 805 is an operational amplifier, R11
14 are resistors, and the operational amplifier 805 and the resistors R11 to R11.
Reference numeral 14 constitutes an inverting adder. Reference numeral 813a is a reference voltage generator for generating the voltage VRA, 813b is a reference voltage generator for generating the voltage VRB, and 812a and 812b are comparators.

Next, the operation of the seventh embodiment will be described with reference to FIG. First, the operation of the control circuit will be described. The control circuit is composed of a current minor loop that performs instantaneous current control and a voltage control loop that responds sufficiently quickly. A current command value IA * to be passed by the inverter to output a sine wave AC voltage is obtained, and an inverter current IA is instantaneously responded to by this command value by a current minor loop, and a sine wave output voltage that follows the AC reference voltage. To get That is,
The operation of this current minor loop is as follows. The error between the current command value IA * to be passed by the inverter for outputting the AC reference voltage and the inverter current IA detected by the detector 601 is amplified by the current control amplifier 906, and the output signal IE1 of this current control amplifier 906 is PWM. Modulation circuit 9
It becomes the input of 08, and the modulation output of this is added to the inverter to perform PWM control.

Next, how to obtain the current command value IA * will be described. The current that the inverter should supply is the capacitor 3
Current IC and load current IL. Therefore, the inverter current command value IA * is obtained by comparing the capacitor current IC * output from the capacitor current command generation circuit 902 with the detector 6
A correction component Jc for minimizing the voltage deviation is added to the load current IL detected in 03 by an adder 911, and a signal limited to the allowable current of the element or less through a limiter 905 is a reference of a current minor loop. Give as.

Next, the operation of the voltage control loop will be described. In order to correct the disturbance of the output voltage from the sine wave due to load fluctuations and uncertainties and to stabilize the system, the inverter AC output voltage command VC * output from the AC reference voltage generation circuit 901 and the detector 603 detect it. Output voltage VC
Error of the subtractor 909 to the voltage control amplifier 91
It is amplified by 0, and the output signal of the voltage control amplifier 910 is added to the inverter current command IA * as the correction component Jc.

Next, the operation of the abnormality detection circuit of the detector will be described. Inverter current IA, output voltage VC, load current IL detected by each detector 601, 602, 603
The relation of can be expressed by the following equation.

IA + IC + IL = IA + S.Cp.VC + IL = 0

That is, each detector 601, 602, 60
When 3 is normal, the relation of the output of each detector is

IA + S.Cp.VC + IL = 0

Therefore, the output Ve of the operational amplifier 805 which constitutes the inverting adder becomes Ve = 0. But,
When one of the detectors 601, 602, 603 becomes abnormal, the relation of the output of each detector becomes

IA + S · Cp · VC + IL ≠ 0

Therefore, the output Ve of the operational amplifier 805 which constitutes the inverting adder becomes Ve ≠ 0. Therefore, if the output Ve of the operational amplifier 805 is Ve ≠ 0, it can be considered that the detector is abnormal, but in reality, since the detector has a detection error, the output VRA of the reference voltage generators 813a and 813b,
VRB is the positive and negative voltage ± VSE (VRA = + VS
E, VRB = -VSE), and then the comparators 812a and 812b may be compared as in the first embodiment. In the above configuration, the differentiator 800, the resistors R11 to R14, and the operational amplifier 805 form the determination means of claim 7.

In the configuration of the seventh embodiment, each of the detectors 601 and 6 is
It is possible to detect the abnormality of the detector without duplicating 02 and 603.

Example 8. FIG. 10 is a block diagram showing the eighth embodiment. 10, parts corresponding to those in FIG. 7 are designated by the same reference numerals, and detailed description thereof will be omitted. The eighth embodiment differs from the seventh embodiment in that a bias voltage generator 823 and a resistor R15 are added to the judging means of the seventh embodiment to constitute the judging means, and the other points are the same as those of the seventh embodiment.

In FIG. 10, the bias voltage generator 82
By adding 3 and the resistor R15, the output Ve of the operational amplifier 805 forming the inverting adder is

Ve = IA + S.Cp.VC + IL + VB

It becomes Therefore, each detector 601, 60
When 2,603 is normal, the relation of the output of each detector is

IA + S.Cp.VC + IL = 0

Therefore, the output Ve of the operational amplifier 805 forming the inverting adder becomes Ve = VB. However, when one of the detectors 601, 602, 603 becomes abnormal, the output relationship of each detector becomes

IA + S · Cp · VC + IL ≠ 0

Therefore, the output Ve of the operational amplifier 805 forming the inverting adder becomes Ve ≠ VB. Further, when a failure such as the output voltage of the operational amplifier 805 becomes 0V, the output Ve of the operational amplifier 805 becomes Ve ≠ VB. Therefore, the output Ve of the operational amplifier 805 is Ve ≠ VB
If so, it may be considered that the detector is abnormal, but in reality, since the detector has a detection error, the reference voltage generators 813a, 813
Outputs VRA and VRB of 13b are voltages (VRA = + VSE) obtained by adding positive and negative voltages ± VSE according to the error to the bias voltage VB.
+ VB, VRB = -VSE + VB), and the comparators 812a and 812b may be compared as in the first embodiment.

In the configuration of the eighth embodiment, the abnormality of the detector can be detected without duplicating the detectors 601, 602 and 603 as in the seventh embodiment, and further, the abnormality of the operational amplifier 805 (the operational amplifier (When the output voltage of 805 becomes 0) can be detected.

Example 9. FIG. 11 is a block diagram showing the ninth embodiment. 11, parts corresponding to those in FIG. 7 are designated by the same reference numerals, and detailed description thereof will be omitted. The difference from the seventh embodiment is that in the judging means of the seventh embodiment, the output of each detector is added by an inverting adder composed of a resistor and an operational amplifier, whereas in the ninth embodiment, the output of the resistor R21, R2
The second embodiment is similar to the seventh embodiment in that the determining means is configured to add the outputs of the detectors by R2 and R23.

The resistors R21, R22 and R23 are connected to R21 =
When R22 = R23, the voltage Ve at the butt point of the resistors R21, R22, and R23 is

Ve = (IA + S · Cp · VC + IL) / 3

It becomes: Therefore, each detector 601, 60
When 2,603 is normal, the relation of the output of each detector is

IA + S.Cp.VC + IL = 0

Therefore, the resistors R21, R22 and R23 are
The voltage Ve at the matching point becomes 0. However, when one of the detectors 601, 602, 603 becomes abnormal, the output relationship of each detector becomes

IA + S · Cp · VC + IL ≠ 0

Therefore, the voltage Ve at the matching point of the resistors R21, R22 and R23 is Ve ≠ 0. So Ve
If ≠ 0, the detector may be considered abnormal, but in reality,
Since the detector has a detection error, the reference voltage generator 813
The outputs VRA and VRB of a and 813b may be positive and negative voltages ± VSE (VRA = + VSE, VRB = −VSE) according to the error, and may be compared by the comparator 812a and the comparator 812b.

In the configuration of the ninth embodiment, the abnormality of the detector can be detected without duplicating the detectors 601, 602 and 603 as in the seventh embodiment, and the circuit configuration is simplified. be able to.

Example 10. FIG. 12 is a block diagram showing the tenth embodiment. 12, parts corresponding to those in FIG. 11 are designated by the same reference numerals, and detailed description thereof will be omitted. The tenth embodiment is different from the ninth embodiment in that a bias voltage generator 833 and a resistor R24 are added to the judging means of the ninth embodiment to constitute the judging means, and the other points are the same as those of the ninth embodiment.

The resistors R21, R22, R23 and R24 are
If R21 = R22 = R23 = R24, the resistance R21,
The voltage Ve at the matching point of R22, R23, and R24 is

Ve = (IA + S.Cp.VC + IL + VB) / 4

It becomes Therefore, each detector 601, 60
When 2,603 is normal, the relation of the output of each detector is

IA + S.Cp.VC + IL = 0

Therefore, the resistors R21, R22 and R2 are
3, the voltage Ve at the matching point of R24 is Ve = VB / 4
Becomes However, when one of the detectors 601, 602, 603 becomes abnormal, the output relationship of each detector becomes

IA + S.Cp.VC + IL ≠ 0

Therefore, the resistors R21, R22, R23, R
The voltage Ve at the matching point of 24 is Ve ≠ VB / 4. Further, when the wiring from the matching point of R21, R22, R23, and R24 to the comparators 812a and 812b is broken, the input voltage Va of the comparators 812a and 812b is Va.
≠ Ve. Therefore, if Va is not equal to VB / 4, it may be considered that the detector is abnormal or the wiring is broken. However, in reality, the detector has a detection error.
Outputs VRA and VRB of 13a and 813b are bias voltage V
A voltage (VRA = + VSE + VB / 4, which is a value obtained by dividing B by 4 (VB / 4) and adding positive and negative voltages ± VSE according to the error, (VRA = + VSE + VB / 4,
VRB = -VSE + VB / 4), and the comparators 812a and 812b may be compared as in the first embodiment.

In the structure of the tenth embodiment, similar to the ninth embodiment, the detectors 601, 602 and 603 are not duplicated,
It is possible to detect the abnormality of the detector with a simple circuit configuration.
Furthermore, the wiring to the comparator is broken (Ve is
In such a case), it can be detected.

Example 11. Next, FIG. 13 is a block diagram showing an eleventh embodiment. 13, parts corresponding to those in FIG. 7 are designated by the same reference numerals, and detailed description thereof will be omitted.
The eleventh embodiment differs from the seventh embodiment in that detectors 601 and 6 are provided.
The outputs of 02 and 603 are digitized by the multiplexer 809 and the A / D converter 810.
The point is that the determination means is configured by adding the D converter 810. Others are the same as in the seventh embodiment.

In FIG. 13, each of the detectors 601 and 60 is
The inverter current IA, the load current IL, and the output voltage VC, which are the outputs of 2, 603, are switched by the multiplexer 808, digitized by the A / D converter 809, and detected by the microprocessor 850.

The error of the detectors 601, 602, 603 is
Since the error range varies depending on the detector rating, accuracy, etc., the value of the reference voltage generator must be changed.
Since it is digitized by the D converter and detected by the microprocessor or the like, the detected value can be easily changed.

In the structure of the eleventh embodiment, the detectors 601, 602 and 603 are not duplicated as in the seventh embodiment,
The abnormality of the detector can be detected, and the abnormality detection value can be easily changed.

Example 12. FIG. 14 is a block diagram showing the twelfth embodiment. 14, parts corresponding to those in FIG. 13 are designated by the same reference numerals, and detailed description thereof will be omitted. The difference from the eleventh embodiment is that each detector has A
The D / D converters 809a, 809b, and 809c are provided for digitization.
Is the same as.

In FIG. 14, each of the detectors 601 and 60
A / D converters 809a, 80 for each of the inverter current IA, the load current IL, and the output voltage VC, which are the outputs of 2, 603.
Digitization is performed by 9b and 809c, and detection is performed by the microprocessor 850.

Even if one of the A / D converters 809a, 809b, 809c for digitizing the output of each detector becomes abnormal,

IA + S.Cp.VC + IL ≠ 0

Therefore, the abnormality of the A / D converter can be detected.

In the configuration of the twelfth embodiment, the abnormality of the detector can be detected without duplicating the detectors 601, 602 and 603 as in the eleventh embodiment, and the abnormality detection value can be easily detected. It can be changed, and in addition, A /
Abnormalities of the D converters 809a, 809b, 809c can also be detected.

Furthermore, in the above-mentioned seventh to twelfth embodiments, the case of the single-phase inverter has been described, but by using the same abnormality detection circuit for each phase, it can be applied to the three-phase inverter.

Furthermore, although the case of the inverter has been described in the above description, the invention can be similarly applied to a converter for converting AC power into DC power.

[0132]

Since the present invention is constructed as described above, it has the following effects.

According to the abnormality detecting circuit of the power converter according to claim 1 of the present invention, the power converter is provided with a detector for detecting the output current of each phase of the power converter on the output side of the power converter. In the abnormality detection circuit, the detector outputs are added, and when the added value reaches a predetermined value, a determination means for determining that the detector is abnormal is provided, so that the abnormality of the detector can be determined. Therefore, a highly reliable abnormality detection circuit for the power converter can be obtained without duplicating the detector.

According to the abnormality detecting circuit for a power converter according to claim 2 of the present invention, a detector for detecting each line output voltage of the power converter is provided on the output side of the power converter for generating a multi-phase alternating current. In the abnormality detection circuit of the power converter provided, the output of the detector is added, and when the added value reaches a predetermined value, a determination means for determining that the detector is abnormal is provided. To be able to judge
Therefore, a highly reliable abnormality detection circuit for the power converter can be obtained without duplicating the detector.

According to a third aspect of the present invention, there is provided an abnormality detection circuit for a power converter, wherein in the abnormality detection circuit for a power converter according to the first or second aspect, the determining means determines the output of the detector. Since the addition is performed by the adder including the operational amplifier and the resistor, the abnormality of the detector can be determined with a simple configuration.

According to a fourth aspect of the present invention, there is provided an abnormality detection circuit for a power converter, wherein in the abnormality detection circuit for a power converter according to the first or second aspect, the determining means is the output of the detector. When a predetermined fixed bias voltage is added by an adder composed of an operational amplifier and a resistor, it is possible to judge the abnormality of the detector and the output voltage becomes 0 due to the abnormality of the operational amplifier. Can also be detected.

According to a fifth aspect of the present invention, there is provided an abnormality detection circuit for a power converter, wherein in the abnormality detection circuit for a power converter according to the first aspect or the second aspect, the determining means determines the output of the detector. Since the addition is made using a plurality of resistors, it is possible to determine the abnormality of the detector with a simple configuration.

According to a sixth aspect of the present invention, there is provided an abnormality detection circuit for a power converter, wherein in the abnormality detection circuit for a power converter according to the first or second aspect, the determining means is the output of the detector. Since a predetermined fixed bias voltage is added by a plurality of resistors, it is possible to judge the abnormality of the detector with a simple configuration and also detect the case where the potential becomes 0 due to the disconnection of the wiring. can do.

According to a seventh aspect of the present invention, there is provided the abnormality detection circuit for a power converter, wherein in the abnormality detection circuit for a power converter according to the first or second aspect, the judging means determines the output of the detector. Digitization by one A / D converter and multiplexer with multiple channels
Since the processor detects the abnormality of the detector,
It is possible to determine the abnormality of the detector, and it is possible to easily determine the predetermined value for determining the abnormality.

According to the abnormality detecting circuit of the power converter according to claim 8 of the present invention, in the abnormality detecting circuit of the power converter according to claim 1 or 2, the judging means outputs the output of the detector. Since it is digitized by a plurality of A / D converters and the abnormality of the detector is detected by the microprocessor, the abnormality of the detector can be judged and the abnormality of the A / D converter can also be judged. can do.

According to the abnormality detecting circuit of the power converter of the ninth aspect of the present invention, the switching element is configured to generate a multi-phase AC output by performing switching a plurality of times within one cycle. In the abnormality detection circuit of the power converter, a detector for detecting the output current, the output voltage, and the load current of the power converter, a value corresponding to the differential value of the output voltage, and the output detected by the detector. When the current and the load current are added and the added value reaches the specified value,
Since it has a determining means for determining that the detector is abnormal,
It is not necessary to duplicate the detectors for the output current, output voltage and load current of the converter.

According to a tenth aspect of the power converter abnormality detection circuit of the present invention, in the power converter abnormality detection circuit of the ninth aspect, the determination means uses the operational amplifier and a resistor to output the detector output. Since the addition is performed by the configured adder, it is possible to determine the abnormality of the detector with a simple configuration.

According to the eleventh aspect of the power converter abnormality detecting circuit of the present invention, in the abnormality detecting circuit of the power converter according to the ninth aspect, the judging means is fixed to the output of the detector in a predetermined manner. Since the bias voltage and the bias voltage are added by an adder composed of an operational amplifier and a resistor, the abnormality of the detector can be determined with a simple configuration, and the output voltage becomes 0 due to the abnormality of the operational amplifier. Cases can be detected and reliability can be further improved.

According to a twelfth aspect of the power converter abnormality detection circuit of the present invention, in the power converter abnormality detection circuit of the ninth aspect, the judging means uses the plurality of resistors to output the output of the detector. Since the addition is performed, the detector abnormality can be detected with a simple configuration.

According to the thirteenth aspect of the power converter abnormality detection circuit of the present invention, in the power converter abnormality detection circuit of the ninth aspect, the determination means is fixed to the output of the detector in a predetermined manner. Since the bias voltage and the bias voltage are added by a plurality of resistors, it is possible to detect an abnormality of the detector and also to detect the case where the potential becomes 0 due to the disconnection of the wiring. It can be increased.

According to a fourteenth aspect of the power converter abnormality detection circuit of the present invention, in the power converter abnormality detection circuit of the ninth aspect, the judging means outputs one A / A signal from the detector. Since it is digitized by the D converter and the multiplexer having a plurality of channels and the abnormality of the detector is detected by the microprocessor, it is possible to determine the abnormality of the detector and the predetermined value for determining the abnormality. Can be easily determined.

According to a fifteenth aspect of the power converter abnormality detection circuit of the present invention, in the power converter abnormality detection circuit of the ninth aspect, the determination means outputs the output of the detector to a plurality of A / A. Digitized by D converter,
Since the processor detects the abnormality of the detector, the abnormality of the detector can be determined and A
It is also possible to determine the abnormality of the / D converter.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

FIG. 4 is a block diagram showing a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a fifth embodiment of the present invention.

FIG. 6 is a block diagram showing a sixth embodiment of the present invention.

FIG. 7 is a block diagram showing a seventh embodiment of the present invention.

FIG. 8 is a main circuit diagram of a power converter.

FIG. 9 is a diagram illustrating a pulse width modulation circuit.

FIG. 10 is a block diagram showing an eighth embodiment of the present invention.

FIG. 11 is a block diagram showing Embodiment 9 of the present invention.

FIG. 12 is a block diagram showing a tenth embodiment of the present invention.

FIG. 13 is a block diagram showing an eleventh embodiment of the present invention.

FIG. 14 is a block diagram showing a twelfth embodiment of the present invention.

FIG. 15 is a block diagram showing a conventional technique.

[Explanation of symbols]

1 inverter main circuit, 2 reactors, 3 capacitors, 4 loads, 601U, 601V, 601W detectors, 601, 602, 603 detectors, 803, 81
3, 833 Reference voltage generator, 802, 812 comparator, 805 operational amplifier, 801 rectifier circuit, 807
OR circuit, 808 multiplexer, 809 A / D converter, 800 differentiator, 901 AC sine wave reference voltage generation circuit, 902 capacitor current command generation circuit, 903 clock generation circuit, 905 limiter, 906 current control amplifier, 908 PWM modulation circuit, 910 voltage control amplifier, 810, 909, 911, 912 adder / subtractor circuit,
R11 to R15, R21 to R25 resistors.

Claims (15)

[Claims] 1. An abnormality detection circuit of a power converter, comprising a detector for detecting output currents of respective phases of the power converter on the output side of the power converter, adding outputs of the detectors, and adding the sum. Is a predetermined value, the abnormality detection circuit for a power converter is provided with a determination means for determining an abnormality in the detector. 2. An abnormality detection circuit for a power converter, comprising a detector for detecting each line output voltage of the power converter on the output side of the power converter for generating a multi-phase alternating current. When the added value reaches the specified value,
An abnormality detection circuit for a power converter, comprising a determination means for determining that the detector is abnormal. 3. The abnormality detection circuit for a power converter according to claim 1 or 2, wherein the determination means adds the output of the detector by an adder composed of an operational amplifier and a resistor. 4. The determining means adds the output of the detector and a predetermined fixed bias voltage by an adder composed of an operational amplifier and a resistor. Abnormality detection circuit of power converter. 5. The abnormality detection circuit for a power converter according to claim 1 or 2, wherein the determination means adds the outputs of the detector by a plurality of resistors. 6. The power converter abnormality detection according to claim 1 or 2, wherein the determination means adds the output of the detector and a predetermined fixed bias voltage by a plurality of resistors. circuit. 7. The judgment means outputs the output of the detector as 1
3. An abnormality detection circuit for a power converter according to claim 1, wherein the abnormality detection circuit is digitized by one A / D converter and a multiplexer having a plurality of channels, and an abnormality of the detector is detected by a microprocessor. 8. The determination means digitizes the output of the detector by a plurality of A / D converters,
The abnormality detection circuit of the power converter according to claim 1 or 2, wherein the processor detects an abnormality of the detector. 9. An abnormality detection circuit for a power converter configured to generate a multi-phase AC output by a switching element performing switching a plurality of times within one cycle, and an output current of the power converter. And a detector for detecting the output voltage and the load current, respectively, and a value corresponding to the differential value of the output voltage and the output current and the load current detected by the detector are added, and the added value becomes a predetermined value. An abnormality detection circuit for a power converter, comprising: a determination unit that determines that the abnormality of the detector has occurred. 10. The abnormality detection circuit for a power converter according to claim 9, wherein the determination means adds the output of the detector by an adder composed of an operational amplifier and a resistor. 11. The power converter according to claim 9, wherein the determination means adds the output of the detector and a predetermined fixed bias voltage by an adder configured by an operational amplifier and a resistor. Abnormality detection circuit. 12. The abnormality detection circuit for a power converter according to claim 9, wherein the determination means adds the outputs of the detector by a plurality of resistors. 13. The abnormality detection circuit for a power converter according to claim 9, wherein the determination means adds the output of the detector and a predetermined fixed bias voltage with a plurality of resistors. 14. The determination means digitizes the output of the detector by a multiplexer having one A / D converter and a plurality of channels, and detects an abnormality of the detector by a microprocessor. Claim 9
Abnormality detection circuit of power converter. 15. The determination means digitizes the output of the detector by a plurality of A / D converters,
The abnormality detection circuit for a power converter according to claim 9, wherein the abnormality of the detector is detected by a processor.