JPH07288288A - Wiring method for integrated circuit device - Google Patents

Abstract

(57) [Summary] [Purpose] A wiring method of an integrated circuit device, in which cross wiring is performed.
The contact area can be reduced by reducing the number of contact holes.
Use local wiring that can be reduced. [Constitution] p⁺Type silicon substrate 1 grown on p-type silicon substrate 1
The field oxide film 3 and the p-type region 2 on the recon layer 2₁And n
Mold area 2₂And gate oxide film 4₁, 4₂Forming on it
A polycrystalline silicon film 5 and a silicon oxide film 6 are formed on the
Electrode 5₁, 5 ₂And wiring 5₃Silico planning to form
Part of the silicon oxide film 6 is removed,
Gate electrode by patterning the polycrystalline silicon film 5
5₁, 5₂And wiring 5₃Forming the gate electrode 5₁, 5₂
Source mask 2₁₁, 2_{twenty one}And drain region 2
₁₂, 2_{twenty two}Forming a metal silicide layer 8 on the exposed surface
₁₁Is formed and the drain region 2 is formed.₁₂, 2_{twenty two}From wiring 5
₃Or other metal FET on the surface of the gate electrode of FET
Id layer 8₁₁Local wiring is formed over.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device wiring method, and more particularly to a high density CMOS static memory cell wiring method.

[0002]

2. Description of the Related Art In recent years, semiconductor memory devices have been highly integrated, and there is still a strong demand for further improvement in the degree of integration.

Conventionally, in a CMOS static memory cell on a silicon substrate, a plurality of CMOS transistor matrixes are formed, and then an interlayer insulating film is formed on a source region, a drain region and a gate electrode. A contact hole reaching the source region, the drain region, and the gate electrode is formed on the surface, a metal film is formed on the entire surface including the contact hole, and the metal film is patterned to form the drain region of the nMOS transistor and the drain of the pMOS transistor. Between the regions, or the drain region of the nMOS transistor and the pMOS
The drain region of the transistor and the gate of another CMOS transistor are connected.

In such a conventional wiring method, when forming a contact hole, in addition to the size of the contact hole itself, the margin of the contact hole with respect to the diffusion region such as the source region and the drain region and the gate electrode and the wiring. A contact hole margin is required.

To add a further explanation, for example, when a contact hole is formed in a diffusion layer which is a source region or a drain region and a misalignment occurs, a field oxide film that defines an element forming region is formed. This will etch the edge and destroy the underlying pn junction for element isolation, resulting in a leakage current.
In addition, when a contact hole is formed with respect to the gate electrode and misalignment occurs, there is a problem that the oxide film near the gate electrode penetrates or the contact hole has an insufficient effective area, resulting in poor contact. Was occurring.

In order to avoid such a problem, it is necessary to secure a sufficient margin for this alignment, and especially in a large-capacity storage device (memory cell) having a large number of contact holes. Difficult to convert.

Conventionally, as a method for wiring between a source region, a drain region, and a gate electrode without forming a contact hole, a method of using auxiliary local wiring in addition to ordinary metal wiring has been disclosed in T. Introduced by Tang et al. (I
EEE International Electro
n Device Meeting 85 (198)
5). Technical Digest pp. 59
0-593).

FIG. 8 shows a conventional wiring method for an integrated circuit device.
It is explanatory drawing, (A) shows a cross section, (B) is the circuit.
Is shown. In this figure, 61 is p⁺Type silicon base
Plate, 62 is a p-type silicon crystal layer, 62 ₁Is a p-type region, 6
Two₂Is an n-type region, 62₁₁, 62_{twenty one}Is the source region, 6
Two₁₂, 62 _{twenty two}Is a drain region, 63 is a field oxide
Film, 64 is a gate insulating film, 65₁, 65₂Is a gate
Pole, 65₃Is wiring, 66₁₁, 66₁₂, 66_{twenty one}, 66_{twenty two}，
66₃₁, 66₃₂Is the sidewall, 67₁₁, 67₁₂, 6
7₁₃, 67_{twenty one}, 67_{twenty two}, 67_{twenty three}, 67₃Is a silicide
The layer 68 is a local wiring.

A wiring method of a conventional integrated circuit device will be described with reference to this explanatory diagram. It should be noted that, in this description, many actually performed steps are collectively described as appropriate.

First Step First, a p-type silicon crystal layer 62 is epitaxially grown on a p ⁺ -type silicon substrate 61, and p-type impurities and n-type impurities are selectively introduced into the surface of the p-type silicon crystal layer 62. To form a p-type region 62 ₁ and an n-type region 62 ₂ . Then, by forming a field oxide film 63 on the p-type region 62 ₁ and the n-type region 62 _2, p-type region 62 ₁ and the n-type region 62
₂ defines a MOSFET formation region.

Second Step The surface of the MOSFET formation region is thermally oxidized to form a gate insulating film 64, a polycrystalline silicon film is formed on the entire surface thereof, and the polycrystalline silicon film is patterned to form a p-type region. Gate electrodes 65 ₁ and 65 ₂ and a wiring 65 ₃ are formed in the MOSFET forming regions of 62 ₁ and the n-type region 62 ₂ .

Third step The gate electrode 65 ₁ is used as a mask in a state of covering the n-type region 62 ₂ and n is formed in the p-type region 62 ₁ on both sides of the gate electrode 65 _1.
A type impurity is ion-implanted to form an n-type source region 62 ₁₁ and a drain region 62 ₁₂ . On the contrary, the p-type region 6
With the gate electrode 65 ₂ as a mask in a state of covering 2 ₁ , p-type impurities are ion-implanted into the n-type regions 62 ₂ on both sides of the gate electrode 65 ₂ to form p-type source regions 62 ₂₁ and drain regions 62 ₂₂ . To do.

Fourth step: A SiO ₂ film is formed on the entire surface by CVD, and this SiO ₂ film is formed.
_By anisotropically etching the _two films by RIE, side walls 6 are formed on the side surfaces of the gate electrodes 65 ₁ and 65 _2.
6 ₁₁ , 66 ₁₂ , 66 ₂₁ , 66 ₂₂ are formed, and side walls 66 ₃₁ , 66 ₃₂ are formed on the side surfaces of the wiring 65 ₃ .

Fifth Step Then, the source region 62 ₁₁ , the drain region 62 ₁₂ , the source region 62 ₂₁ and the drain region 62 which are single crystal silicon.
₂₂ and low-resistance silicide layers 67 ₁₁ , 67 ₁₂ , 67 ₁₃ , 67 ₂₁ , 6 ₂ by siliciding the surfaces of the gate electrode 65 ₁ , the gate electrode 65 ₂ , and the wiring 65 _{3 made} of polycrystalline silicon.
7 _22, 67 _23, 67 ₃ to form a.

[0015] Following the sixth step to form a titanium nitride film on the entire surface over the entire surface, the silicide layer 67 _12, 67 _22, 67 ₃ and the local and patterned to include other gates of the CMOS transistors P _2, N ₂ The wiring 68 is formed. Then, an interlayer insulating film is deposited by a conventionally known process, contact holes are opened, and metal wiring is formed through these contact holes.

According to this method, the contact area for the metal wiring layer is not required at the cross-connecting portion of the inverter, and the cell area can be reduced accordingly.

[0017]

The above-mentioned method using the local wiring, which has been proposed so far, can surely reduce the contact hole and is effective in reducing the size of the integrated circuit device. Since the silicide layer is exposed on the surface of the wiring, the wiring cannot be crossed with the gate electrode, and the applicable range is considerably limited.
In view of this inconvenience, the present invention provides an integrated circuit device having a local wiring which can be wired by arbitrarily intersecting with or in contact with the gate electrode and which does not impair the advantage of reducing the area by reducing the contact hole. The purpose is to provide.

[0018]

In a wiring method for an integrated circuit device according to the present invention, a step of forming a wiring material film on a substrate and a step of forming an insulating material film on the wiring material film. Forming a wiring by selectively removing a part of the insulating material film, which is to be formed with the wiring material film, and patterning a two-layer film including the insulating material film and the wiring material film And a step of forming an insulating film on the side surface of the wiring, and a step of forming a local wiring connecting the surface of the substrate and the surface of the wiring.

In this case, the insulating material film formed on the wiring material film is substantially transparent to the wavelength of the exposure light used when patterning the wiring material film and the insulating material film by a photolithography process. And the film thickness can be an integral multiple of a half wavelength of the exposure light in the insulating material film.

In another integrated circuit device wiring method according to the present invention, a step of depositing a wiring material film on a substrate, a step of forming an insulating material film on the wiring material film, Forming a wiring by patterning a two-layer film consisting of a material film and the wiring material film; removing a part of the insulating material film above the wiring; and forming an insulating film on the side surface of the wiring. And a step of forming a local wiring connecting the surface of the substrate and the surface of the wiring.

In these cases, the surface of the substrate can be a source region or a drain region and the wiring can be a gate electrode or the like.

[0022]

FIG. 1 is a diagram for explaining the principle of the wiring method for an integrated circuit device according to the present invention, in which (A) and (B) show respective steps. The process when the present invention is applied to the manufacture of a CMOS static memory cell will be described with reference to this drawing.

In this figure, 1 is a p ⁺ type silicon substrate,
2 p-type silicon layer, 2 ₁ p-type region, 2 ₂ n-type region, 2 _11, 2 ₂₁ source region, 2 _12, 2 ₂₂ drain region, 3 a field oxide film, 4 _1, 4 ₂ Is a gate oxide film, 5 is a polycrystalline silicon film, 6 is a silicon oxide film,
5 ₁ , 5 ₂ are gate electrodes, 5 ₃ are wirings, 6 ₁ , 6 ₂ , 6
₃ is an opening, 7 ₁₁ , 7 ₁₂ , 7 ₂₂ , 7 ₂₁ , 7 ₃₁ , 7 ₃₂ is a sidewall, 8 ₁₁ , 8 ₁₂ , 8 ₁₃ , 8 ₂₁ , 8 ₂₂ , 8 ₂₃ , 8
₃ is a metal silicide layer, 9 is a local wiring, 10 is an interlayer insulating film, 10 ₁₁ , 10 ₁₂ , 10 ₂₂ , 10 ₂₁ are contact holes, and 11 ₁₁ , 11 ₁₂ , 11 ₂₂ , 11 ₂₁ are metal wirings.

First, a p-type silicon layer 2 is deposited on a p ⁺ -type silicon substrate 1, and an n-type impurity and a p-type impurity are selectively introduced to form a p-type region 2 ₁ which becomes an active layer of an n-channel MOSFET. And n serving as the active layer of the p-channel MOSFET
The type region 2 ₂ is formed, and then the field oxide film 3 is formed around the p-type region 2 ₁ and the n-type region 2 ₂ around the MOSFET formation region.

P-type region 2₁And n-type region 2₂Surface of hot acid
Gate oxide film 4₁, 4₂Forming the whole surface on it
A polycrystalline silicon film 5 is formed on the
Oxide film 6 is grown, and the polycrystalline silicon film 5 is used as a gate.
Electrode 5₁, 5₂And wiring 5₃The area that will form the
By selectively removing a part of the silicon oxide film 6 of
6 ₁, 6₂, 6₃(See Fig. 1 (A).
See).

Next, the opening 6₁, 6₂, 6₃Having
A two-layer film composed of the recon oxide film 6 and the polycrystalline silicon film 5
Gate electrode 5 after patterning₁, 5₂And wiring 5₃Shape
N-type region 2₂Gate electrode 5 with the top covered
₁With p as a mask ₁Ion implantation of n-type impurities
Enter the source area 2₁₁And drain region 2₁₂To form
On the contrary, p-type region 2₁With the top covered,
Pole 5₂With n as a mask₂P-type impurities to
Drain region 2_{twenty two}And source area 2_{twenty one}To form
It

Next, on the side surfaces of the gate electrodes 5 ₁ , 5 ₂ and the wiring 5 ₃ , side walls 7 ₁₁ , 7 ₁₂ , 7 ₂₂ , 7 ₂₁ , 7 ₃₁ ,
7 ₃₂ are formed and are exposed on the surface of the source region 2 ₁₁ , the drain region 2 ₁₂ , and the drain region 2 ₂₂ , which are made of single crystal.
The metal silicide layers 8 ₁₁ , 8 ₁₂ , 8 ₁₃ , 8 ₂₁ , 8 ₂₂ , 8 ₂₃ , 8 are formed on the upper surfaces of the source region 2 ₂₁ , the gate electrodes 5 ₁ and 5 _{2 made of} the polycrystalline silicon film 5, and the wiring 5 _{3. 3} is formed, a tungsten film is deposited on the entire surface, and the tungsten film is patterned so as to remain on the region including the metal silicide layers 8 ₁₂ , 8 ₂₂ , and 8 ₃ to form the local wiring 9. The contact hole 1 formed in the interlayer insulating film 10 by depositing the interlayer insulating film 10 by the process
Metal wiring 1 through 0 ₁₁ , 10 ₁₂ , 10 ₂₂ and 10 ₂₁
1 ₁₁ , 11 ₁₂ , 11 ₂₂ , and 11 ₂₁ are formed (above, FIG.
(See (B)).

As described above, the polycrystalline silicon film 5
A part of the silicon oxide film 6 formed on the gate electrode 5 is selectively removed by etching, and then a two-layer film composed of the silicon oxide film 6 and the polycrystalline silicon film 5 is patterned to form the gate electrode 5
_1, 5 ₂ and instead of forming the wiring _3, after forming the gate electrode 5 _1, 5 ₂ and the wiring 5 ₃ by patterning the two-layer film composed of a silicon oxide film 6 of a polycrystalline silicon film 5 It is also possible to selectively remove a part of the silicon oxide film 6 by etching.

When the insulating film is deposited on the wiring material film formed on the substrate as in the wiring method of the integrated circuit device of the present invention, insulation of the connection portion between the wiring formed by the wiring material film and the local wiring is performed. Whether the step of selectively removing the film is before or after patterning the wiring, the thickness of this insulating film does not need to be as thick as that of the interlayer insulating film. Forming an excessive opening in this insulating film,
Alternatively, even if an opening is formed at a position deviating from the wiring pattern, the step of forming this opening does not cause etching through a thick field oxide film or the like.

Further, in this case, when the wiring is the gate electrode of the MOSFET, it is not necessary to take a margin for alignment required in the prior art, and the insulating film may be removed larger than the wiring pattern. Good. Therefore, when forming the contact hole, there is no increase in the area due to the processing margin, and it is possible to form another wiring by intersecting with the remaining portion without removing the insulating film.

[0031]

EXAMPLES Examples of the present invention will be described below. (First Embodiment) FIGS. 2 and 3 are views for explaining the manufacturing process of the CMOS static memory cell of the first embodiment.
(A)-(F) has shown each process.

In this figure, 1 is a p ⁺ type silicon substrate,
2 p-type silicon layer, 2 ₁ p-type region, 2 ₂ n-type region, 2 _11, 2 ₂₁ source region, 2 _12, 2 ₂₂ drain region, 3 a field oxide film, 4 _1, 4 ₂ Is a gate oxide film, 5 is a polycrystalline silicon film, 5 ₁ and 5 ₂ are gate electrodes,
5 ₃ is wiring, 6 is a silicon oxide film, 6 ₁ , 6 ₂ , 6 ₃ are openings, 7 ₁₁ , 7 ₁₂ , 7 ₂₁ , 7 ₂₂ , 7 ₃₁ and 7 ₃₂ are sidewalls, 8 ₁₁ , 8 ₁₂ and 8 ₁₃ , 8 ₂₁ , 8 ₂₂ , 8 ₂₃ , and 8 ₃ are metal silicide layers, 9 is local wiring, 10 is an interlayer insulating film,
10 ₁₁ , 10 ₁₂ , 10 ₂₁ , 10 ₂₂ are contact holes,
11 ₁₁ , 11 ₁₂ , 11 ₂₁ , and 11 ₂₂ are metal wirings.
A method of manufacturing the CMOS static memory cell of the first embodiment will be described with reference to the process explanatory drawing.

First Step (See FIG. 2A) A p-type silicon layer 2 is deposited on the p ⁺ -type silicon substrate 1 by epitaxial growth, and n-type impurities are introduced to n.
The p-type region 2 ₁ as the active layer of the channel MOSFET is formed, to form an n-type region 2 ₂ to be the active layer of the p-channel MOSFET by introducing a p-type impurity. Then, a field oxide film 3 is formed around the MOSFET formation regions of the p-type region 2 ₁ and the n-type region 2 ₂ by the LOCOS method.

Second step (see FIG. 2B) The surfaces of the p-type region 2 ₁ and the n-type region 2 ₂ are thermally oxidized to form gate oxide films 4 ₁ and 4 ₂ having a film thickness of 7 nm.
A polycrystalline silicon film 5 having a film thickness of 180 nm is formed on the entire surface by chemical vapor deposition (CVD), and a silicon oxide film 6 having a film thickness of 100 nm is grown on the entire surface by CVD.

Part of the silicon oxide film 6 on the gate electrodes 5 ₁ and 5 ₂ and the wiring 5 ₃ formed by the polycrystalline silicon film 5 in the fourth step after the third step (see FIG. 2C). Are selectively removed by a photolithography process to form openings 6 ₁ , 6 ₂ and 6 ₃ .

Fourth step (see FIG. 3D) The opening 6 is formed in the third step.₁, 6₂, 6₃Formed silicon
By patterning the oxide film 6 and the polycrystalline silicon film 5,
Electrode 5₁, 5₂And wiring 5₃To form. Then n
Mold area 2₂Gate electrode 5 with the top covered₁The mass
P-type region 2₁N-type impurities are ion-implanted into the
Source area 2₁₁And drain region 2₁₂To form. Also, the reverse
In the p-type region 2₁Gate electrode 5 with the top covered₂
With n as a mask₂Ion implantation of p-type impurities
Then drain region 2_{twenty two}And source area 2 _{twenty one}To form.

Fifth step (see FIG. 3E) A 100 nm-thickness silicon oxide film is deposited on the entire surface by the CVD method, and this silicon oxide film is etched by anisotropic reactive ion etching (RIE). ,
The sidewalls 7 ₁₁ , 7 ₁₂ , 7 ₂₂ , 7 ₂₁ , and 7 ₂₁ , are selectively left only on the side surfaces of the gate electrodes 5 ₁ and 5 ₂ and the wiring 5 ₃ .
7 ₃₁ and 7 ₃₂ are formed. Then exposed on the surface,
A refractory metal is formed on the upper surfaces of the source region 2 ₁₁ , the drain region 2 ₁₂ , the drain region 2 ₂₂ , the source region 2 ₂₁ and the gate electrodes 5 ₁ and 5 ₂ and the wiring 5 _{3 which} are made of the polycrystalline silicon film 5 and which are made of single crystal. , For example, by selectively reacting cobalt, the metal silicide layers 8 ₁₁ , 8 ₁₂ , 8 ₁₃ , 8 ₂₂ , 8 ₂₁ ,
8 ₂₃ and 8 ₃ are formed.

Sixth step (see FIG. 3F) A tungsten film having a film thickness of 80 nm, for example, is deposited on the entire surface,
This tungsten film is used as a metal silicide layer 8 ₁₂ , 8 ₂₂ , 8
_The local wiring 9 is formed by patterning so as to leave it on the region including ₃ . Then, an interlayer insulating film 10 is deposited by a conventionally known process to form contact holes 10 ₁₁ , 10 ₁₂ , 10 ₂₂ , and 10 ₂₁ ,
Metal wiring 11 ₁₁ , 1 through these contact holes
1 ₁₂ , 11 ₂₂ , and 11 ₂₁ are formed.

(Second Embodiment) FIGS. 4 and 5 show a second embodiment.
Of CMOS static memory cell manufacturing process
And (A) to (F) show each step. This figure
21 is p⁺Type silicon substrate, 22 is p type silicon
Layer, 22₁Is a p-type region, 22₂Is an n-type region, 22₁₁，
22_{twenty one}Is the source region, 22₁₂, 22_{twenty two}Is the drain region,
23 is a field oxide film, 24₁, 24₂Gate oxidation
Film, 25 is a polycrystalline silicon film, 25₁, 25₂Is the gate
Electrode, 25₃Is wiring, 26, 26 ₁, 26₂, 26₃Is
Silicon nitride film, 26₁₁, 26_{twenty one}, 26₃₁Is an opening, 27
₁₁, 27₁₂, 27_{twenty one}, 27_{twenty two}, 27₃₁, 27₃₂Is the side
Wall, 28₁₁, 28₁₂, 28₁₃, 28_{twenty one}, 28_{twenty two}，
28_{twenty three}, 28₃Is a metal silicide layer, 29 is a local wiring,
30 is an interlayer insulating film, 30₁₁, 30₁₂, 30_{twenty one}, 30_{twenty two}Is
Contact hole, 31₁₁, 31₁₂, 31_{twenty one}, 31_{twenty two}Is
It is a metal wiring. This process explanatory drawing shows the second embodiment.
A method of manufacturing a CMOS static memory cell will be described.
It

First step (see FIG. 4A) A p-type silicon layer 22 is deposited on a p ⁺ -type silicon substrate 21 by epitaxial growth, and n-type impurities are introduced to form an active layer of an n-channel MOSFET. Mold area 22
₁ is formed and p-type impurities are introduced to p-channel MOSF
An n-type region 22 ₂ to be the active layer of ET is formed. Next, a field oxide film 23 is formed around the MOSFET formation regions of the p-type region 22 ₁ and the n-type region 22 ₂ by the LOCOS method.

Second step (see FIG. 4B) The surfaces of the p-type region 22 ₁ and the n-type region 22 ₂ are thermally oxidized to form gate oxide films 24 ₁ and 24 ₂ having a film thickness of 7 nm. A film thickness of 180n is formed on the entire upper surface by the CVD method.
m polycrystalline silicon film 25 is deposited, and C is deposited on the entire surface.
A 100-nm-thick silicon nitride (Si ₃
The N ₄ ) film 26 is grown.

Third step (see FIG. 4C) The silicon nitride film 26 and the polycrystalline silicon film 25 are patterned.
The silicon nitride film 26₁, 26₂, 26₃Is covered
Covered gate electrode 25₁, 25₂And wiring 25 ₃Forming
To do.

Fourth Step (see FIG. 5D) The silicon nitride film 2 is covered with the n-type region 22 ₂ covered.
The source region 2 is formed by ion-implanting n-type impurities into the p-type region 22 ₁ using the gate electrode 25 ₁ covered with 6 ₁ as a mask.
2 ₁₁ and drain region 22 ₁₂ are formed. On the contrary, p
The silicon nitride film 26 is covered with the mold region 22 _1.
Using the gate electrode 25 ₂ covered with ₂ as a mask, p-type impurities are ion-implanted into the n-type region 22 ₂ to form the drain region 2
2 ₂₂ and a source region 22 ₂₁ are formed. Then, the silicon nitride film 26 ₁ covering the gate electrode 25 _1, the silicon nitride film 26 ₂ covering the gate electrode 25, the wiring 2
A part of the silicon nitride film 26 ₃ covering 5 ₃ is selectively removed by etching by a photolithography process to form openings 26 ₁₁ , 26 ₂₁ , 26 ₃₁ .

Fifth step (see FIG. 5E) A 100 nm-thickness silicon oxide film is formed on the entire surface by the CVD method.
Film deposition and reaction of this silicon oxide film with anisotropy
Etching by reactive ion etching (RIE),
Gate electrode 25₁, 25₂And wiring 25₃Left only on the side of
And then the sidewall 27₁₁, 27₁₂, 27_{twenty two}, 2
7_{twenty one}, 27₃₁, 27₃₂To form. Then exposed to the surface
The source region 22 made of single crystal₁₁,drain
Area 22₁₂, Drain region 22_{twenty two}, Source region 22_{twenty one},
And the gate electrode 25 made of the polycrystalline silicon film 25
₁, 25₂, Wiring 25₃A refractory metal, such as
Gold is produced by selectively reacting baltic, titanium, and tungsten.
Metal silicide layer 28 ₁₁, 28₁₂, 28₁₃, 28_{twenty one}, 28
_{twenty two}, 28_{twenty three}, 28₃To form.

Sixth step (see FIG. 5F) A tungsten film having a film thickness of 80 nm is deposited on the entire surface,
This tungsten film is used as a metal silicide layer 28 ₁₂ , 2
The local wiring 29 is formed by patterning so as to leave it on the region including 8 ₂₂ and 28 ₃ . Then, an interlayer insulating film 30 is deposited by a conventionally known process to form contact holes 30 ₁₁ , 30 ₁₂ , 30 ₂₂ , 30 ₂₁ and metal wirings 31 ₁₁ , 3 are formed through these contact holes.
1 ₁₂ , 31 ₂₂ , and 31 ₂₁ are formed.

(Third Embodiment) In the wiring method of the integrated circuit device described in the first embodiment, the third step (see FIG. 2C) to the fourth step (see FIG. 3D) are performed. ), The region where the polycrystalline silicon film 5 is exposed and the region where the silicon oxide film 6 is formed on the polycrystalline silicon film 5 are patterned by a photolithography process by one exposure and development. , Gate electrodes 5 ₁ , 5
₂ and wiring 5 ₃ are formed.

Usually, in the step of exposing such a fine pattern, in order to increase the patterning accuracy, in order to suppress the standing wave generated by the exposure light and the reflected light,
The material to be patterned is coated with an antireflection film, but the optimum conditions for this antireflection film vary depending on the amplitude of the reflected light from the underlying material to be patterned and the phase shift between the exposure light and the reflected light. To do.

In other words, when patterning regions having different underlying optical states, similar patterning accuracy cannot be expected over the entire region. In this embodiment, for example, in the first embodiment, the region where the polycrystalline silicon film 5 is exposed and the region where the silicon oxide film 6 is formed on the polycrystalline silicon film 5 are exposed once. Even if patterning is performed by development, it is an object to realize highly accurate patterning over the entire area.

FIGS. 6 and 7 are explanatory views of the manufacturing process of the CMOS static type memory cell of the third embodiment.
(E) has shown each process.

In this figure, 41 is a p ⁺ type silicon substrate, 42 is a p type silicon layer, 42 ₁ is a p type region, 42 ₂
Is an n-type region, 42 ₁₁ and 42 ₂₁ are source regions, 42 ₁₂ and 4
2 ₂₂ is a drain region, 43 is a field oxide film, 4
4 ₁ and 44 ₂ are gate oxide films, 45 is a polycrystalline silicon film, 45 ₁ and 45 ₂ are gate electrodes, 45 ₃ is wiring, 46
Is a silicon oxide film, 46 ₁ , 46 ₂ and 46 ₃ are openings, 4
7 is an amorphous carbon film, 48 is a photoresist film, 49 ₁₁ ,
49 ₁₂ , 49 ₂₁ , 49 ₂₂ , 49 ₃₁ , 49 ₃₂ are sidewalls, 50 ₁₁ , 50 ₁₂ , 50 ₁₃ , 50 ₂₁ , 50 ₂₂ , 50 ₂₂ .
₂₃ and 50 ₃ are metal silicide layers, 51 is local wiring, and 52
Is an interlayer insulating film, 52 ₁₁ , 52 ₁₂ , 52 ₂₁ , and 52 ₂₂ are contact holes, and 53 ₁₁ , 53 ₁₂ , 53 ₂₁ , and 53 ₂₂ are metal wirings. The CM of the third embodiment according to the process explanatory diagram
A method of manufacturing the OS static memory cell will be described.

First step (see FIG. 6A) A p-type silicon layer 42 is deposited on a p ⁺ -type silicon substrate 41 by epitaxial growth, and n-type impurities are introduced to form an active layer of an n-channel MOSFET. Mold area 42
₁ is formed and p-type impurities are introduced to p-channel MOSF
An n-type region 42 ₂ to be the active layer of ET is formed. Then, a field oxide film 43 is formed around the MOSFET formation regions of the p-type region 42 ₁ and the n-type region 42 ₂ by the LOCOS method.

Second step (see FIG. 6B) The surfaces of the p-type region 42 ₁ and the n-type region 42 ₂ are thermally oxidized to form gate oxide films 44 ₁ and 44 ₂ having a film thickness of 7 nm. A 180 nm-thick polycrystalline silicon film 45 is formed on the entire upper surface by a chemical vapor deposition (CVD) method,
A silicon oxide film 46 is grown on the entire surface by the CVD method.

This silicon oxide film 46 is exposed to the resist film 48, which is performed in a step of forming the gate electrodes 45 ₁ and 45 ₂ and the wiring 45 ₃ by selectively etching the polycrystalline silicon film 45 in the fourth step later. It is substantially transparent to the wavelength of light, and its film thickness is an integral multiple of half the wavelength of the exposure light in the silicon oxide film 46.

That is, when a KrF excimer laser having a wavelength of 248 nm in vacuum is used as the exposure light, the silicon oxide film 46 has substantially no absorption and is transparent. And, in general, the wavelength of light transmitted through a medium is a value obtained by dividing the wavelength in vacuum by the refractive index of the medium,
If the refractive index of the silicon oxide film 46 is 1.48, the wavelength in the silicon oxide film 46 is 248 nm / 1.
48≈168 nm. Therefore, the thickness of the silicon oxide film 46 is set to 84 nm which is the half wavelength of the KrF excimer laser light in the silicon oxide film 46.

Then, in a fourth step after that, a polycrystalline silicon film is formed.
Gate electrode 45 formed by 45₁, 45₂And
And wiring 45₃Photo of a part of the silicon oxide film 46 on the
Selective etching removal by lithography process
Opening 46₁, 46₂, 46 ₃To form.

Third step (see FIG. 6C) An amorphous carbon film 47 having a film thickness of 45 nm is formed thereon as a reflection preventing film by the CVD method. The amorphous carbon film 47 can control the refractive index and absorption coefficient of light to some extent under the film forming conditions of the CVD method. In this embodiment, the refractive index is 1.58 and the absorption coefficient is Was 0.75.

A photoresist film 48 is formed on the amorphous carbon film 47, and the photoresist film 48 is patterned on the polycrystalline silicon film 45 to form the gate electrode 4.
In order to form 5 ₁ , 45 ₂ and the wiring 45 ₃ , a KrF excimer laser having a wavelength of 248 nm is used for selective exposure, development, and patterning.

Fourth step (see FIG. 7D) The patterning of the silicon oxide film 46 and the polycrystalline silicon film 45 having the openings 46 ₁ , 46 ₂ and 46 ₃ formed in the second step formed in the third step The gate electrode 45 is patterned by using the photoresist film 48 thus formed.
₁ , 45 ₂ and wiring 45 ₃ are formed. After the gate electrodes 45 ₁ and 45 ₂ and the wiring 45 ₃ are formed, the photoresist film 48 and the amorphous carbon film 47 are removed by plasma etching.

Then, with the n-type region 42 ₂ covered, a gate electrode 45 ₁ is used as a mask to ion-implant an n-type impurity into the p-type region 42 ₁ to form a source region 42 ₁₁ and a drain region 42 ₁₂ . Form. On the contrary, the p-type region 42 ₁
With the gate electrode 45 ₂ masked, p-type impurities are ion-implanted into the n-type region 42 ₂ to form a drain region 42 ₂₂ and a source region 42 ₂₁ with the gate electrode 45 ₂ covered.

Fifth step (see FIG. 7E) A 100 nm-thickness silicon oxide film is formed on the entire surface by the CVD method.
A film is deposited, and this silicon oxide film is subjected to RI having anisotropy.
Etching with E, gate electrode 45₁, 45₂When
Wiring 45₃Selectively leave only the sides of the
Le 49₁₁, 49 ₁₂, 49_{twenty two}, 49_{twenty one}, 49₃₁, 49₃₂To
Form. Next, the single crystal exposed on the surface
Source region 42₁₁, Drain region 42₁₂, Drain region
Area 42_{twenty two}, Source region 42_{twenty one}, And polycrystalline silicon
Gate electrode 45 composed of film 45₁, 45₂, Wiring 45₃
A refractory metal such as cobalt is selectively reacted with the upper surface of the
Let the metal silicide layer 50₁₁, 50₁₂, 50₁₃, 5
0_{twenty two}, 50_{twenty one}, 50_{twenty three}, 50₃To form.

Sixth step (see FIG. 7F) A tungsten film having a film thickness of 80 nm is deposited on the entire surface,
This tungsten film is used as a metal silicide layer 50 ₁₂ , 5
The local wiring 51 is formed by patterning so as to leave it on the region including 0 ₂₂ and 50 ₃ . Then
An interlayer insulating film 52 is deposited and contact holes 52 ₁₁ and 5 are formed.
2 _12, 52 _22, 52 ₂₁ is formed, the metal wiring 53 ₁₁ through these contact holes 53 _12, 53 _22, 53 ₂₁
To form.

As in this embodiment, the gate electrodes 45 ₁ ,
The thickness of the silicon oxide film 46 formed on the polycrystalline silicon film 45 for forming the wiring 45 ₂ and the wiring 45 ₃ is
Assuming that the exposure light has a half wavelength in the silicon oxide film 46, it travels through the silicon oxide film 46 and is reflected by the interface with the lower polycrystalline silicon film 45 to be reflected by the silicon oxide film 4.
The optical state of the reflected light returning to the photoresist film 48 on 6 is exactly the same as the optical state of the reflected light on the region where the polycrystalline silicon film 45 is exposed without being covered with the silicon oxide film 46. .

Therefore, the optimum condition of the antireflection film by the amorphous carbon film 47 can be realized over the entire exposure range, the standing wave can be reduced, or the waveform of the standing wave can be designed. Even if the thickness of the silicon oxide film 46 formed on the polycrystalline silicon film 45 is set to an integral multiple of the half wavelength of the exposure light in the silicon oxide film 46, the same effect as described above can be obtained. It is clear in principle.

In the fifth step of the first embodiment, a 100 nm-thickness silicon oxide film is deposited on the entire surface by the CVD method, and this silicon oxide film is subjected to anisotropic reactive ion etching (RIE). By etching and selectively leaving only on the side surfaces of the gate electrodes 5 ₁ , 5 ₂ and the wiring 5 ₃ , the side walls 7 ₁₁ , 7 ₁₂ , 7 ₂₂ , 7 ₂₁ ,
After forming 7 ₃₁ and 7 ₃₂ (see FIG. 3E), an insulating film is deposited on the entire surface, the insulating film is deposited, and the source regions 2 ₁₁ and 2 ₂₁ and the drain region 2 ₁₂ are deposited on the insulating film. , 2 ₂₂ , wiring 5
_A local wiring shape groove reaching ₃ is formed by a photolithography process, a local wiring material such as tungsten is deposited on the entire surface including the local wiring shape groove, and the surface is polished by a chemical mechanical polishing method (CMP method). Then, the local wiring material can be left only in the groove having the local wiring shape to form the local wiring.

This method is used for damascene.
Although it is called inlaying method), in the second embodiment as well,
A local wiring can be formed by applying a step similar to this step after the fifth step (see FIG. 5E).

[0066]

As described above, according to the present invention,
Since wiring can be performed by local wiring without using a contact hole, high integration can be achieved without increasing a required area of the integrated circuit device, and an insulating film can be formed over the gate electrode or the wiring. Therefore, it is possible to arbitrarily intersect and connect with other wiring in a state of being insulated by the insulating film, and in particular, it is possible to reduce the area of the SRAM cell and achieve high integration. It greatly contributes to performance improvement.

When the film thickness of the silicon oxide film formed on the polycrystalline silicon film forming the gate electrode is set to a half wavelength of the exposure light in the silicon oxide film or an integral multiple thereof, the silicon oxide film is formed. Even when patterning a region covered with a film and a region not covered with a silicon oxide film by the photolithography process at the same time, the reflection state of the exposure light generated in both regions is the same, and the standing wave is applied to one of the regions. If the anti-reflection film or the like is set under the condition that minimizes the above condition, the other condition is also optimized for the other one at the same time, and there is no difference in patterning accuracy between the two regions.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of a wiring method for an integrated circuit device of the present invention, in which (A) and (B) show respective steps.

FIG. 2 is an explanatory view (1) of the manufacturing process of the CMOS static memory cell of the first embodiment, in which (A) to (C) show each process.

FIG. 3 is a manufacturing process explanatory diagram (2) of the CMOS static memory cell of the first embodiment, and (D) to (F) show each process.

FIG. 4 is an explanatory view (1) of the manufacturing process of the CMOS static memory cell of the second embodiment, in which (A) to (C) show each process.

FIG. 5 is a manufacturing process explanatory diagram (2) of the CMOS static memory cell of the second embodiment, and (D) to (F) show each process.

FIG. 6 is a manufacturing process explanatory diagram (1) of the CMOS static memory cell of the third embodiment, in which (A) to (C) show each process.

FIG. 7 is a manufacturing process explanatory diagram (2) of the CMOS static memory cell of the third embodiment, in which (D) to (F) show each process.

FIG. 8 is an explanatory diagram of a wiring method of a conventional integrated circuit device, in which (A) shows a cross section and (B) shows the circuit.

[Explanation of symbols]

1 p ⁺ type silicon substrate 2 p type silicon layer 2 ₁ p type region 2 ₂ n type region 2 ₁₁ , 2 ₂₁ source region 2 ₁₂ , 2 ₂₂ drain region 3 field oxide film 4 ₁ , 4 ₂ gate oxide film 5 polycrystal Silicon film 5 ₁ , 5 ₂ Gate electrode 5 ₃ Wiring 6 Silicon oxide film 6 ₁ , 6 ₂ , 6 ₃ Openings 7 ₁₁ , 7 ₁₂ , 7 ₂₁ , 7 ₂₂ , 7 ₃₁ , 7 ₃₂ Sidewalls 8 ₁₁ , 8 ₁₂ 8 ₁₃ , 8, ₂₁ , 8 ₂₂ , 8 ₂₃ , 8 ₃ Metal silicide layer 9 Local wiring 10 Interlayer insulating film 10 ₁₁ , 10 ₁₂ , 10 ₂₁ , 10 ₂₂ Contact hole 11 ₁₁ , 11 ₁₂ , 11 ₂₁ , 11 ₂₂ Metal wiring 21 p ⁺ type silicon substrate 22 p type silicon layer 22 ₁ p type region 22 ₂ n type region 22 ₁₁ , 22 ₂₁ source region 22 ₁₂ , 22 ₂₂ drain region 23 field oxide film 24 ₁ and 24 ₂ gate oxide film 25 polycrystal Silicon film 25 ₁ , 25 ₂ gate electrode 25 ₃ wiring 26, 26 ₁ , 26 ₂ , 26 ₃ silicon nitride film 26 ₁₁ , 26 ₂₁ , 26 ₃₁ opening 27 ₁₁ , 27 ₁₂ , 27 ₂₁ , 27 ₂₂ , 27 ₃₁ , 27 ₃₂ side wall 28 ₁₁ , 28 ₁₂ , 28 ₁₃ , 28 ₂₁ , 28 ₂₂ , 28 ₂₃ , 2
8 ₃ Metal Silicide Layer 29 Local Wiring 30 Interlayer Insulating Film 30 ₁₁ , 30 ₁₂ , 30 ₂₁ , 30 ₂₂ Contact Holes 31 ₁₁ , 31 ₁₂ , 31 ₂₁ , 31 ₂₂ Metal Wiring 41 p ⁺ Type Silicon Substrate 42 p Type Silicon Layer 42 ₁ p-type region 42 ₂ n-type region 42 ₁₁ , 42 ₂₁ source region 42 ₁₂ , 42 ₂₂ drain region 43 field oxide film 44 ₁ , 44 ₂ gate oxide film 45 polycrystalline silicon film 45 ₁ , 45 ₂ gate electrode 45 ₃ wiring 46 Silicon oxide film 46 ₁ , 46 ₂ , 46 ₃ Opening 47 Amorphous carbon film 48 Photoresist film 49 ₁₁ , 49 ₁₂ , 49 ₂₁ , 49 ₂₂ , 49 ₃₁ , 49 ₃₂ Sidewalls 50 ₁₁ , 50 ₁₂ , 50 ₁₃ , 50 ₂₁ , 50 ₂₂ , 50 ₂₃ , 5
0 ₃ metal silicide layer 51 local wiring 52 interlayer insulating film 52 ₁₁ , 52 ₁₂ , 52 ₂₁ , 52 ₂₂ contact hole 53 ₁₁ , 53 ₁₂ , 53 ₂₁ , 53 ₂₂ metal wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 29/78 21/336 H01L 29/78 301 P

Claims (4)

[Claims] 1. A step of forming a wiring material film on a substrate, and a step of forming an insulating material film on the wiring material film,
Wiring is formed by selectively removing a part of the insulating material film for which wiring is to be formed by the wiring material film, and patterning a two-layer film composed of the insulating material film and the wiring material film. A wiring method for an integrated circuit device, comprising: a step, a step of forming an insulating film on a side surface of the wiring, and a step of forming a local wiring for connecting a surface of the substrate and a surface of the wiring. 2. An insulating material film formed on a wiring material film is made of a material which is substantially transparent to a wavelength of exposure light used when patterning the wiring material film and the insulating material film by a photolithography process. , And its thickness,
The wiring method for an integrated circuit device according to claim 1, wherein the exposure light is an integral multiple of a half wavelength in the insulating material film. 3. A step of depositing a wiring material film on a substrate, a step of forming an insulating material film on the wiring material film,
A step of forming a wiring by patterning a two-layer film composed of the insulating material film and the wiring material film; a step of removing a part of the insulating material film above the wiring; and an insulating film on a side surface of the wiring. And a step of forming a local wiring that connects the surface of the substrate and the surface of the wiring, the wiring method of the integrated circuit device. 4. The wiring method for an integrated circuit device according to claim 1, wherein the surface of the substrate is a source region or a drain region.