JPH0728702A - Program converting method - Google Patents

Abstract

PURPOSE:To convert a program in order to decrease the cache misses that are caused by the conflict of cache lines of a cache memory of a set associative system. CONSTITUTION:A part of a program that is repetitively carried out is specified in a step 101, and an array accessed in a loop is checked together with the access position in the array in a step 102. In a step 103, the array access position (subscript expression) changes at the same rate in the loop and the arrays are stored so that the arrays of the same reference and array types are put together. The arrays collected in the same group are changed into a single array in a step 104. In a step 105, the reference to the element of an unstructured array is changed to the reference to the element of a structured array.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for converting a program or compiling a program, and more particularly to a technique for converting a program so as to reduce cache misses in a cache memory of a computer that executes the program.

[0002]

2. Description of the Related Art In many current computer systems, a small-capacity storage device having a high access speed called a cache memory is mainly used in order to fill a speed gap between a CPU operating at high speed and a main memory having a low access speed. It is often provided as an intermediate buffer between the memory (main memory) and the CPU. Since such a cache memory can be accessed by the CPU at high speed, the process of referring to the data in the cache memory that is referred to in the process in the program can be performed very quickly.

Generally, when a program refers to data, it often has the following properties.

1. Access to data at a certain address will occur again within a relatively short time.

2. Data accessed within a certain period of time is distributed to relatively close addresses.

The former is called "temporal locality" and the latter is called "spatial locality". A computer system including a cache memory is designed as follows to utilize these properties.

First, due to temporal locality, an address that has been accessed once is likely to be accessed again in the near future. Therefore, in a normal cache memory, if the data referred to by the CPU is not in the cache memory, it is always fetched in the cache memory to prepare for future re-reference. Since the CPU fetches the data to the cache memory automatically, the program does not need to explicitly issue such an instruction.

Further, due to the spatial locality, when an address is accessed, there is a high possibility that addresses near the address will be accessed in the near future. Therefore, when fetching certain data from the main memory to the cache memory, not only that data but also the memory blocks obtained by dividing the memory storage space into units of a fixed length (about 10 bytes to 100 bytes) are fetched into the cache memory. I am trying to do it.

As described above, since the cache memory is designed by utilizing the general characteristics of the program, even if each program is written without paying attention to the existence of the cache memory, the cache memory device can be effectively used as a result. Often available.

A description of general cache memory technology is given in Information Processing, Volume 33, Number 11 (1992), pages 1348 to 1357.

Now, address mapping of the cache memory will be briefly described.

A memory block is placed in each entry of the cache memory, but there are some methods regarding which memory block is placed in which entry.

The association between the memory block and the cache memory entry is called address mapping. This method is roughly divided into three types.

The method called direct mapping is a method for uniquely determining an entry to be entered by the address of the memory block. Specifically, the remainder obtained by dividing the address by the size of the cache memory is used as the entry number in which the memory block should be inserted. Since the size of the cache memory is usually a power of 2, if it is 2 ^ N, the lower N addresses
The bit determines the entry to enter. In the case of this method, if the lower N bits of the addresses of the two data happen to coincide, the entries to be entered are the same, so the two data cannot exist in the cache memory at the same time. This is called cache memory line competition.

The method called set associative is similar to the direct map in that the lower N addresses of memory are
The entry to be entered is determined by the bit, but there are multiple entry candidates that should be entered. The number of candidates is called the number of sets.
For example, if the number of sets is two, even if the lower N bits of the addresses of the two data match, they can simultaneously exist (up to two) in the cache memory. Usually, the number of sets is usually 2 or 4. Even in this method, competition of cache memory lines still occurs.

The method called perfect associative is
This is a method in which a memory block can be put in any vacant entry. In this method, competition of cache memory lines does not occur, but it is rarely used in practice because it is expensive and slow in terms of hardware.

[0017]

However, when a certain data is fetched from the main memory to the cache memory, there is a program in which the cache memory cannot be effectively used only by fetching the entire memory block into the cache memory. Specifically, this corresponds to a case where a plurality of data accessed in a repeatedly executed part (loop) of a program compete for a cache memory line.

As an example, consider the program shown in FIG. It is assumed here that the cache memory is an associative cache memory with a set number of 2, the cache memory 1 entry is 32 bytes (8 words), and the number of entries is 128 (therefore, the size is 2 * 32).
* 128 = 8192 bytes). The cache memory replacement method is LRU (a method of expelling from the cache memory the entry with the oldest access time).

The program shown in FIG. 4 is an example of a program written in a programming language known as C. In this example, first,
Definition statement of four array types a, b, c, d
t (integer type) and the number of elements 2048 are defined.

After the type int (integer type) of i, j is defined at 407 in the processing main 405, a loop for i is declared at 408 and a loop for j is declared at 409. And loops 409-411 for i
The four array elements a [j], b [j], c [j], d [j] are referred to in the loops 410 and 411 for j in j, and the value of a [j] is assigned to b [j]. 410, c
The value of [j] is substituted into d [j] 411.

Here, these four elements compete for a cache memory line. Because the sizes of all four arrays are 8192 (= 2048 * 4) bytes, which is the same as the size of the cache memory, a [j],
This is because the remainders obtained by dividing the addresses of b [j], d [j], and c [j] by 8192 will always be the same.

It is assumed that a cache miss has occurred at the time when the array element a [J] is referenced (J is a certain value of j). Then, a block (a [J ..
J + 7]) is fetched into the cache memory. Next, when a cache miss occurs at the time when the array element b [J] is referred to, a block (b [J..J
+7]) is fetched into the cache memory. At this time, these two blocks compete for the cache memory line, but since the number of sets of the cache memory is 2, a [J. ． J + 7] and b [J. ． J + 7] can simultaneously exist in the cache memory.

However, in this case, the array element c [J]
A cache miss occurs when you refer to. Then, the block (c [J..J + 7]) including c [J] is fetched into the cache memory, and a [J. ． J + 7]
Are flushed from cache memory. Therefore, at this point, b [J. ． J + 7] and c [J. ． J + 7] are simultaneously present in the cache memory. Also,
Next, referring to the array element d [J], a cache miss still occurs, and the block d [J. ． J
+7] is fetched into the cache memory, and b [J. ．
J + 7] is expelled from the cache memory. Therefore, at this point, c [J. ． J + 7] and d [J. ． J
+7] exists in the cache memory at the same time.

Now, the next round of loop iteration is as follows. First, the array element a [J + 1] is referenced. Then, a cache miss occurs. This is because c [J. ． J + 7] and d [J. ． J + 7] is stored and a [J. ． J +
7] has been kicked out. In this way, array element references b [J + 1], c [J + 1], d [J +
1] ,. ． ． , D [J + 7], a cache miss will occur. Similarly, a [J +
8] Since the same situation applies to access after that,
Eventually a cache miss will occur for all array element references.

As described above, it has been shown that all the array references in the program loop of FIG. 4 cause a cache miss. In order to effectively use the cache memory for such programs, it is effective to increase the capacity of the cache memory or increase the number of sets.

That is, by increasing the cache memory capacity, it is possible to indirectly reduce the chance of competition for the cache memory lines. In the case of the example of FIG. 4, if the capacity of the cache memory is doubled, the contention of the cache memory lines is reduced from 4 to 2 as a derivative effect, and the spatial locality can be utilized. However, there is a major drawback in that the increase in cache memory capacity causes an increase in cost.

On the other hand, the increase in the number of sets directly reduces the possibility of cache memory line competition. Two
When the number of sets is 4, a [J], b [J], c
Even if four references [J] and d [J] occur at the same time, a line including a [J], b [J], c [J], and d [J] can exist in the cache memory at the same time. However,
Increasing the number of sets has the drawback of increasing the cache memory access time. And this causes the operating frequency of the processor to be lowered.

As described above, various problems occur in the measures from the viewpoint of hardware such as an increase in the cache memory capacity and an increase in the number of sets.

Therefore, according to the present invention, a portion (loop) of a program that is repeatedly executed without changing hardware.
It is an object of the present invention to provide a program conversion method capable of improving the hit rate of a cache memory even for a plurality of data accessed by.

[0030]

The above objects are achieved by transforming a program to avoid cache memory line conflicts, rather than making changes to the cache memory device itself. That is, for a program in which array elements referenced in a loop may conflict with cache memory lines, the placement of those arrays in memory is changed to an arrangement that does not conflict with cache memory lines. Change the program as follows.

Therefore, for this purpose, the present invention is a method for converting a program, which comprises a step of determining a portion describing a looping process of the program, and a portion describing a determined looping process. Among the plurality of arrays described to be referred to, the types of the arrays are the same, and are referenced in each processing of the loop processing,
A step of grouping arrays that have the same position in the array of elements of the array into the same group, and a description that defines a plurality of arrays grouped into the same group, and a description that defines one array composed of the plurality of arrays. And a description that refers to elements of a plurality of arrays that are grouped in the same category in the loop processing part is changed to a description that refers to corresponding elements of one array configured by the plurality of arrays. And a converting step, which provides a program converting method.

[0032]

According to the program conversion method of the present invention,
Determine the part of the program that describes the looping process, and in the part that describes the determined looping process,
Among a plurality of arrays described to be referenced, the arrays have the same type, and the elements of the arrays referred to in each processing of the loop processing have the same position in the array. The description defining a plurality of arrays grouped into the same group and converted into a description defining one array composed of the plurality of arrays is performed, and the same grouping in the loop processing part is performed. The description referring to the elements of the plurality of arrays summarized in (1) is converted into the description referring to the corresponding element of one array configured by the plurality of arrays. Then, with respect to the program whose description is converted in this way, there is no competition of cache lines between a plurality of arrays forming the one array. Further, it is more efficient if the respective array elements having the same position in the array of the plurality of arrays forming the one array are sequentially arranged at the continuous position in the main memory in the computer executing the program at the time of executing the program. The cache memory can be used.

[0033]

EXAMPLES An example of the present invention will be described below.

FIG. 2 shows the configuration of the computer system according to this embodiment.

As shown, the computer system is a CPU
It comprises 201, a main storage device 202, an external storage device 203, a display device 204, and a keyboard 205.

A source program 206 and an object program 207 are stored in the external storage device 203. In the main storage device 202, a compiler program 211 describing a compiling process, an intermediate language 208 required in the compiling process, a symbol table 209, and
The in-loop array reference table table 210 is stored. The compiling process is a process for generating an object program 207 described by an assembly language or a machine language that can be directly interpreted by a computer from a source program 206 written by a user in a high-level language such as C. It is realized by the CPU 201 executing the compiler program.

The keyboard 205 receives a compiler activation instruction from the user. Display device 2
04 displays a compilation end message and an error message.

The details of the compiling process according to this embodiment will be described below.

FIG. 3 is a flow chart showing the processing of the compiler. Compile is lexical analysis 301, syntactic analysis 3
02, structuring 303, optimization 304, code generation 30
Proceed in the order of 5.

Of these, the vocabulary analysis, the syntax analysis, the optimization, and the code generation are the same as the processing in the conventional compiler, and therefore will be briefly described.

In the lexical analysis 301, the source program stored simply as a character string is stored in the external storage device 203.
It is read out more sequentially and made into a row of words (lexicon). For example, when the source program described in the programming language C shown in FIG. 4 described above is lexically analyzed, a string of words as shown in FIG. 5 is obtained.

Here, as shown in the figure, each word is of type 5
It is expressed by a set of 01 and the token 502. The words are arranged in the order of appearance of the source program. Type of keyw
ord is a keyword of the program, id is an identifier, pu
nc represents a delimiter and num represents a number.

Next, the syntactic analysis 302 analyzes the string of words. The syntax analysis performs different processing depending on whether the analyzed statement is a declarative statement or an executable statement. For the declaration statement, the declared identifier is registered in the symbol table 209, and for the execution statement, the intermediate word 208 is stored in the main storage device 202.
Create on top.

An example of the symbol table 209 is shown in FIG. Note that the example shown in FIG. 6 corresponds to the example shown in FIG.
It corresponds to the source program of.

As shown, the symbol table 209
The information registered in is the name 601, the appearance position 602,
A mold 603, a structured flag 604, and the like. Name 601
Indicates the name of the identifier, and the appearance position 602 indicates the position where the identifier is declared (whether inside the function or outside the function). The type 603 represents the type of the identifier, and for example, “array (int, 204
8) ”is“ the element type is int (integer type) and the number of elements is 204
8 array ". Structured flag 604
Is a flag set in the structuring process 303 described later, and is initially off.

Next, an example of the intermediate word 208 is shown in FIG. This example also corresponds to the program of FIG.

As shown in the figure, the intermediate word 208 is represented by a tree structure. A tree is a set of nodes and edges. In FIG. 7, nodes are parts surrounded by squares, and edges are lines connecting them. Each node has one parent node and zero or more child nodes (however, only a special node called the root has no parent node). In the figure, the edge extending upward from each node is a parent node, and the edge extending downward is a child node. The children are called the first child, the second child, ... From the left. For example, the parent node of “{}” (703) is “fuc
n ”(701), and the child node is“ for ”(70
4). The root node is "func" (701). Trees are suitable for representing the logical structure of programs and are often used in compilers.

The symbol table 209 and the intermediate language 208 thus created can be said to be a program equivalent to the source program.

Next, in the optimization 303, the part of the executable statement represented by the tree structure is operated. Then, optimization processing such as finding a redundant portion and deleting the redundant portion is performed.

In the final code generation 305, an object program expressed in assembly language is generated.
There is also one that generates an object module expressed in machine language.

That is, in the code generation 305, an assembly language area definition instruction and a constant definition instruction are generated from the symbol table 209, and an assembly language machine language instruction is generated from the intermediate language 208.

Next, the processing procedure of the structuring 303 will be described.

FIG. 1 is a flow chart showing in detail the processing procedure of the structuring 303.

As shown in the figure, the processing of structuring 303 is performed by recognizing a loop structure 101, analyzing an array reference in a loop 102, classifying an array group 103, and structuring an array element 10
4. Change of array element reference to structured member reference 105
In order.

These processes will be specifically described below.

In structuring 303, first, step 101
Then, the loop structure is recognized 101 from the intermediate word 208. In this process, the intermediate word 208 is scanned, a node representing a loop is found, and a statement repeatedly executed in the loop (hereinafter, simply referred to as “loop execution statement”) is recognized. The loop recognition process starts scanning from the root of the tree. For example, in the intermediate language of FIG. 7, the root func 701 represents a function definition, the first child of which represents the function name main and the second child represents the function body. The second child is {} 703. Moving to the first child of {}, for704 (a kind of loop node)
Is found (first for sentence). The fourth child represents the statement executed by the for node (the first child is the initial value setting statement, the second child is the repeat determination statement, and the third child is the control variable update statement). Move on to. The fourth child for708 is again a for node (second for sentence). So when I moved to the fourth child, it was {} 709,
Furthermore, it can be seen that the child of {} 709 has two assignment statements (indicated by =). Therefore, it is understood that the loop execution statement of the second for statement is two assignment statements. This is the end of recognition of the loop structure.

Next, at step 102, the array element reference analysis in the loop is performed. In this processing, the intermediate word 208 of the loop execution statement recognized in step 101 is scanned to find the array element reference node, and the array name, subscript expression, reference status (use /
The definition) is checked and registered in the array element reference table 210 of the main memory 202. Here, the subscript expression is an expression represented by the function F of the array a [F (x)].

For example, in the intermediate language shown in FIG. 7, the first child of the array element reference node (indicated by []) is the array name,
The second child represents a subscript expression. Further, it is assumed that the first child of the assignment node (denoted by =) represents the assignment destination (definition side) and the second child represents the assignment source (use side). The loop execution statement in the intermediate language of FIG. 7 is two assignment statements.

In the first assignment statement (710), the array element designated by the array name a and the subscript expression j (corresponding to a [j] in the expression on the source program) is designated by the array name b and the subscript expression j. Array element (b [j] in the source program representation)
Corresponding to) is the form to substitute. Hereinafter, for the sake of clarity, the expression on the source program will be used for the array elements for the sake of clarity. The following assignment statement (711) has a form of assigning the array element c [j] to the array element d [j]. Therefore, in step 102, the array element reference table 210 shown in FIG. 8 is created from the intermediate language shown in FIG.
When the array element is defined and used, the reference status of the array element reference table 210 is “definition”.

Next, in step 103, the array groups are classified.

This process determines whether each array element reference belongs to the same class. Here, the array element reference refers to a description indicating a reference to an element of an array, which corresponds to a description such as a [j] or c [j] on the source program, and an array element reference on the intermediate language. The description of the node (indicated by []) and its children correspond.

A flowchart of this processing is shown in FIG.

In this processing, first, at step 901, it is checked whether both the subscript expressions of the given array element references are linear expressions of the loop control variable. Here, the linear expression has a form of “constant 1 * loop control variable + constant 2” (however, constant 1 and constant 2 may be 0). If at least one of them is not a linear expression of the loop control variable, it is judged that they do not belong to the same class (906).
Processing ends.

If both are linear expressions, then step 9
In 02, it is checked whether the coefficient of the subscript expression and the constant term are equal (whether constant 1 and constant 2 are equal). If they are not equal, it is determined that they do not belong to the same class (906), and the process is terminated.

If they are equal, then in step 903, it is checked whether the two arrays have the same type. Equal type here means that the type of array element and the number of elements of the array are equal. If they are not equal, it is determined that they do not belong to the same class (906), and the process is terminated.

If the types are the same, then in step 904,
Check if the reference statuses are equal. Here, the reference situations being equal means that the two references are both definitions or both are uses. If they are equal, it is determined that they belong to the same class (905), and the process ends.
If they are not equal, it is determined that they do not belong to the same class (906)
The process ends.

By the above processing, for example, in the source program shown in FIG. 4, the references a [j] and c [j] are in the same class, and the references b [j] and d [j] are in the same class. It is determined to be included (j is a loop control variable).

Now, returning to FIG.
Then, the array elements are structured.

In this processing, a plurality of arrays referred to by the array reference belonging to one class are put together into one array. The element type of the array is a structure type, which is calculated as follows. Sequences belonging to one class are A1, ..., A
Let n be the element type thereof, and t be the number of array elements (if they are of the same type, the element type and number of elements of the array are the same).
Then, the element types of the combined array are (in C language): It becomes the type. This is the i of the combined sequence.
The th element is the i of each of the n arrays A1, ..., An.
Indicates that the array is the th integer type element.
Note that the number of elements in the array that has been merged into one remains N.

The sequence names of the combined sequences are made unique (do not conflict with other names), but here, the original sequence names are simply combined (A1 ... An) for convenience. I will use it for.

Now, the array newly generated in this way is
Register in the symbol table 209. Then, the "structuring flag" indicating that the original array has been structured is turned on. The array symbol after further structuring is registered. Step 1 for the program in Figure 4
When the processing of 04 is performed, the symbol table becomes as shown in FIG. In FIG. 10, arrays a and c are structured into 1
One array ac (1001) is formed, and the arrays b and d are structured into one array bd (1002). The types of these arrays are both "array (struct
(Int, int), 2048) ”. The structuring flag is turned on for the arrays a, b, c and d. Further, in the field (605) indicating the symbol after being structured, the array ac is registered for the arrays a and c, and the array bd is registered for the arrays b and d.

Next, at step 105, the array element reference is changed to a structured member reference. This is a process of scanning the intermediate word again, and if there is a reference to an array element whose structuring flag is on, replaces it with the array element reference (structure member reference) after structuring. FIG. 11 is a diagram showing the change of the intermediate language in this processing. Letting A be the original array reference and B be the array after structuring, 1101 represents the tree before the change and 1102 represents the tree after the change. In Fig. 11, "."
Is a node that represents the member reference of the structure.

The modification of FIG. 11 is that A [e] is changed to B [e]. It means to change to A. In the program of FIG. 4, arrays a, b, c, and d are rewritten as shown in the symbol table of FIG. Therefore, when scanning the intermediate word of FIG. 7, array references a [j], b [j], c [j], d [j] are found to be changed and are changed as follows (actually,
Change at intermediate language level as shown in FIG. 11) a [j] → ac [j]. a b [j] → bd [j]. bc [j] → ac [j]. cd [j] → bd [j]. d where ac [j]. a represents the j-th element of the array a that is structured into the array ac among the elements of the array ac.

This is the end of the explanation of the structuring process.

FIG. 12 is a source program image showing a program at the time when the structuring process is completed. However, since the above processing is performed on the intermediate language 208 and the symbol table 209 equivalent to the source program, the source program is not actually changed.

Now, the intermediate language 208 and the symbol table 20 changed by the structuring 303 in this way are described.
As described above, 9 is the optimization 30 in which optimization processing such as deleting the redundant portion of the executable statement represented by the tree structure after the intermediate processing is performed. Then, in the code generation 305, an object program expressed in assembly language or machine language is generated from the intermediate language 208 and the symbol table 209 changed by the structuring 303. That is, as described above, the code generator 305 generates an assembly language area definition instruction and a constant definition instruction from the symbol table 209, and generates an assembly language machine language instruction from the intermediate language 208.

When generating the assembly language area definition instruction from the symbol table 209, the code generator 305 uses the structuring flag 6 of the symbol table 209.
No area definition instruction is generated for an array in which 04 is set to ON. That is, for example, the area is defined for the structured array ac, but the area is not defined for each of the original arrays a and c.

When the object program is executed, the structured array is stored in the area defined by the area definition command for the array ac on the main memory of the computer that executes the object program. a, ac
[0]. c, ac [1]. a, ac [1]. c, ..., a
c [2047]. a, ac [2047]. It is stored in the order of c.

Hereinafter, it will be described how many cache misses occur in the cache memory when the object program 207 thus generated is executed.

Now, assume a cache memory as shown in FIG.

The cache memory shown in FIG. 13 is an associative cache having two sets. The total cache capacity is 8 kbytes, that is, the capacity of one set is 4 kbytes. One set has 128 entries. The entry number is called an index, and two entries having the same index are collectively called a line. 1
In each line, one line consists of three parts: control bit (1201), tag (1202), and data (1203). 32 bytes (8 words) of memory data are stored in the data section. The tag is a field that specifies to which memory address the data stored in the data section corresponds. The control bit is the empty bit (12
04), recent bit (1205), dirty
It consists of bits (1206) and the like. The empty bit indicates whether this line is empty (when it is true, it is empty). rec
The ent bit indicates whether this entry is accessed later than the other entry (when true, after). di
The rty bit indicates whether or not there is a write in this entry (when true, there is a write).

When a memory access occurs, the line in the cache line is specified by using the 6th to 12th lowest 7-bit value of the memory address (1207) as an index (1209). Since the number of sets is 2, there are two entries in one line. Next, the value of the upper 20 bits of the relevant memory address is set to the tag (120
8), and the value of the tag (1202) stored in the entry is compared by the comparator (1210). If there is a matching entry, it is a cache hit. Otherwise, you will get a cache miss. In the case of a cache miss, the data is fetched from the memory and stored in the empty entry (the emtppy bit of the control bit is true) of the two entries. If neither entry is empty, the last accessed time is older (rec
ent bit is not true) Store in entry. However, before storing, it is checked whether or not the entry has been written (whether the dirty bit is true), and if there is the writing, the previous entry contents are written back to the main memory. If there is no writing, there is no need to write it back to the main memory.

When the previously created object program is executed in a computer having such a cache memory, each array data is arranged in the main memory as shown in FIG.

FIG. 14 is a diagram showing the arrangement of the structured arrays ac and bd in the main memory. As shown in the figure, the array ac is from 00000000 to 00002F
At the FC address, ac [0]. a, ac [0]. c, ac
[1]. a, ac [1]. c, ..., ac [2047].
a, ac [2047]. It is stored in the order of c. Array bd
From address 003000 to address 00004FFC,
bd [0]. b, bd [0]. d, bd [1]. b, b
d [1]. d, ..., bd [2047]. b, bd [20
47]. They are stored in the order of d.

When array element data is fetched into the cache memory, 8 elements (8 words) are fetched at once. For example, array element ac [0]. If a is accessed and it is not in the cache, ac
[0]. 8 word memory block including a (ac
[0]. a, ..., ac [3]. c) is fetched into the cache. In this case, for any I, a
The values of the lower 12 bits of the addresses of c [I] and bd [I] are equal. For example, the address of ac [1] is 0
The address of 00000004, bd [1] is 000030
In 04, the lower 12 bits are both 004. Bottom 1
Since the cache line is determined by 2 bits, they are stored in the same cache line. That is, ac
[I] and bd [I] compete for a cache line.

The behavior of the cache memory along with the object program execution of the source program shown in FIG. 4 is as follows.

First, the array element ac [0]. Reference is made to a. This is the first access and ac [0]. A memory block (ac [0] .a, ..., ac [3] .c) including a is fetched into the cache memory. Next, bc [0]. b
Is referred to. This is also the first reference, bd [0]. b
, Including memory block (bd [0] .b, ..., bd
[3]. d) is fetched into the cache memory. These two memory blocks compete for the cache line, but both sets remain in the cache memory because the number of sets is two. After that, ac [0]. c, bd [0]. d, ac
[1]. a, bd [1]. b, ac [1]. c, bd
[1]. d, ..., bd [3]. Although they are referred to in the order of d, they are cache hits because they have already been fetched into the cache memory. In summary, 16 references refer to two cache misses. The next sequence reference is ac [4]. a, but this part is the first ac
[0]. It becomes the same situation as the reference of a. Therefore, 16
A cache miss will occur twice for each reference.

For comparison, FIG. 15 shows the arrangement of the arrays a, b, c and d in the main memory when the arrays are not structured. In this case, the array a is 00000
Array b is 00 from address 000 to address 00001FFC
Array c from address 002000 to address 00002FFC
From 00003000 to 0000FFFC,
The array d is continuously stored from the address 0004000 to the address 0000440FFC. Also, for any I, a
The values of the lower 12 bits of the addresses of [I], b [I], c [I], and d [I] are all equal. That is, they compete for cache lines. Therefore, in this case, as described above, the cache miss occurs 16 times, that is, every time the reference is made 16 times.

Therefore, according to the present embodiment, with respect to the source program shown in step 4, the cache miss is 1/8.
This means that we were able to reduce it to (= 2/16).

According to the present embodiment, since the arrays having the same reference status are grouped into a single array, the array in which the reference status is "used" is changed in the cache memory. Not done. Therefore, there is no need to write back this array to main memory. That is, array a
Since c is not changed in the cache memory, array a
When the cache line including the part of c is evicted from the cache, the dirty is not set and the writing back to the main memory is unnecessary. This is advantageous for a computer that employs the store-in method as a method for writing back to the main memory, as described above. Because the data that needs to be written back to the main memory,
This is because the memory blocks can be localized and the number of write backs can be reduced. However, if the program is executed only on a computer that adopts the store-through method as the write-back method, such an effect cannot be expected. Therefore, in such a case, even arrays having different reference situations may be collectively structured into one array. That is, step 904 in FIG. 9 may be omitted. Of course, in a program executed on a computer that uses the store-in method as the write-back method, even if the arrays have different reference conditions, the cache misses described above are reduced even if they are structured into a single array. The effect of doing can be achieved. In this case, in the example shown in FIG. 4, the arrays a, b,
c and d are structured into one array abcd. In this case, cache line contention does not occur, and a fetch to the cache memory occurs once every eight references. This is also the case with the direct mapping method. Therefore, by doing so, cache misses can be reduced also in the direct mapping method.

In the above embodiments, the source program written in the programming language known as C is described as an example.
A programming language known as FORTRAN,
Other programming languages can be implemented similarly.

In the present embodiment, the structure of the array and the conversion of the array element reference are performed for the intermediate language and the symbol table at the time of compiling, but the source program is made to reflect the result. May be converted. For example, the source program shown in FIG. 4 may be converted into the source program shown in FIG. In this case, after that, the source program shown in FIG. 12 may be compiled in the same manner as the conventional one.

As described above, according to this embodiment, a program in which cache misses frequently occur due to cache line competition can be automatically converted into a program in which cache misses are less likely to occur. As a result, the execution performance of the program can be improved without changing the cache device. Further, according to the present embodiment, since such program conversion can be automatically performed by the computer,
This has the effect of reducing the effort and error compared to the programmer manually changing the program.

[0094]

As described above, according to the present invention, the hit rate of the cache memory can be set even for a plurality of data accessed in the repeatedly executed part (loop) of the program without changing the hardware. It is possible to provide a program conversion method that can be improved.

[Brief description of drawings]

FIG. 1 is a flow chart showing a processing procedure of a structuring processing according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a computer system according to an embodiment of the present invention.

FIG. 3 is a flowchart showing a processing procedure of a compile processing according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram showing an example of a source program.

FIG. 5 is an explanatory diagram showing an example of a vocabulary analysis result.

FIG. 6 is an explanatory diagram showing an example of a symbol table.

FIG. 7 is an explanatory diagram showing an example of an intermediate language.

FIG. 8 is an explanatory diagram showing the structure of a vocabulary element place table according to an embodiment of the present invention.

FIG. 9 is an explanatory diagram showing a symbol table after structuring processing according to an embodiment of the present invention.

FIG. 10 is an explanatory diagram showing how an intermediate language is changed by the structuring processing according to the embodiment of the present invention.

FIG. 11 is an explanatory diagram showing a program after conversion by a structuring process according to an embodiment of the present invention at a source program level.

FIG. 12 is an explanatory diagram showing a configuration example of a cache memory.

FIG. 13 is a flowchart showing a processing procedure of processing for making a type determination of array element reference according to an embodiment of the present invention.

FIG. 14 is an explanatory diagram showing an arrangement on a main memory of a structured array according to an embodiment of the present invention.

FIG. 15 is an explanatory diagram showing an arrangement on a main memory of an array according to a conventional technique.

[Explanation of symbols]

 101 ... Recognition of loop structure 102 ... Analysis of in-loop array reference 103 ... Classification of array group 104 ... Structuring of array element 105 ... Change of array element reference to structure member reference

Claims (7)

[Claims] 1. A method for converting a program, which comprises a step of determining a part describing a looping process of the program, and a reference in the part describing the determined looping process. A plurality of arranged arrays, the types of the arrays are the same, and the steps of grouping the arrays having the same position in the array elements of the arrays referred to in each processing of the loop processing into the same category, , A description defining multiple arrays grouped into the same category,
The step of converting into a description defining one array composed of the plurality of arrays, and the description referring to the elements of the plurality of arrays grouped in the same category in the loop processing part, by the plurality of arrays. And a step of converting a description that refers to a corresponding element of one configured array, to a program conversion method. 2. The program conversion method according to claim 1, wherein the step of grouping the plurality of arrays includes a plurality of arrays described to be referred to in a part describing the determined looping process. Among them, the types of the arrays are the same, and the positions of the elements of the arrays referred to in each processing of the loop processing are the same in the arrays, and further, the contents of the description that refers to the array However, both of the arrays that are descriptions that change the contents of the array are grouped in the same class,
A method of converting a program, characterized in that the contents of the description referring to the array are the steps of grouping the arrays which are descriptions that do not change the content of the array. 3. The program conversion method according to claim 1, wherein in the step of classifying, the position of an element referred to in each process of the loop process in the description that refers to the array. When the contents of the subscript expressions that specify are equal, the positions of the elements of the array referred to in the processing of each time in the array are the same array, and the program conversion method. 4. A method of compiling a program for generating an object code sequence to be executed on a computer having a main memory and a cache memory from a program, the portion describing a looping process of the program. Among the plurality of arrays that are described to be referred to in the part that describes the determining step and the determined looping processing, the array types are the same, and the processing of each time of the loop processing is performed. The steps of grouping arrays that have the same position in the array of the elements of the array referred to in, and the description that defines multiple arrays grouped in the same group of the program are configured by the multiple arrays. The step of converting into a description defining one array, and the description referring to the elements of a plurality of arrays grouped in the same category in the loop processing part, A step of converting a description that refers to a corresponding element of one array configured by an array of numbers, and a plurality of arrays that form the one array have the same position in the array, according to the converted program. An object code in which an element includes an object code for arranging one array composed of the plurality of arrays so as to be sequentially arranged at consecutive positions on a main memory of a computer that executes the program when the program is executed And a step of generating a sequence. 5. A method of compiling a program for generating an object code to be executed on a computer having a main memory and a cache memory from a program, and determining a part describing a looping process of the program. In the part that describes the looping process and the step that is determined, among the multiple arrays that are described to be referenced, the array types are the same, and in each processing of the loop processing The step of grouping arrays that are referred to and having the same position in the array within the same group, and the description that refers to the elements of a plurality of arrays grouped in the same group within the loop processing part From the step of converting the description that refers to the corresponding element of one array configured by the array of
Specifies that the elements of each array that have the same position in an array of multiple arrays that are grouped into the same category of the program are sequentially arranged at consecutive positions in the main memory of the computer that executes the program when the program is executed. And a step of generating an object code string including object code. 6. A storage device storing a source program,
A computer system comprising a processing device for converting the source program, wherein the processing device describes means for determining a portion describing a looping process of the program, and the determined looping process. Position of the elements of the array in the array that are of the same array type and are referenced in each processing of the loop processing among the plurality of arrays described to be referenced. Means for assigning the same category to the same sequences, and a description defining a plurality of arrays to which the same category of the program is assigned is configured by the plurality of arrays.
A means for changing to a description that defines one array and a description that refers to elements of a plurality of arrays that are grouped in the same category in the portion that describes the loop processing are configured by the plurality of arrays. And a means for changing the description to refer to the corresponding element of one array. 7. The computer system according to claim 6, wherein the processor further includes, from the program whose description has been converted, each element having the same position in the array of a plurality of arrays forming the one array. When the program is executed, an object code sequence including an object code for arranging one array composed of the plurality of arrays so as to be sequentially arranged at consecutive positions in the main memory of the computer that executes the program A computer system having means for generating.