WO2004066146A1

WO2004066146A1 - List management program and list management device

Info

Publication number: WO2004066146A1
Application number: PCT/JP2003/000417
Authority: WO
Inventors: Katsuyoshi Moriya; Masanori Kaneko
Original assignee: Fujitsu Limited
Priority date: 2003-01-20
Filing date: 2003-01-20
Publication date: 2004-08-05

Abstract

A list management program for managing data of a list structure used by a computer having a cache memory, realizing a data registering section for creating a node in such a way that the first address is a multiple of the cache line size and adding the node to a variable address list and a data retrieving section for carrying out control using a prefetch instruction so that the data on the nodes is present in the cache memory when a node is retrieved.

Description

List management program and list management device

Technical field

The present invention relates to a list management program and a list management device for managing data having a list structure used in a computer having a cache memory.

List management that can prevent data search speed from dropping due to cache mistakes

The present invention relates to a program and a list management device. .

Background art

Conventionally, a binary search tree has been used as a method for searching and importing data at high speed. That is, assuming that the number of data to be searched is η, in a binary search tree, the average computational complexity of both data search and import is of the order of log η. On the other hand, in the linear search, the computational complexity of the search is of the order of η, and in the case of insertion, the computational complexity is of the order of η if it is necessary to confirm that the same data does not exist. In a binary search that uses magnitude comparison as in the case of a binary search tree, the computational complexity of the search is log n, but the computational complexity of the order is n. For information on such conventional search technologies, see, for example, Kiyoshi Ishihata, “Algorithms and Data Structures”, Iwanami Lecture, Soft Tuesce Science, March 30, 1989, 5.57-8 It is introduced in 7.

However, when using a list structure such as a binary search tree on a computer with a cache memory, a cache miss occurs every time a pointer is entered, and it takes a lot of time to search and insert data. There's a problem.

In other words:-If the latency of the misses (the delay of reading the data including cache) is very large compared to the latency of the cache hit (the delay of reading the data from the cache memory), the search is performed. The actual search speed is based on whether or not the data to be searched hits the cache memory rather than the amount of calculation required for It greatly affects the degree.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem of the related art, and has as its object to provide a list management program and a list management device capable of preventing a reduction in data search speed due to a cache miss. The purpose is. Disclosure of the invention

In order to solve the above-described problems and achieve the object, the present invention is directed to a list management program for managing data of a list structure used in a computer having a cache memory. A data registration procedure for registering data in a list in which the number of data to be stored in each node constituting the list structure is determined based on the number of data that can be read into the memory; and When searching for data sequentially for nodes constituting the list, a data search procedure for performing search while controlling each node to be in a state of being read into the cache memory at the start of search of each node. It is characterized by executing.

The present invention also relates to a list management device for managing data having a list structure used in an information processing device having a cache memory, wherein the number of data that can be read into the cache memory by one memory access is determined. A data registration unit for registering data in a list in which the number of data to be stored in each node constituting the list structure is determined; and a node constituting the list by registering the data registered in the list by the data registration unit. And a data search means for performing a control so that each node is in a state of being read into the cache memory at the start of the search of each node. .

• According to the effort, data is stored in a list in which the number of data to be stored in each node forming the list structure is determined based on the number of data that can be read into the cache memory by one memory access. When searching for the nodes that make up a list of registered data in order, when each node starts searching, Since the search is performed while controlling the data to be read into the cache memory, it is possible to prevent a reduction in the data search speed due to a cache miss.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is an explanatory diagram for explaining the concept of thread variable variable management by the list management device according to the present embodiment. FIG. 2 is a diagram illustrating the list management device according to the present embodiment. FIG. 3 is a functional block diagram showing the configuration, FIG. 3 is a flowchart showing a processing procedure of a data search unit shown in FIG. 2, and FIG. 4 is a flowchart showing a processing procedure of data registration processing. FIG. 5 is a diagram showing a computer system that executes the list management program according to the present embodiment. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, preferred embodiments of a list management program and a list management device according to the present invention will be described in detail with reference to the accompanying drawings. Here, a case where the address management of a thread local variable is performed using the list management device according to the present invention will be described.

Here, a thread local variable is a variable that has a variable with the same name in the main thread and is local to the child thread. Then, the list management device uses the address of a variable having the same name in the main thread (hereinafter referred to as “main thread variable address”).

) And the address of the thread local variable (hereinafter referred to as “thread local variable address”) are managed in association with each other, and given the main thread variable address, the corresponding thread local variable address is returned.

First, the concept of thread control variable address management in the list management device according to the present embodiment will be described. FIG. 1 is an explanatory diagram for explaining the concept of thread local variable address management by the list management device according to the present embodiment. FIG. 2A is a diagram showing conventional thread local variable address management. Figure (b) is Mel a view showing a thread-local variables address management according to the embodiment ₀

In the conventional thread-local variable address management, as shown in Fig. 2 (a), the main thread variable address and the thread local variable address are determined by using a binary search tree whose key is the address of the variable in the main thread. It was managed in correspondence. Specifically, on the source program

intva, νD, νc, νd, ve, νι, νg;

The variables v a, v b, v c, v d, v e, v f, and v g are managed by a binary search tree with the variable v d as the root and the leaves v a, v c, v e, and v g as the leaves. Each node has a main thread variable address and a thread variable variable address. For example, a node corresponding to the variable Vd is a main thread variable address of "0 0 AC" in hexadecimal. And the hexadecimal "01BC" thread low force variable variable address.

When searching such a binary search tree, first, the given main thread variable address is compared with the Vd main thread variable address, and the given main thread variable address is smaller than the Vd main thread variable address. In this case, the node on the left side, that is, the node of Vb is accessed, and a cache miss occurs at this time. Similarly, the given main thread variable address is compared with the main thread variable address of Vb, and if the given main thread variable address is smaller than the main thread variable address of Vb, the node of Va is Is accessed, and a cache miss also occurs at this time. That is, in the conventional thread variable variable address management, a cache miss occurs every time each node is entered, and it takes much time to search.

On the other hand, as shown in FIG. 11B, in the present embodiment, in the variable variable management, which is a descendant of the present invention, (n−1) messages are stored in one node using the variable address list 100. The thread variable address, a pointer to the next node, and (n-1) thread draw force variables corresponding to the (n-1) main thread variable addresses, respectively. Manage dresses in order. Where n is the size of the cache line divided by the address size, so the size of each node is twice the size of the cache line. For example, if the cache line size is 64 bytes and the address size is 4 bytes, then n = 64 ÷ 4 = 16 and the size of each node is 128 bytes.

Also, create each node so that the start address of each node is a multiple of the cache line size. In this way, by setting the head address of each node to be a multiple of the cache line size and doubling the size of each node to the cache line, when the head of the node is accessed, (n — 1) main thread When the variable address and the pointer to the next node are read into the cache memory, and the address of the node's first address + cache line size is accessed, (n-1) thread local variable addresses can be read into the cache memory. .

When searching for a thread local variable address, a prefetch instruction is issued during the search initialization process to the first T-address of the first node and the first node's first address + the address of the cache line size, When searching for the first node, prepare so that the first node is in the cache memory. Also, before searching for the first node, the address of the second node and the address of the first node + cache line size are used using the address of the next node stored in the first node. By issuing a prefetch instruction, the second node is placed in the cache memory while the first node is being searched.

As described above, in the thread-based variable address management according to the present embodiment, control is performed such that all data of the nodes is stored in the cache memory at the time of searching for data of each node in the variable address list 100. As a result, it is possible to prevent the search efficiency from being lowered due to the latency of the cache memory.

For example, if the number of data to be searched is 64, the latency of cache miss is 82 clocks, and the latency of cache hit is 3 clocks, the conventional thread In local variable address management, the average number of searches is about log ₂ 64 _ l = 5, that is, about 5 times. Since a cache miss occurs each time a search is performed, the number of clocks required for the search is 8 Two clocks X 5 = 4 10 clocks. On the other hand, in the thread local variable address management according to the present embodiment, the average number of searches increases to 6 4 = 2 = 32 times, but since no cache miss occurs, the number of clocks required for the search is 3 clocks X 3 2 = 96 clocks, and the search time can be greatly reduced.

Next, the configuration of the list management device according to the present embodiment will be described. FIG. 2 is a functional block diagram showing a configuration of the list management device according to the present embodiment. As shown in the figure, the list management device 200 includes a data registration unit 210, a data search unit 220, and a list storage unit 230.

The data registration unit 210 is a processing unit that creates a new entry and adds it to the variable address list 100 0 when the thread local variable address is not registered in the variable address list 100. When the node that has added a new entry becomes full, the data registration unit 210 creates a new node, and makes the first address of the created node a multiple of the size of the cache line. To

The data retrieval unit 220 is a processing unit that receives a main thread variable address, retrieves and returns a corresponding thread local variable address. The data search unit 220 controls the search using a prefetch instruction so that the data of the node to be searched is always in the cache memory.

The list storage unit 230 stores a main thread variable address and a thread local variable address in association with each other. More specifically, the variable address list 10 shown in FIG. 1 (b) is stored. Note 0.

In this way, the list management device 200 creates a node such that the leading address is a multiple of the cache line size, and the data search unit 220 searches for the data. The cache memory is controlled by using a prefetch instruction so that the data of the node to be executed is always in the cache memory. , It is possible to prevent a decrease in search efficiency caused by the search.

Next, the processing procedure of the data search unit 220 shown in FIG. 2 will be described. FIG. 3 is a flowchart showing a processing procedure of the data search unit 220 shown in FIG.

As shown in the figure, the data search unit 220 receives the first node of the variable address list 100 stored in the list storage unit 230 in consideration of the cache miss latency during the search initialization process. Is prefetched (step S301). Also, before starting the search for the first node, the next node is prefetched (step S302), so that the next node enters the cache memory before the search for the next node starts. prepare.

Then, the data search index i in the node is initialized to “1” (step S303), the i-th data is extracted from the node (step S304), and the end of the registered data is obtained. (Step S305). Here, whether or not the end of the registered data is determined depending on whether or not the data value is “0”.

As a result, if it is not the end of the registered data, it is checked whether or not the given main thread variable address matches the data (step S306), and if not, i is set to “ The value is increased by 1 (step S307), and it is checked whether the i-force is smaller than "16", that is, whether or not the next data exists in this node (step S308).

If i is smaller than "1 6", the flow returns to step S304 to check the next data. If i becomes "16J", the flow returns to step S302. Search for the next node At this time, the next node is in the state of being stored in the cache memory due to the prefetching of the previous step S302, and before starting the search for the next node, one after another Prefetch.

On the other hand, if the given main thread variable address matches the data, the corresponding thread local variable address is returned (step S309), and the processing ends. Complete. If the i-th data is at the end of the data, the main thread variable address and the corresponding thread local variable address are added to the node as new entries by data registration processing (step S310). The registered thread local variable address is returned (step S311).

As described above, the data search unit 220 prefetches the next node before starting the search of each node in the variable address list 100, so that all data in the node is searched at the time of each node search. Are in the cache memory.

Next, the processing procedure of the data registration processing (step S310) will be described. FIG. 4 is a flowchart showing a procedure of a data registration process. Note that this data registration processing corresponds to the processing of the data registration unit 210 shown in FIG.

As shown in the figure, in this data registration process, the address of a new local variable is obtained (step S401), the obtained address is used as the thread local variable address, and the variable with the given main thread variable address. It is registered as a new entry in the address list 100 (step S402). Then, it is checked whether or not the node to which the new entry has been added has room for registering the next entry (step S403). If there is a space, the process ends as it is.

On the other hand, if there is no free space, a new node with a multiple of the cache line size as the start address is created (step S404). At this time, all data in the created node is cleared to zero. Then, the created node is connected to the variable address list 100 (step S405).

As described above, in the present embodiment, when the data registration unit 21 cr newly creates a node to be added to the variable address list 100, the head address is set to a multiple of the cache line size. The data search unit was designed to use a prefetch instruction so that the node data was always stored in the cache memory when searching for each node. High-speed thread local variable addressing by preventing search efficiency from deteriorating due to the latency of Can be searched.

In the present embodiment, the list management device has been described. However, by realizing the configuration of the list management device by software, a list management program having the same function can be obtained. Therefore, a computer system that executes the list management program will be described.

FIG. 5 is a diagram showing a computer system that executes the list management program according to the present embodiment. As shown in the figure, the computer system 500 includes a main body 510, a display device 520 for displaying a display screen according to an instruction from the main body 510, and a keyboard 530 for inputting various information to the computer system 500. And a mouse 540 for specifying a position on the display screen.

The main unit 510 includes a CPU 511 having a cache, a RAM 512, a ROM 513, a hard disk drive (HDD) 514, a CD-ROM / DVD drive 515, an FD drive 516, and an I / O interface 51 7 And a LAN interface 518 and a modem 519.

The computer system 500 can be connected to another computer system (PC) 551, a server 552, a printer 553, and the like via a LAN 550 connected to a LAN interface 518, and can be connected to a public line 560 via a modem 519. Can be connected to

The list management program executed in the computer system 500 is stored in a portable storage medium such as a floppy disk (FD), a CD-ROM, a DVD disk, a magneto-optical disk, and an IC card. It is read from the medium and installed on computer system 500.

Alternatively, the list management program may be a database of a server 552 connected via a LAN interface 518, a database of another computer system (PC) 551, and a database of another computer system connected via a public line 560. Etc., read from these databases, and installed in the computer system 500. The installed list management program is stored in the HDD 514 and executed by the CPU 511 using the RAM 511, the ROM 513, and the like. According to the present invention, data is registered in a list in which the number of data to be stored in each node constituting the list structure is determined based on the number of data that can be read into the cache memory by one memory access, and the registered data is listed. When searching for the nodes that make up the nodes in order, at the start of the search for each node, control is performed so that each node is in the state of being read into the cache memory. This has the effect of preventing a reduction in data search speed due to a cache miss. Industrial applicability

As described above, the list management program and the list management device according to the present invention are suitable for the case where data is managed using a list structure in an information processing device having a large latency of cache miss.

Claims

The scope of the claims

1. A list management program for managing data of a list structure used in a computer having a cache memory,

A data registration procedure for registering data in a list in which the number of data to be stored in each node constituting the list structure is determined based on the number of data that can be read into the cache memory by one memory access;

When searching the data registered in the list by the data registration procedure for nodes constituting the list in order, it is assumed that each node is read into the cache memory at the start of the search of each node. Data search procedure to search while controlling,

A list management program characterized by executing the following.

2. The data search procedure is characterized in that a prefetch instruction is issued to a node to be searched in advance, so that the node is read into the cache memory at the start of the search of the node. The list management program according to claim 1.

3. In the data search procedure, a prefetch instruction is issued to the next node before starting the search of each node, so that the next node is read into the cache memory at the start of the search of the next node. 3. The list management program according to claim 2, wherein the list management program performs control for setting the list management state.

4. The data registration procedure is characterized in that, when a new node to be used for registering the data becomes necessary, a node to be placed in the cache memory is created by two memory accesses to register the data. The list management program according to claim 1, 2, or 3. .

5. In the data registration procedure, when a new node to be used for registering the data becomes necessary, a node having a size twice as large as the cache line size is created using a multiple of the cache line size as a leading address. 5. The list management program according to claim 4, wherein the created node is stored in the cache memory by two memory accesses.

6. A list management device for managing data having a list structure used in an information processing device having a cache memory,

Data registration means for registering data in a list in which the number of data to be stored in each node constituting the list structure is determined based on the number of data that can be read into the cache memory by one memory access;

When searching the data registered in the list by the data registration means for nodes constituting the list in order, it is assumed that each node is read into the cache memory at the start of the search of each node. Data search means for searching while controlling,

A list management device comprising:

7. The data search means executes a prefetch instruction to a node to be searched in advance to control the node to be in a state of being read into the cache memory at the start of the search of the node. The list management device according to claim 6.

8. The data search means issues a prefetch instruction to the next nonide before starting the search of each node, so that the next node is read into the cache memory at the start of the search of the next node. 8. The list management device according to claim 7, wherein the list management device performs the following control.

9. The data registering means is characterized in that, when a new node to be used for registering the data becomes necessary, a node to be placed in the cache memory is created by two memory accesses to register the data. 9. The list management device according to claim 6, 7, or 8.

10. The data registering means, when a new node used for registering the data becomes necessary, sets a node having a size twice as large as the cache line size with a multiple of the cache line size as a leading address. 10. The list management device according to claim 9, wherein the created node is placed on the cache memory by performing two memory accesses.