JPH07284125A - Time base correction device - Google Patents

Abstract

PURPOSE:To provide the time base correction device in which time base is corrected for plural times within one horizontal scanning period. CONSTITUTION:The device is provided with a phase angle detection circuit 10 extracting a color burst signal from a digital composite video signal to detect a time base fluctuation in the extracted color burst signal and with a division accumulation circuit 15 calculating a difference between a time base fluctuation in the color burst signal for a just preceding horizontal scanning period and a time base fluctuation of the color burst signal for a current horizontal scanning period, dividing the calculated difference into plural values, accumulating the uniformly divided differences and adding the accumulated sum for each accumulation to the time base fluctuation of the color burst signal for the current horizontal scanning period, and the accumulated output at each summing point of time in the division accumulation circuit 15 is used for a time base correction value to correct the time base.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis correction device which improves the accuracy of correction of time axis fluctuations during a horizontal scanning period, and more particularly to a time axis correction device which performs velocity error correction.

[0002]

2. Description of the Related Art Velocity error refers to a phase error that fluctuates within one horizontal scanning period of a composite video signal, that is, a lead or lag of the time axis. In a video signal recording / reproducing apparatus or the like, a phase error occurs due to an instantaneous error in relative speed between the magnetic tape and the magnetic head. From now on, the name of velocity error has arisen.

When a phase error is detected by using a color burst signal in a composite video signal, the phase error is intermittently detected and a velocity error occurs. This will be described with reference to FIG. 9. Since phase comparison is performed using a color burst signal, it is performed at points A and B in FIG. The time base correction will be performed based on the phase error detected in. That is, the phase error is detected for each horizontal scanning period, and the time axis correction based on this phase error is performed during one horizontal scanning period. Therefore, it is not possible to correct the phase error that changes within one horizontal scanning period. It was Therefore, FIG.
An error corresponding to the amount of change in the phase error indicated by the shaded portion in (b) remains or becomes large, and color unevenness occurs on the right side of the screen.

[0004]

Therefore, in the conventional art,
The digitized composite video signal is stored in the memory, the clock on the reading side is modulated according to the velocity error component, and the digitized composite video signal is read from the memory by the modulated clock on the reading side. However, there was a problem that the time axis could not be corrected accurately.

It is an object of the present invention to provide a time axis correction device capable of correcting the time axis a plurality of times within one horizontal scanning period.

[0006]

A time axis correction apparatus of the present invention is a color burst signal from a digitized composite video signal sampled and A / D converted by a sampling pulse synchronized with a horizontal synchronizing signal in the composite video signal. Color burst signal extraction means for extracting the color burst signal, detection means for detecting the time-axis variation value of the extracted color burst signal, time-axis variation value of the color burst signal in the immediately preceding horizontal scanning period, and color burst signal in the current horizontal scanning period Calculation means for calculating the difference from the time-axis fluctuation value of the above, and for equally dividing the calculated difference value into a plurality of values, and for cumulatively adding the equally divided difference values and for each cumulative addition A cumulative addition means for adding the time-axis fluctuation value of the color burst signal in the horizontal scanning period, and the cumulative addition output at each addition time point of the cumulative addition means. And performing correction of the time axis as the time axis correction value.

[0007]

In the time axis correction apparatus of the present invention, the difference between the time axis fluctuation value of the color burst signal in the immediately preceding horizontal scanning period and the time axis fluctuation value of the color burst signal in the current horizontal scanning period is equally divided into a plurality of values. The time-axis variation value of the color burst signal evenly divided is added to the time-axis variation value of the color burst signal in the horizontal scanning period, and the added time-axis variation value is added as the time-axis correction value at each addition. The axis is corrected. Therefore, 2 including the time-axis variation value of the color burst signal in the immediately preceding horizontal scanning period
The time-axis correction based on the time-axis fluctuation of the horizontal scanning period will be performed a plurality of times during one horizontal scanning period. Therefore, as compared with the conventional time-axis correction for each horizontal scanning period based on the time-axis variation value detected for each horizontal scanning period, the optimum time-axis correction is performed in any part of the one horizontal scanning period. As a result, the time axis correction approximately corresponding to the time axis fluctuation within one horizontal scanning period is performed.

[0008]

EXAMPLES The present invention will be described below with reference to examples. Figure 1
FIG. 1 is a block diagram showing a configuration of an embodiment according to a time axis correction device of the present invention.

The composite video signal is supplied to the sync separation circuit 1,
The sync separation circuit 1 separates the horizontal sync signal. The oscillation output of the voltage-controlled oscillator 2 having the free-running oscillation frequency of 4 fsc is supplied to the frequency divider 3 and divided by 910 to obtain the output in the period 1 horizontal scanning period. The output of the frequency divider 3 and the horizontal sync signal separated by the sync separation circuit 1 are supplied to the phase comparator 4 for phase comparison. Here, fsc is the frequency of the color carrier. The phase comparison output of the phase comparator 4 is supplied to the loop filter 5, and the high frequency component in the phase comparison output is removed. The output of the loop filter 5 is supplied to the voltage controlled oscillator 2 as a frequency control voltage, the oscillation frequency of the voltage controlled oscillator 2 is controlled, and the voltage controlled oscillator 2 generates a clock pulse synchronized with the horizontal synchronizing signal in the composite video signal. To do. here,
The sync separation circuit 1, the voltage controlled oscillator 2, the frequency divider 3, the phase comparator 4, and the loop filter 5 form a PLL circuit.

The clock pulse output from the voltage controlled oscillator 2 is supplied to the A / D converter 6 as a sampling pulse to sample the composite video signal, and the A / D converter 6 is sampled.
The composite video signal is converted into a digitized composite video signal by. The clock pulse output from the voltage controlled oscillator 2 is used as a write clock pulse, and the digitized composite video signal is written in the memory 7 based on the write clock pulse. Using the oscillation output of the crystal oscillator 8 having an oscillation frequency of 4 fsc as a read clock pulse, the digitized composite video signal written in the memory 7 is read based on the read clock pulse, and the digitized composite video signal read from the memory 7 is read. The Y / C separation circuit 9 is supplied with Y / C
The separation circuit 9 separates into a digitized luminance signal and a digitized color signal (hereinafter, also referred to as a color signal by omitting digitization).

The luminance signal separated by the Y / C separation circuit 9 is supplied to the D / A converter 30, converted into an analog signal and output. On the other hand, the color signals separated by the Y / C separation circuit 9 are supplied to a phase angle detection circuit 10 and a delay circuit 16 which include a color burst signal extraction means and a detection means for detecting a time base fluctuation value of the color burst signal. As shown in FIG. 2, the phase angle detection circuit 10 is composed of a 4-phase quadrature converter 11, cumulative adders 12 and 13, and a quadrature signal generation circuit 14.

As shown in FIG. 2, the 4-phase orthogonal converter 11 has
The color burst signal extracting circuit 11-1 which is a color burst signal extracting means for extracting the color burst signal from the color signal by supplying the color signal and the extraction pulse for extracting the color burst signal, and the oscillation output of the crystal oscillator 8 are divided into four minutes. The frequency divider 11-which divides the frequency and outputs the output of the frequency fsc
2 and phase shifters 11-3, 11 connected in tandem to sequentially shift the phase of the output of the frequency divider 11-2 by 90 degrees.
-4, 11-5, frequency divider 11-2, phase shifter 11-3,
11-4 and 11-5 are used as sampling pulses, and sample hold circuits 11-6 to 11-9 sample-hold the color burst signal extracted by the color burst signal extraction circuit 11-1. There is.

Frequency divider 11-2, phase shifters 11-3, 11-
The phases of the sampling pulses output from 4 and 11-5 are different by 90 degrees, and the sampling pulses are N1, N2, N3, and N4. Although the case where the sampling pulses N2 to N4 are generated using the phase shifters 11-3 to 11-5 has been illustrated above, the output of the frequency divider 11-2 is shifted by 90 degrees by the phase shifter 11-3. The sampling pulse N2 and the output of the frequency divider 11-2 are inverted by an inverter to obtain the sampling pulse N2.
3, the output of the inverter is converted to 9 by the phase shifter 11-5.
The phase may be shifted by 0 degree to obtain the sampling pulse N4.

The color burst signal extracted by the color burst signal extracting circuit 11-1 is shown by a solid line in FIG. 5 if it is shown in analog form for the sake of description. This color burst signal is a sampling pulse N.
Sampled by 1, N2, N3, N4. The sampling time points are the time points indicated by arrows A, B, C, and D in FIG. 5, which are respectively shifted by 90 degrees, and there is a phase difference of θ between the sampling time point by the sampling pulse N1 and the color burst signal. This is because the phase of the oscillation output of the crystal oscillator 8 does not match the phase of the color burst signal.

Sampling pulses N1, N2, N3,
Four-phase orthogonal transformer 1 sampled by N4, respectively
When the output from 1 is the outputs S1, S2, S3, and S4, the outputs S1 to S4 are as shown in each equation of the equation 1,
P indicates the amplitude of the color burst signal, and A indicates the DC clamp level of the composite video signal.

[0016]

[Equation 1]

The cumulative adder 12 is composed of an adder 12-1 and a register 12-2, and the cumulative adder 13 is composed of an adder 13-1 and a register 13-2. Four
The output S1 and the output S3 of the phase orthogonal converter 11 are added to the adder 12
-1 to subtract the latter from the former, and adder 12-1
The subtraction output (2Psinθ) of the register 12-2 is supplied to and held in the register 12-2, and the output of the register 12-2 is added by the adder 12-1.
Supply to and add. The addition in the adder 12-1 is 1
The number of times e, which is less than the wave number of the color burst signal during the horizontal scanning period, is accumulated. Therefore, the adder 12-1
And the register 12-2 constitute a cumulative adder 12 in which accumulation is performed.
It is set to 2-2. The DC clamp level A of the composite video signal is canceled by the subtraction in the adder 12-1, and the register 12-2 stores 2Ps of 2Ps by the accumulation.
The addition result of inθ is to be registered.

Similarly, the outputs S2 and S4 of the 4-phase quadrature converter 11 are supplied to the adder 13-1, and the latter is subtracted from the former, and the subtraction output (2Pcosθ) of the adder 13-1 is registered in the register 13. -2 to hold it, register 13-2
Is supplied to the adder 13-1 to be added. Adder 1
The addition in 3-1 is performed only e times, which is the same number of times as the number of additions in the cumulative adder 12. Therefore, the adder 1
3-1 and the register 13-2 constitute a cumulative adder 13 in which accumulation is performed, and the accumulated value is registered in the register 13-2. The DC clamp level A of the composite video signal is canceled by the subtraction in the adder 13-1, and the result of addition of 2Pcosθ of e times is registered in the register 13-2 by accumulation.

The quadrature signal generation circuit 14 includes a divider 14-1,
It is composed of a memory 14-2 and a multiplier 14-3.
The output of the register 12-2 and the output of the register 13-2 are supplied to the divider 14-1, and the divider 14-1 divides the output of the register 12-2 by the output of the register 13-2. Therefore, the output of the divider 14-1 becomes a value corresponding to (tan θ) by the calculation in the divider 14-1. The output of the divider 14-1 is supplied to the memory 14-2 as address data, and the data stored in the memory 14-2 is read once in one horizontal scanning period and maintained until the next reading. Here, the value of (cos θ) corresponding to (tan θ) is (tan) in the memory 14-2.
Each θ) is stored as shown in Table 1.

[0020]

[Table 1]

The data read from the memory 14-2 and the output of the divider 14-1 are supplied to the multiplier 14-3 for multiplication. Therefore, the output from the multiplier 14-3 is (si
nθ) value. Therefore, the memory 14-
The value from 2 to (cos θ) is from the multiplier 14-3 to (sin
The value of θ) is output. That is, a quadrature signal is output from the memory 14-2 and the multiplier 14-3.

Therefore, in the phase angle detection circuit 10, the phase difference θ corresponding to the time axis fluctuation value is detected, including the detecting means for detecting the time axis fluctuation value of the color burst signal, and sin θ with respect to the phase difference θ is detected. And a quadrature signal of cos θ is output.

Output from the phase angle detection circuit 10 (si
The value of (nθ) and the value of (cosθ) are calculated by calculating the difference between the time-axis variation value of the color burst signal in the immediately preceding horizontal scanning period and the time-axis variation value of the color burst signal in the current horizontal scanning period. Arithmetic means for equally dividing the difference value into a plurality of values; and cumulative addition means for cumulatively adding the uniformly divided difference values and adding the cumulative addition value to the time-axis fluctuation value of the immediately preceding color burst signal for each cumulative addition. Is supplied to the dividing / cumulative adding circuit 15 that divides one horizontal scanning period into a plurality of periods, and sequentially accumulates and outputs the correction signals IC and QC.

As shown in FIG. 3, the division / cumulative addition circuit 15 does not delay the output of the delay circuit 15-1 for delaying the value of (sin θ) by one horizontal scanning period and the output of the delay circuit 15-1 ( subtractor 15-3 for subtracting from the value of (sin θ)
And the register 1 in which the subtraction result of the subtractor 15-3 is set.
5-5 and the register number of register 15-5 are N (N is a natural number)
A dividing circuit 21 for dividing the value of (sin θ) into N and a value of (cos θ) of 1
Delay circuit 15-2 for delaying the horizontal scanning period and delay circuit 1
The output of 5-2 is subtracted from the undelayed (cos θ) value, the subtracter 15-4, the register 15-6 in which the subtraction result of the subtractor 15-4 is registered, and the register 15-6. And a divider 15-8 for dividing the number by N (co
The division circuit 22 divides the value of sθ) into N.

The division / cumulative addition circuit 15 further adds the adder 15-9 with the undelayed (sin θ) value as an initial value and adding the number and the division result of the divider 15-7. A cumulative adder 23, which comprises a register 15-11 whose register number is updated by the addition result of the adder 15-9, cumulatively adds the outputs of the dividing circuit 21 and outputs a correction signal IC,
The adder 15-10 and the addition result of the adder 15-10 in which the value of non-delayed (cos θ) is added as an initial value and the addition result and the division result of the divider 15-8 are added are A division circuit 22 including a register 15-12 to be updated
And an accumulative adder 24 that outputs the correction signal QC by accumulating the outputs of.

The value of (sin θ) is supplied to the delay circuit 15-1 and delayed by one horizontal scanning period.
The delayed (sin θ) value at 1 is subtracted from the undelayed (sin θ) value, and the output of the subtracter 15-3 is registered in the register 15-5. Therefore, in the register 15-5, the difference (θb-θa = Δ) between the value (θa) of (sin θ) in the previous horizontal scanning period and the value (θb) of (sin θ) in the current horizontal scanning period.
θ) will be registered.

Difference registered in the register 15-5 (Δθ)
Is divided by a predetermined number N in the divider 15-7. The difference (Δθ) is divided into N by the division by the divider 15-7, and the division result becomes (Δθ / N). The division result (Δθ / N) by the divider 15-7 is the adder 15-
9 and the value (θb) stored in the register 15-11 and added in the register 15-11 are added in the adder 15-9, and the addition result is registered in the register 15-11. Is updated to the addition result. Therefore, the adder 15-9
And the register 15-11 constitute a cumulative adder 23, and cumulative addition is performed (N-1) times.

As a result of this accumulation, the first addition is in register 1
Since the register number of 5-11 is (θb), the register 15-
In {11}, {θb + Δθ (N-1) / N} will be registered. FIG. 7 schematically shows this relationship. Figure 7 (a)
Indicates the detected phase difference. FIG. 7B shows the register 15
The difference (Δθ) registered in −5 is shown, and FIG.
The register number of the register 15-11 in the case of 9 is shown, which is output as the correction signal IC.

The operation of the division circuit 22 and the cumulative adder 24 is similar, and the value of (cos θ) is the delay circuit 15-2.
Is supplied to the delay circuit 1 and delayed by one horizontal scanning period.
The delayed (cos θ) value in 5-2 is subtracted from the undelayed (cos θ) value, and the output of the subtracter 15-4 is registered in the register 15-6.
Therefore, in the register 15-6, the difference (θb′−) between the value (θa ′) of (cos θ) in the previous horizontal scanning period and the value (θb ′) of (cos θ) in the current horizontal scanning period.
θa ′ = Δθ ′) will be registered.

The difference (Δθ entered in the register 15-6
′) Is divided by a predetermined number N in the divider 15-8.
The difference (Δθ ′) is divided into N by the division by the divider 15-8, and the division result becomes (Δθ ′ / N). The division result (Δθ ′ / N) by the divider 15-8 is supplied to the adder 15-10, and the value (θb ′) registered in the register 15-12 is added by the adder 15-10. , This addition result is registered in the register 15-12,
This registered number is updated to the addition result every addition. Therefore, the adder 15-10 and the register 15-12 form a cumulative adder 24, and cumulative addition is performed (N-1) times.

As a result, the first addition is done in register 15-1.
Since the register number of 2 is (θb ′), as a result of the accumulation, the register 15-12 is registered with {θb ′ + Δθ ′ (N−1) / N}, which is the correction signal QC. Is output as.

Therefore, the correction signals IC and QC output from the division / cumulative addition circuit 15 are not intermittent values for each horizontal scanning period, but the phase difference in the current horizontal scanning period,
The difference between the phase difference in the immediately preceding horizontal scanning period and the phase difference in the current horizontal scanning period and the value obtained by adding the phase difference in the current horizontal scanning period are almost smoothly connected.

On the other hand, the color signal separated by the Y / C separation circuit 9 is supplied to the delay circuit 16 to delay it, and the color signal output from the delay circuit 16 is supplied to the demodulation phase correction circuit 17. Here, the delay time in the delay circuit 16 is set to the sum of the times required for the processing in the phase detection circuits 10 and the division / cumulative addition circuit 15, for example, approximately H / 4. H is one horizontal scanning period.

The demodulation phase correction circuit 17 digitally demodulates a color signal into a color difference signal (see FIG. 4).
And a demodulated color difference signal when the phase angle θ is 0, that is, when the phase is not shifted, the demodulation axis (RY) axis,
It is composed of a phase angle correction circuit 19 (see FIG. 4) that corrects the phase so as to match the (BY) axis.

As shown in FIG. 4, the color demodulation circuit 18 divides the oscillation output of the crystal oscillator 8 into two and outputs the output of frequency 2fsc, and the output of the frequency divider 18-1. An inverter 18-2 for inverting the signal, a sample hold circuit 18-3 for sampling and holding a color signal with the output of the frequency divider 18-1 as a sampling pulse, and a color signal for sampling with the output of the inverter 18-2 as a sampling pulse. And hold sample and hold circuit 18
-4, and digitally demodulates the color signal. The sampling pulses output from the frequency divider 18-1 and the inverter 18-2 have phases different from each other by 180 degrees.
6, and the outputs of the sample hold circuits 18-3 and 18-4 are S5 and S6, respectively.

The demodulated color difference signal output digitally demodulated in the color demodulation circuit 18 is an R-Y axis demodulated color difference signal output {D (RY)} whose phase is shifted by θ and a phase-shifted B-. Y-axis demodulated color difference signal output {DI (BY)},
R-Y axis demodulated color difference signal output with a phase shift of θ {DI (R
-Y)} and a BY-axis demodulated color difference signal output {D (BY)} with a phase shift of θ, where R-Y with a phase shift of θ.
The demodulated color difference signal output {D (RY)} of the axis and the demodulated color difference signal output {DI (RY)} of the RY axis whose phase is shifted by θ are the rising edges of the output of the frequency divider 18-1. Is output from the sample hold circuit 18-3 and the phase is deviated by θ from the BY demodulated color difference signal output {D (BY)} and the phase is deviated by θ.
The Y-axis demodulated color difference signal output {DI (BY)} is output from the sample hold circuit 18-4 at every rise of the output of the inverter 18-2.

Here, the BY-axis demodulated color difference signal output {DI (B-Y)} whose phase is deviated by θ is B-Y whose phase is deviated by θ.
This is a phase-inverted signal of the axis demodulated color difference signal output {D (BY)}, and the phase is shifted by θ. The phase of the RY axis demodulated color difference signal output {DI (RY)} is shifted by θ. It is a phase-inverted output of the demodulated color difference signal output {D (RY)} on the RY axis.
The temporal relationship among the demodulated color difference signal output, the output of the frequency divider 18-1 and the output of the inverter 18-2 is as shown in FIG. 6, and FIG. 6A shows the frequency relation of the frequency divider 18-1. 6B shows the output of the inverter 18-2.
(C) shows the demodulated color difference signal output {D (RY)} on the RY axis with the phase shifted by θ and the demodulated color difference signal output {DI (RY)} on the RY axis with the phase shifted by θ. , FIG. 6D shows a demodulated color difference signal output of the BY axis which is out of phase by θ (DI (B-
Y)} and a BY-axis demodulated color difference signal output {D (BY)} with a phase shift of θ.

The phase angle correction circuit 19 includes multipliers 19-1 to 19-1.
9-4, adders 19-5 and 19-6, latch circuit 1
9-7 and 19-8, and a multiplexer 19-9. The phase output from the color demodulation circuit 18 is θ
The demodulated color difference signal output of the shifted (RY) axis is output to the multiplier 19-
1 and 19-2, the correction signal QC output from the division / cumulative addition circuit 15 is multiplied in the multiplier 19-1, and the correction signal IC output from the division / cumulative addition circuit 15 and the multiplier 19- Multiply at 2. Color demodulation circuit 1
The demodulated color difference signal output on the (BY) axis whose phase is shifted by θ is supplied to multipliers 19-3 and 19-4,
The correction signal QC is multiplied by the multiplier 19-3, and the correction signal IC is multiplied by the multiplier 19-4.

From the output of the multiplier 19-1 to the multiplier 19-4
Is subtracted in the adder 19-5 to obtain the adder 19-
The output from 5 is supplied to the latch circuit 19-7, and the output of the adder 19-5 is latched in the latch circuit 19-7 by the strobe pulse N7 having a frequency of 2fsc, which is obtained by dividing the oscillation output of the crystal oscillator 8 by two. The output is sent to the multiplexer 19-9. The output of the multiplier 19-2 and the output of the multiplier 19-3 are added by the adder 19-6,
The output from the adder 19-6 is supplied to the latch circuit 19-8, the output of the adder 19-6 is latched in the latch circuit 19-8 by the strobe pulse N7, and the latched output is sent to the multiplexer 19-9. . The generation timing of the strobe pulse N7 is shown by an arrow in FIG.

The multiplexer 19-9 is a latch circuit 19
It has the function of inverting the sign of the output from -8 and inputting it.
Moreover, the oscillation output (frequency 4 fsc) of the crystal oscillator 8 is supplied to the multiplexer 19-9 as a clock pulse, and the latch output of the latches 19-7 and 19-8 is 4 f.
It is multiplexed by the oscillation output of sc.

Therefore, the output of the adder 19-5 and the output of the adder 19-6 are demodulation color difference of the demodulation axis (RY) axis in which the phase is not shifted as shown in Formula 2 for each cycle 1 / (2fsc). The demodulation color difference signal output of the demodulation axis (BY) axis whose phase is not shifted from the signal output F (RY) shown in Expression 3 {-FI (B-
Y)} and the demodulation color difference signal output {FI (RY)} of the demodulation axis (R-Y) axis shown in Expression 4 and the phase shown in Expression 5 in which the phase is not shifted ( It becomes a pair of the demodulated color difference signal output {-F (BY)} on the (BY) axis, and the value of the expression 2 and the value of the expression 4 are input to the latch circuit 19-7 at a cycle of 1 / (2f).
sc), and the value of the equation 3 and the value of the equation 5 are latched by the latch circuit 19-8 every cycle 1 / (2fsc).

[0042]

[Equation 2]

[0043]

[Equation 3]

[0044]

[Equation 4]

[0045]

[Equation 5]

Demodulation color difference signal output [-{FI (BY)}] of the demodulation axis (BY) axis whose phase is not shifted and demodulation color difference signal of the demodulation axis (RY) axis whose phase is not shifted Output [F
(RY)] is inverted at the time of input to the multiplexer 19-9, and as a result, the demodulation axis (BY) axis whose phase is not shifted from the multiplexer 19-9 every 1 / (4 fsc). Demodulated color difference signal output [FI (BY)] of
Demodulation color difference signal output [F (RY)] of demodulation axis (R-Y) axis where phase is not shifted, demodulation axis (B where phase is not shifted)
-Y) axis demodulation color difference signal output [F (BY)] and demodulation axis (RY) axis non-shifted demodulation color difference signal output [FI (RY)] are sequentially output in this order. Sent out. The order of the color difference signals corrected in this way is the multiplexer 1.
After being rearranged and modulated by 9-9, the output from the multiplexer 19-9 is supplied to the D / A converter 20 and converted into an analog color signal.

FIG. 8 is a vector diagram for explaining the operation of the above-described embodiment. The phase of the demodulated color signal can be expressed as shown in FIG. If the color signal without jitter is demodulated on the regular demodulation axis, the original signal F (B-
Y) and F (RY) are demodulated. However, in the case of a color signal having jitter on the time axis, the sampling clock deviates from the original demodulation axis. In this embodiment, since there is a jitter of the phase angle θ, the demodulation axis deviates from the regular demodulation axis by θ. Therefore, the angle θ at which the demodulation axis deviates from the normal demodulation axis when there is jitter as described above is obtained, and the value of sin θ is
It can be corrected from the value of cos θ as shown in Expressions 2 to 5.

Here, in FIG. 5, the broken line indicates the (BY) carrier, the alternate long and short dash line indicates the (RY) carrier, and the {(BY) demodulation axis} and {-(BY) demodulation. axis},
The description of {(RY) demodulation axis} and {-(RY) demodulation axis} is shown by omitting the description that the phase is deviated by θ. (BY), demodulation axis with a phase shift of θ- (BY), demodulation axis with a phase shift of θ (R-
Y), which means the demodulation axis − (R−Y) whose phase is deviated by θ.

The demodulation phase correction circuit 17 also demodulates and corrects the phase of the color burst signal. Now, the correction at the point A in FIG. 5 may be obtained by calculating (RY), and assuming that P = 100 and the phase angle θ is 30 degrees, (Equation 2) F (RY) = Acosθ−Bsinθ = 50 × 0.866-86.6 × 0.5 = 0. Here, A is Psin 30 ° (= 50) and B is Pcos 30 ° (= 86.6).

The correction at point B in FIG. 5 is {-(B
-Y)} is obtained (see Expression 3) -FI (BY) = Asin θ + B cos θ = 50 × 0.5 + 86.6 × 0.866 = 100, and it is confirmed that Equations 2 and 3 are correct. I understand. Similarly, it is understood that the equations 4 and 5 are also correct.

In the above-described embodiment of the present invention, the dividing / cumulative adding circuit 15 and the dividing circuit 21 and the cumulative adder 2 are provided.
Although the case where one set of 3 and the division circuit 22 and one set of the cumulative adder 24 are provided is illustrated, instead of this, one set of the division circuit 21 and the cumulative adder 23 is provided, and the divider 14- 1, the value of tan θ is supplied to the dividing circuit 21, the address of the memory 14-2 is designated by the output of the cumulative adder 23, the value of cos θ is read from the memory 14-2, and the output of the cumulative adder 23 is output. And the value of cos θ read from the memory 14-2 are multiplied by the multiplier 14-3,
The value read from the memory 14-2 is supplied to the multipliers 19-1 and 19-3 instead of the correction signal QC, and the multiplier 1
The multiplier 19 outputs the multiplication output of 4-3 instead of the correction signal IC.
-2 and 19-4 may be supplied. In this case, the timing of reading the value of cos θ from the memory 14-2 is as follows:
It is necessary to read in synchronization with the change of + Δ (N-1) / N}.

From the memory 14-2 in this case,
The reading timing of the value of sθ can be specifically set as follows. One horizontal scanning period corresponds to 910 clocks when converted by a clock having a frequency of 4fsc.
This clock is divided into N equal parts, and immediately after the output data of the divider 14-1 changes, the value of cos θ is first read from the memory 14-2, then after 910 / N clocks, and then after 910 / N clocks. read out. In this way, the data up to 910 (N-1) / N is finally read at the same time interval, and then the output data of the divider 14-1 changes again, and the above operation is repeated and read.

[0053]

As described above, according to the time base correction apparatus of the present invention, the difference between the time base fluctuation value of the color burst signal in the immediately preceding horizontal scanning period and the time base fluctuation of the color burst signal in the current horizontal scanning period. Is evenly divided into
The time-axis variation value of the color burst signal in the immediately preceding horizontal scanning period is added to the time-axis variation value of the color burst signal that is evenly divided, and the added time-axis variation value is used as the time-axis correction value for each addition. I tried to correct the axis.
Therefore, the time-axis correction based on the time-axis variation of the two horizontal scanning periods including the time-axis variation value of the color burst signal in the immediately preceding horizontal scanning period is performed a plurality of times during one horizontal scanning period, and the conventional one horizontal scanning period is performed. In comparison with the time axis correction for each horizontal scanning period based on the time axis fluctuation value detected in step 1, the optimum time axis correction is performed in any part of one horizontal scanning period, and the time axis fluctuation within one horizontal scanning period is performed. There is an effect that the time axis correction approximately corresponding to is performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a time axis corrector according to the present invention.

FIG. 2 is a block diagram showing a configuration example of a phase angle detection circuit in an embodiment of a time axis correction device according to the present invention.

FIG. 3 is a block diagram showing a configuration example of a division / cumulative addition circuit in one embodiment of the time axis correction device according to the present invention.

FIG. 4 is a block diagram showing a configuration example of a demodulation phase correction circuit in an embodiment of a time axis correction device according to the present invention.

FIG. 5 is a timing chart for explaining a phase difference in one embodiment of the time axis correction device according to the present invention.

FIG. 6 is a timing chart for explaining a demodulated color difference signal in one embodiment of the time axis correction device according to the present invention.

FIG. 7 is a schematic diagram for explaining the operation of the division / cumulative addition circuit in one embodiment of the time axis correction device according to the present invention.

FIG. 8 is a vector diagram for explaining phase correction in one embodiment of the time axis correction device according to the present invention.

FIG. 9 is an explanatory diagram of an operation of the conventional time axis correction device.

[Explanation of symbols]

 6 A / D Converter 7 Memory 8 Crystal Oscillator 9 Y / C Separation Circuit 10 Phase Angle Detection Circuit 12, 13, 23 and 24 Cumulative Adder 15 Division / Cumulative Addition Circuit 17 Demodulation Phase Correction Circuit

Claims (2)

[Claims] 1. A color burst signal extracting means for extracting a color burst signal from a digitized composite video signal which is sampled and A / D converted by a sampling pulse synchronized with a horizontal synchronizing signal in the composite video signal, and the extracted color. Detecting means for detecting the time-axis variation value of the burst signal, and calculating the difference between the time-axis variation value of the color burst signal in the immediately preceding horizontal scanning period and the time-axis variation value of the color burst signal in the current horizontal scanning period. Calculating means for equally dividing the difference value into a plurality of values, and cumulatively adding the uniformly divided difference value, and for each cumulative addition, the cumulative addition value is used as a time axis variation value of the color burst signal in the current horizontal scanning period. And a cumulative addition means for performing addition, and the time axis correction is performed using the cumulative addition output at each addition time point of the cumulative addition means as the time axis correction value. Time base correction apparatus according to claim. 2. The time axis correction device according to claim 1,
The detecting means is a detecting means for detecting a phase difference between a reference clock pulse having the same frequency as the sampling pulse synchronized with the horizontal synchronizing signal and containing no jitter, and the extracted color burst signal. Correction device.