JPH07283235A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To enable an FET to be reduced in characteristic change with temperature and enhanced in reliability so as to provide a high-performance and high- output amplifier or the like provided with the FET. CONSTITUTION:The gate fingers 101 of a comb-like gate are set short in length near the center of a gate finger pattern and long near the ends. Or, pitches of the gate fingers 101 are made long at the center and short at the ends.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field-effect transistor, and more particularly to a field-effect transistor which exhibits less characteristic deterioration under severe conditions such as high voltage, high current or high temperature operation, and an amplifier using the same.

[0002]

2. Description of the Related Art FET (Field Effect) with a comb-shaped gate structure
Transistor) is a conventional example of, for example, gallium arsenide devices and circuits.
(GaAs DEVICES AND CIRCUITS) (Michael Shur, PLENUM
PRESS, 1987) 412. The gate electrodes of these conventional comb gate FETs are composed of uniformly distributed gate fingers as shown in FIG.

[0003]

In a high-power FET, the element itself is heated by a high applied voltage and a large induced current, resulting in characteristic deterioration and, in some cases, destruction. A first object of the present invention is to improve the element characteristics and the reliability thereof by increasing the temperature at which the element characteristic deterioration starts. The second purpose is to obtain a high-performance amplifier.

[0004]

The first object is achieved by making the gate finger lengths or densities of the comb-type gate FET nonuniform, and the second object is achieved by using such an FET. This can be achieved by building a circuit.

[0005]

[Function] A typical high output amplifier circuit using an FET is shown in FIG.
Shown in. In such a circuit, when the external temperature rises, the element characteristics such as the threshold voltage and the gate leakage current change, so that a current as indicated by an arrow 209 in the drawing starts to flow. This current causes the potential of the gate to change more and more, resulting in an increase in drain current, that is, thermal runaway. This thermal runaway is more likely to occur as the temperature dependence of the threshold voltage and the gate leakage current increases. On the other hand, the temperature distribution inside the element is higher in the central portion of the comb-shaped gate as shown in FIG. This is because heat is more likely to be accumulated in the central portion of the element due to the heat radiation property and the temperature is likely to rise. Therefore, the current density tends to increase toward the center of the device. On the other hand, if the gate finger distribution shown in FIG. 1 is given,
Since the current density near the central portion originally becomes small, the heat generation amount becomes small. This prevents only the central part from getting hot and thermal runaway is less likely to occur.

[0006]

Embodiments of the present invention will be specifically described below with reference to the drawings. In the following description, AlG is used as the material description.
aAs is one in which some Ga atoms in GaAs are replaced by Al, InGaAs is one in which some Ga atoms in GaAs are replaced by In, and InAlAs is AlA.
It means a part of Al atoms in s replaced by In.

(Embodiment 1) FIG. 6 shows a sectional view of Embodiment 1 of the present invention. First, MB on the semi-insulating GaAs substrate 1.
Undoped GaAs by E (molecular beam epitaxy) method
Layer (thickness: 500 nm) 2, undoped AlGaAs
(Al composition: 0.25, thickness: 100 nm) layer 3, undoped GaAs spacer layer (thickness: 10 nm) 4, n-G
aAs channel layer (thickness: 100 nm, Si concentration: 2 ×
10 ¹⁷ / cm ³ ) 5, n-GaAs layer (thickness: 80 nm,
Si concentration: 2 × 10 ¹⁷ / cm ³ ) 6, undoped AlGa
An As (Al composition: 0.25, thickness: 5 nm) layer 7 is grown, and finally an n-GaAs cap layer (Si concentration: 7 ×) is grown.
10 ¹⁸ / cm ³ , thickness: 160 nm) 8 is deposited.

After element isolation is performed by mesa etching, an insulating film is deposited and a source electrode 51 and a drain electrode 52 are formed by lift-off. AuGe / Mo / Au is used as the source / drain electrode material, and heat treatment (400 ° C., 5 minutes) is performed in a nitrogen atmosphere after the material deposition. As the lift-off mask, one having an opening formed in an insulating film by a normal photolithography process is used. Also,
The opening of the insulating film is side-etched by wet etching to have a shape that facilitates lift-off. Furthermore, n-
The GaAs cap layer 8 is etched by wet etching to about 40 nm.

Next, a desired portion is opened by a normal photolithography process, and the insulating film is removed by dry etching. Next, the n-GaAs layer 8 is removed by dry etching. At this time, side etching is performed by isotropic etching, and a region larger than the opening is removed by etching. Next, the gate length is 0.5μ
m, the gate electrode 53 with a gate width of 12 mm is undoped A
It is formed on the lGaAs layer 7 by lift-off. Mo / Pt / Au is used as the gate electrode material.

In this way, the FE having the structure shown in FIG.
Realized T. Also, the comb-shaped gate pattern at this time is
As shown in Fig. 1, the gate finger length is short in the central part and becomes longer toward the end, and the number of gate fingers is 6
Zero, the average gate finger length was 200 μm.

The device according to this embodiment has a threshold voltage of -3.
V, saturation output 28 dBm, efficiency 71%, thermal runaway start temperature 180 ° C, showing high performance.

In this embodiment, the thickness of the undoped AlGaAs spacer layer 7 is set to 5 nm, but good results were obtained in the range of 2 to 10 nm. Further, the ionized impurity concentration of the n-GaAs layers 6 and 7 is not limited to the above and is 1 × 10 ^16.
Good results are obtained in the range of up to 5 × 10 ¹⁷ / cm ³ .

The conditions in this embodiment may be as follows. Similar results can be obtained by using an epitaxial crystal growth method in the manufacturing process, instead of the MBE method, in which the growth can be controlled in atomic layer units, such as the MOCVD method. Further, the cap layer 8 is not limited to GaAs, but is made of a material such as InGaA that easily makes ohmic contact.
You may use s etc. In addition, undoped Al directly under the gate
The GaAs layer 7 should have a pressure resistance of 1 × 10
You may use n-AlGaAs of ¹⁸ / cm < ³ > or less. Al
Although the Al composition of the GaAs layers 3 and 7 was 0.25,
Similar results can be obtained by using a value of about 0.15 to 0.4. Although GaAs is used for the channel layer 4, it is 0.1
To In of about 0.4 to about 0.4, the thickness may be such that dislocations do not enter, and the material is not limited to GaAs but may be GaAsSb or a combination of a plurality of semiconductor layers.

The substrate material is not limited to GaAs, but In
You may use P etc. When an InP substrate is used, InAlAs having an In composition of 0.3 to 0.6 is used instead of the AlGaAs layer, and In composition is 0.4 instead of the GaAs layer.
Good results are obtained with ~ 0.7 InGaAs. In addition, although an example of an N-channel field effect transistor is shown in this embodiment, good results can be obtained with a P-channel. In this case, this is achieved by making the N-doped layer a P-doped layer. In addition, although the FET including the ionized impurities in the channel is described in this embodiment, the present invention is not limited to this.
It goes without saying that good results can be obtained even when applied to other heterojunction elements such as HEMTs, reverse HEMTs, and doped channel FETs with a carrier supply layer.

(Embodiment 2) FIG. 7 shows a sectional view of Embodiment 2 of the present invention. First, an insulating film 50 is vapor-deposited on the semi-insulating GaAs substrate 1, and openings for source and drain electrode regions are provided at desired positions by a normal photolithography process. Next, Si ion implantation (irradiation dose: 3
× 10 ¹³ / cm ² , accelerating voltage: 125 kV). Next, an opening for forming a channel region is provided at a desired position by a photolithography process, and Si ion implantation is performed.
(Irradiation amount: 5 × 10 ¹² / cm ² , accelerating voltage: 80 kV) and M
g ion implantation (irradiation amount: 5 × 10 ¹¹ / cm ² , accelerating voltage: 150 kV) is performed. Further, an opening for the N ′ layer is provided at a desired position by a photolithography process, Si ion implantation (irradiation amount: 1 × 10 ¹² / cm ² , accelerating voltage: 200 kV) is performed, and heat treatment is performed in an arsine atmosphere (850 C, 20 minutes).

Next, the source electrode 51 and the drain electrode 52
Are formed by lift-off. AuGe / Mo / Au is used as the source / drain electrode material, and heat treatment (400 ° C., 5 minutes) is performed in a nitrogen atmosphere after the material deposition. As the lift-off mask, one having an opening formed in an insulating film by a normal photolithography process is used. The opening of the insulating film is side-etched by wet etching to have a shape that facilitates lift-off. Next, a desired portion is opened by an ordinary photolithography process, and the insulating film is removed by dry etching. Next, a gate electrode 53 having a gate length of 1 μm and a gate width of 12 mm
Are formed by lift-off. T for gate electrode material
i / Pt / Au is used. In this way, the FET having the structure shown in FIG. 7 was realized. In addition, the comb-shaped gate pattern at this time has a distribution in which the gate finger length is short in the central part and is longer toward the ends as shown in FIG. 1, the number of gate fingers is 60, and the average gate finger length is 200.
μm.

The device according to this embodiment has a threshold voltage of -3.
V, saturation output 25 dBm, efficiency 78%, thermal runaway start temperature 185 ° C, showing high performance.

The Si and Mg ion implantation conditions and annealing conditions, each electrode material, and the like in this embodiment are not limited to the above, and may be changed to appropriate conditions according to desired FET characteristics. Further, the N'layer and the Mg implanter may be omitted. Further, a p-type buffer region may be provided by implanting P-type ions such as Mg ions and Be ions with higher energy than that for channel formation. Also,
Although the examples of the N-channel field effect transistor are shown in these embodiments, good results can be obtained even in the P-channel.
In this case, this is achieved by making the N-doped layer a P-doped layer.

The conditions in the first and second embodiments may be as follows. Ti / Pt / for the gate metal material
Au was used, but not limited to this, Al, Ti / Al, WS
You may use i etc. Further, the source and drain electrode materials may be Ti / Au or the like. The process also employs the method of forming the gate by lift-off, but the method is not limited to this, and the method of forming the gate first and forming the implantation region in the self-alignment may be adopted. Total gate width and average gate finger length are 12mm and 200μm, respectively
However, the length is not limited to this, and may be a length according to the purpose. Further, instead of providing the gate finger length distribution, a similar effect can be obtained with a structure in which the density distribution changes as shown in FIG. Further, by using these in combination, the same effect can be obtained while reducing the chip area.

(Embodiment 3) FIG. 5 shows a circuit diagram of a high output amplifier according to Embodiment 3 of the present invention. FE described in Examples 1 and 2
T is formed on the semiconductor substrate together with the matching circuit using the line 207, the resistor 206, and the capacitor 208. The high-power amplifier thus obtained has the drain voltage and drain current of the FET 100 of 4.7 V and 10 mA, the input signal power of 100 mW, and the frequency of 800 MHz, respectively.
Good performance with an output of 1.7 W and a thermal runaway start temperature of 175 ° C was obtained.

In this embodiment, an example of a so-called monolithic IC in which the matching circuit is on the same substrate is shown, but a hybrid IC which is slightly deteriorated in performance but easy to manufacture, that is, a matching circuit is not on the same substrate. But good results are obtained. Further, although a circuit having a frequency band of 800 MHz is described, good characteristics were obtained in other frequency bands by changing the matching circuit. In addition, good characteristics were obtained even in applications with smaller operating current and operating voltage, such as those requiring low power consumption operation such as car phones and mobile phones. In this case, the cell size required to obtain the same characteristics as those achieved by using the conventional element could be reduced to half or less. This is because the element obtained by the present invention has better performance than the conventional element, so that a high-performance amplifier can be obtained even if the circuit is configured with a small number of elements. Further, the FET of the present invention may be used for other circuits.

[0022]

According to the present invention, it is possible to obtain a highly reliable FET having a small change in characteristics with respect to temperature changes, and a high output amplifier or the like using the FET has improved performance.

[Brief description of drawings]

FIG. 1 is a plan structure view of a comb-shaped gate of a field effect transistor of the present invention.

FIG. 2 is a plan view of a comb-shaped gate of a conventional field effect transistor.

FIG. 3 is a diagram showing heat distribution in a conventional field effect transistor.

FIG. 4 is a plan structure view of a comb-shaped gate of the field effect transistor of the present invention.

FIG. 5 is a circuit diagram of a high power amplifier.

FIG. 6 is a cross-sectional structure diagram of the field effect transistor of Example 1 of the present invention.

FIG. 7 is a sectional structural view of a field effect transistor of Example 1 of the present invention.

[Explanation of symbols]

1 ... Semi-insulating GaAs substrate, 2 ... Undoped GaAs buffer layer, 3 ... Undoped AlGaAs channel layer, 4
... undoped GaAs spacer layer, 5 ... n-GaAs channel layer, 6 ... n-GaAs layer, 7 ... undoped AlG
aAs layer, 8 ... n-GaAs cap layer, 11 ... n-ohmic region, 12 ... n-channel region, 13 ... N ′ region, 50 ... Insulating film, 51 ... Source electrode, 52 ... Drain electrode, 53 ... Gate electrode , 101 ... Gate finger,
102 ... Gate pad, 103 ... Temperature rising region, 200
... FET, 201 ... Ground, 202 ... Input terminal, 203
... output terminal, 204 ... FET gate voltage terminal, 205
... FET drain voltage terminal, 206 ... resistance, 207 ...
Strip line, 208 ... Capacitor.

Claims (7)

[Claims] 1. A field effect transistor having a comb-shaped gate electrode structure, characterized in that the length of each comb-shaped gate is not uniform. 2. The field effect transistor according to claim 1, wherein the length of each comb-shaped gate is short at the center of the pattern and long at the end. 3. A field effect transistor having a comb-shaped gate electrode structure, wherein the density of gate fingers is non-uniform. 4. The field effect transistor according to claim 3, wherein the density of the gate fingers is sparse at the center of the pattern and dense at the end of the pattern. 5. The active region of the field effect transistor is formed by ion implantation.
5. The field effect transistor according to any one of 4 to 4. 6. The field effect transistor according to claim 1, wherein the active region of the field effect transistor is formed of a heterojunction compound semiconductor crystal. 7. A power amplifier using the field effect transistor according to any one of claims 1 to 6.