JPH0728278B2 - Sync signal extraction circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync signal extraction circuit for extracting a sync signal included in a received digital signal in digital transmission, and more particularly to a sync signal from a digital signal with a lot of jitter. The present invention relates to a synchronization signal extraction circuit suitable for extracting the signal.

[Conventional technology]

The conventional sync signal extraction circuit has a digital logic circuit configuration.
A PLL circuit is adopted, and as described in Japanese Patent Laid-Open No. 60-72345, the phase comparison output of the input signal and the synchronization signal is judged by a binary value (+1 or -1) of phase lead or phase lag, It is designed to control the phase of the synchronization signal. In other words, the phase comparator judges the phase difference between the extracted sync signal and the change point of the input signal by judging whether the phase of the sync signal is ahead of or behind the phase of the input signal. It is not taken into account whether it is late or late.

[Problems to be solved by the invention]

In order to accurately judge "0" and "1" of the input signal, the third
As shown in the figure, the sync signal A6 synchronized with the input signal A1 is extracted by the sync signal extraction circuit, and the sync signal A6 is extracted from the sync signal A6.
It is necessary to obtain the timing signal A7 indicating the bit center position of and to make the determination at this timing signal position.

When the input signal A1 is actually input to the sync signal extraction circuit, it may be a signal A2 containing a jitter that changes at a point shifted forward or backward by a certain fixed amount from the normal change point. . In this case, the synchronization signal A4 is the signal A3 whose falling timing comes to the change point which is shifted forward of the original input signal A1.
Then, it becomes indefinite in the middle of the signal A5 whose falling timing coincides with the change point deviated to the rear. In the conventional sync signal extraction circuit, if the number of times of jitter in each of the leading direction and the delaying direction is the same within a certain time, the output of the phase comparator will be no matter where the signal A4 is between the signals A3 and A5. It is smoothed and canceled by the up-down counter, and the phase of the sync signal is not corrected. This situation will be described with reference to FIG.
For example, it is assumed that a jitter occurs in the transmission signal CO during its transmission and a reception signal (input signal) C1 is obtained as shown in the figure. In this case, if the probability that the same change point appears at t ₁ is almost equal to the probability that it appears at t ₂ , in such a case, the fall timing is between t ₁ and t ₂ Positioned sync signal C3 (The duty ratio of sync signal C3 is 50
%), The received signal C1 is punched out at the rising timing, so that the data is accurately received from the specific area (hatched intersection area) in the received signal C1. However, in the case of the conventional technique using the up-down counter, if the phase shifts to a position such as the sync signal C2, the sync signal C2 is not phase-corrected to the sync signal C3, and the phase state remains unchanged. You will be able to
In this phase state, the specific area is not punched out depending on the data punching timing by the synchronization signal C2, and the data cannot be accurately received from the received signal C1 whose change point is deviated to t ₂ . In other words, the conventional synchronizing signal extraction circuit does not consider the case where the phase of the change point is shifted and dipolarized due to the jitter. Therefore, there is a region where the phase of the synchronization signal is indefinite, and if the range is large, the center position of the bit of the input signal cannot be obtained accurately. Therefore, there is a problem that the synchronizing signal extraction circuit using the PLL having the digital circuit configuration can be used only when the jitter of the input signal is small.

The object of the present invention is to synchronize the input signal with a regular change point (change point when no jitter is included), even for an input signal in which the phase of the change point is divided into two poles because it contains large jitter. Another object of the present invention is to provide a synchronizing signal extracting circuit having a digital logic circuit configuration capable of extracting the synchronizing signal.

[Means for solving problems]

The above-mentioned objects are: a change point detection circuit for detecting a change point of a digital input signal; a frequency division variable frequency dividing circuit for counting and dividing a reference clock pulse; and a change point detected by the change point detection circuit. An addition accumulating circuit that adds and accumulates the frequency dividing circuit by regarding the count value as a binary number with a sign, and a dividing circuit of the frequency dividing circuit when the accumulated value of the addition accumulating circuit exceeds a positive or negative constant value. This is achieved by forming a synchronizing signal extraction circuit by providing a control circuit for changing the frequency and correcting the output phase of the frequency dividing circuit, and using the frequency divided output of the frequency dividing circuit as the synchronizing signal.

[Action]

The change point detection circuit generates a pulse when the input signal changes, and the addition / accumulation circuit adds the count value of the frequency division circuit when the output pulse of the change point detection circuit occurs to the accumulated value up to that point. Hold the sum. The control circuit outputs a phase control signal to the frequency dividing circuit when the value held in the addition / accumulation circuit exceeds a positive or negative constant value, and
Initialize the cumulative value of the adder / cumulative circuit. The divider circuit divides the clock and outputs the synchronizing signal, but when the phase control signal from the control circuit is received, the dividing number is increased or decreased to advance or delay the phase of the synchronizing signal.

As a result, the synchronizing signal output from the frequency dividing circuit is synchronized with the average phase of the input signal. Therefore, even if the input signal contains large jitter, the phase of the synchronization signal is fixed at a position where the phase difference from the input signal is zero on average. Since the average phase position of the change point and the normal change point of the input signal usually coincide with each other, the phase of the synchronization signal is phase-locked with the normal change point position of the input signal.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram of a sync signal extraction circuit according to an embodiment of the present invention.

In this embodiment, the change point detection circuit is a D flip-flop 9
And an exclusive OR gate 10, and the divider circuit is a divider 5
And D flip-flop 12 and the adder / accumulator circuit is composed of an adder 2 and a register 3.

The input signal B1 input from the signal input terminal 6 is applied to the D input terminal of the D flip-flop 9, and the exclusive OR of the Q output of the D flip-flop 9 and the input signal B1 is gated.
It is taken at 10 and is supplied to the L input of the register 3 as the change point signal B2. Reference clock B3 supplied to clock input terminal 7 (frequency approximately 16 times the bit rate of input signal B1)
Are input to the clock terminals CK of the D flip-flops 9 and 12, the frequency divider 5 and the register 3.

The output control signal of the control circuit 4 described later is input to the frequency divider 5.
By inputting to A, B, C, D, the reference clock B3 is 1/15,
Divide 1/16, 1/17. That is, the frequency divider 5 outputs a pulse to the C ₀ terminal when the count value is “15” (“−1” when the most significant bit is regarded as a code bit). This pulse is delayed by one clock at the D flip-flop 12 and transmitted to the L input of the frequency divider 5. When the L input is "1", the frequency divider 5 resets the count value to the input value of A, B, C, D at the next clock. In this case, the L input becomes "1" when the count value is "0", so if the input value of A, B, C, D is "1" at this time, set the count value to "1" at the next clock. , Becomes a normal 1/16 divider circuit. When the input values of A, B, C and D are "0", the state where the count value is "0" continues twice and the circuit becomes a 1/17 frequency divider. When the input value of A, B, C, D is "2", the state of count value "1" disappears and the circuit becomes 1/15 frequency divider.

The adder 2 adds the count value B4 of the frequency divider 5 to the cumulative value B5 of the register 3 every time the change point signal B2 is input to the register 3, and the register 3 holds the result as a new cumulative value B5. To do. This accumulated value B5 is transmitted to the control circuit 4.
The adder 2 and the register 3 have an 8-bit configuration, and the count value B4 of the frequency divider 5 is regarded as a 4-bit signed binary number and is sign-extended to 8 bits and input to the adder 2.

The control circuit 4 normally outputs "1" as the control data B6, and the frequency divider 5 has the A, B, C, D input values of "1", so 1/1
Operates as a 6-divider. However, when the cumulative value B5 exceeds a positive constant value (for example, 64), "0" is output as the control data B6 and the frequency divider 5 is operated as a 1/17 frequency divider. On the other hand, when the value is below the negative constant value (eg, −63), “2” is output as the control data B6 and the frequency divider 5 is set to 1/15.
Operate as a frequency divider. When "0" or "2" is output as the control data B6, the divider operates once as a 1/15 divider or a 1/17 divider, then clears register 3 and sets the control data. Set B6 back to “1”.

The highest bit B7 of the counter value B4 output from the output Q _D of the frequency divider 5 is output to the output terminal 8 through the delay element 1,
The synchronization signal B8 is obtained.

FIG. 2 is a timing chart showing the operation of the sync signal extraction circuit shown in FIG.

Jitter is added to the signal while the transmission signal B0 is transmitted through the transmission path, and the change point is bipolarized by the jitter. Input signal B1
Is input to the input terminal 6. At this time, the change point signal
B2 may come out at the timing of t _{1 or at} the timing of t ₂ . When the change point signal B2 appears at the timing of t ₁ , “−2” is added to the register 3, and when the change point signal B2 appears at the timing of t ₂ , “+2” is added to the register 3. Will be taken. If the probability of occurrence of the changing point signal B2 at t ₁ and t ₂ are the same, the cumulative value B5 register 3 does not exceed +64 or -63. When the phase of the count value B4 is shifted by one clock, the count value becomes B4 '. In the case of the conventional technique using the up / down counter, the phase difference detection is only a binary value of advance or delay, so that the up / down counter does not overflow and the phase is not corrected. In the present embodiment, the count values B4 ′ at t ₁ and t ₂ are “−1” and “+3” respectively, the cumulative value of the register 3 finally exceeds +64, and the frequency divider 5 only once. It operates as a 1/17 frequency divider, the phase of count value B4 'is returned after one clock, and the position becomes normal position B4. Count value B4
When the phase of is shifted behind, similarly, the register value falls below −63, the frequency divider 5 operates as a 1/15 frequency divider once, and the phase of the count value B4 is changed. to correct. In this way, the phase of the count value B4 has a substantially constant phase relationship with the original transmission signal.

〔The invention's effect〕

According to the present invention, it is possible to accurately extract the synchronization signal only by the logic circuit, even for the input signal in which the phase of the change point is divided into two poles due to jitter.

[Brief description of drawings]

FIG. 1 is a block diagram of a synchronizing signal extraction circuit according to an embodiment of the present invention, FIG. 2 is an operation timing chart of the circuit shown in FIG. 1, FIG. 3 is a timing chart of a conventional circuit, and FIG. 4 is a conventional circuit. It is a figure for demonstrating the malfunction of. 2 ... Adder, 3 ... Register, 4 ... Control circuit, 5 ...
... Divider, 6 ... Signal input terminal, 7 ... Reference clock input terminal, 8 ... Sync signal output terminal, 9, 12 ... D flip-flop, 10 ... Exclusive OR gate.

Claims (1)

[Claims] 1. A sync signal extraction circuit for extracting a sync signal from a digital signal supplied as serial data and outputting the sync signal, a change point detection circuit for detecting a change point of the digital signal, and counting and dividing a reference clock pulse. A frequency division variable frequency dividing circuit, and an addition accumulation circuit that adds and accumulates the count value of the frequency division circuit when the change point is detected by the change point detection circuit as a signed binary number. A control circuit is provided for correcting the output phase of the frequency dividing circuit by changing the frequency dividing number of the frequency dividing circuit when the cumulative value of the adding / cumulating circuit exceeds a fixed positive or negative value. The sync signal extraction circuit is characterized in that the frequency division output of is output as a sync signal.