JPH07282580A - Power consumption reducing system in dram - Google Patents

Abstract

PURPOSE:To reduce the power consumption of a DRAM by decreasing the number of bits being in a level 1 of data to be stored in the DRAM. CONSTITUTION:At the time of writing data in a DRAM 5, a data deciding part 2 decides whether the number of bits being in a level 1 of data inputted to data busses 1 exceeds the majority of the number of all bits of input data or not to output the result to a selection part 4 and the DRAM 5. The selection part 4 selects inverted data from a data inverting part 3 when the decision result exceeds the majority and selects input data from the data busses 1 when the result is less than the majority to output them to the DRAW 5. At the time of reading data from the DRAM 5, the selection part 4 selects the inverted data from the data inverting part 3 when the decision result exceeds the majority and selects input data from the DRAM 5 when the result is less than the majority to output them to the data busses 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM power consumption reduction method, and more particularly to a DRAM power consumption reduction method for reducing power consumption by reducing the number of level 1 bits stored in the DRAM.

[0002]

2. Description of the Related Art Conventionally, as a method for reducing power consumption in this type of DRAM, for example, JP-A-3-
In the "semiconductor memory device" disclosed in Japanese Patent No. 58381, a memory array including word lines and data lines and DRAMs arranged in a grid pattern at intersections of the word lines and data lines, and a unit provided corresponding to the data lines. A sense amplifier including an amplifier circuit is provided, and only a unit amplifier circuit corresponding to a specified address is brought into an active state, thereby reducing the operating current of the sense amplifier.

[0003]

In the DRAM, "1" is obtained by amplifying the potential change of the data line due to the charging / discharging of the minute charge to the internal memory cell by the internal sense amplifier.
The memory operation is performed by storing "0".

Therefore, power is consumed to hold the level 1 bit. Therefore, the power consumption of the DRAM increases as the number of level 1 bits stored in the DRAM increases.

However, in the above-described conventional semiconductor memory device, there is no effective countermeasure against the increase in the number of level 1 bits stored in the DRAM, and the power consumption of the DRAM increases as the number of level 1 bits stored increases. However, there was a problem in that

It is an object of the present invention to reduce the number of level 1 bits of data stored in DRAM by reducing D
It is an object of the present invention to provide a power consumption reduction method for a DRAM that reduces the power consumption of the RAM.

[0007]

According to the present invention, it is determined whether or not the number of level 1 bits of input data exceeds a majority of the total number of bits of this input data, and the determination result is output. A data determination unit, a data inversion unit that inverts the input data and outputs inverted data, and a selection unit that selects one of the input data and the inversion data according to the determination result of the data determination unit. Prepare, D
A method for reducing power consumption in a DRAM is obtained in which the RAM has a bit width for storing all bits of the data from the selection unit and the bits of the determination result of the data determination unit.

Further, when the selecting section outputs level 1 as a result of the data judging section judging that the number of bits of level 1 of the input data exceeds a majority of the total number of bits of the input data, the selecting section outputs the level 1. The inverted data from the data inversion unit is selected and output, and the data determination unit determines level 0 as a result of determining that the number of bits of level 1 of the input data is equal to or less than the majority of the total number of bits of this input data. A method for reducing power consumption in a DRAM is obtained in which the input data is selected and output when output.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a power consumption reduction system in a DRAM of the present invention.

Referring to FIG. 1, this embodiment is a DRAM 5
And a data judging section 2 which judges whether or not the number of level 1 bits of the input data from the data bus 1 or the DRAM 5 exceeds a majority of the total number of bits of the input data and outputs the judgment result. Data bus 1 or DRA
A data inverting section 3 for inverting the input data from M5, and a data bus 1 or D depending on the determination result of the data determining section 2.
A selection unit 4 for selecting either the input data from the RAM 5 or the inversion data from the data inversion unit 3;
The RAM 5 has a bit width for storing the bits of the data from the selection unit 4 and the bits of the determination result of the data determination unit 2.

Next, the operation of this embodiment will be described.

First, at the time of writing data to the DRAM 5, the data judging section 2 determines that the bit number a of level 1 of the data input to the data bus 1 is the total bit number N of the input data.
It is determined whether or not the number exceeds a majority (N / 2), and the result of the determination is level 1 when the number of bits a> majority N / 2, and level 0 when the number of bits a ≦ majority N / 2.
To the selection unit 4 and the DRAM 5.

The data inverting section 3 inverts the level of the data input to the data bus 1 and selects the inverted data from the selecting section 4.
Output to.

The selection unit 4 selects the inverted data input from the data inversion unit 3 when the level 1 is input as the determination result from the data determination unit 2, that is, when the number of bits a> the majority N / 2. Output to DRAM5.

When level 0 is input from the data determination section 2 as the determination result, that is, when the number of bits a ≦ a majority N / 2, the selection section 4 selects the data input to the data bus 1. Output to DRAM5.

The DRAM 5 stores the determination result (level 0 or 1) input from the data determination unit 2 and the selection result data input from the selection unit 4.

Next, at the time of reading data from the DRAM 5, the data judging section 2 outputs the judgment result (level 0 or 1) inputted from the DRAM 5 to the selecting section 4 as it is.

The data inverting section 3 inverts the data input from the DRAM 5 and outputs the inverted data to the selecting section 4.

When the level 1 is input from the data determination unit 2 as the determination result, that is, when the number of bits a> the majority N / 2, the selection unit 4 selects the inverted data input from the data inversion unit 3. Output to data bus 1.

When level 0 is input from the data determination unit 2 as the determination result, that is, when the number of bits a ≦ a majority N / 2, the selection unit 4 selects the data input from the DRAM 5 and selects the data bus. Output to 1.

Next, the effect of this embodiment will be described with reference to FIG.

FIG. 2 is a diagram showing a bit configuration of data stored in the DRAM by comparing the case according to the prior art with the case according to the present invention. The number of bits of the write data is N = 4, that is, the bit number. 0, 1, 2,
3 has a 4-bit configuration.

In FIG. 2, for example, the number of bits of level 1 in write data 1 of "0001" is a = 1, and the number of bits of level 1 in write data 3 is "0011" is a = 2. Number of bits N = 4
Since it is less than 2 which is a majority of the above, the determination result in this embodiment is level 0.

Further, for example, write data 7 "011"
In the case of 1 ″, the number of bits of level 1 is a = 3, and the majority of the total number of bits of input data = 2, so the determination result according to the present invention is level 1.

As shown in FIG. 2, the total number of level 1 bits of the data stored in the DRAM is 32 in the case of the conventional technique, whereas the number of bits of the judgment result is included in the case of the present embodiment. It becomes 25 pieces.

As described above, according to the present embodiment, when the data bus has 4 bits, the total number of level 1 bits can be suppressed to 78% of the conventional level.

[0028]

As described above, according to the present invention, data for determining whether or not the number of level 1 bits of input data exceeds a majority of the total number of bits of the input data and outputting the determination result. The DRAM includes a determination unit, a data inversion unit that inverts input data and outputs inverted data, and a selection unit that selects either the input data or the inversion data according to the determination result of the data determination unit. By having a bit width for storing all the bits of the data from and the bit of the determination result of the data determination unit, the number of bits of level 1 of the data stored in the DRAM is reduced.
This has an effect that an increase in power consumption due to an increase in the number of bits of level 1 can be significantly suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a power consumption reduction method in a DRAM of the present invention.

FIG. 2 is a diagram showing a bit configuration of data stored in a DRAM in comparison with a case according to a conventional technique and a case according to the present invention.

[Explanation of symbols]

 1 Data Bus 2 Data Judgment Section 3 Data Inversion Section 4 Selection Section 5 DRAM

Claims (2)

[Claims] 1. A data determination unit for determining whether or not the number of level 1 bits of input data exceeds a majority of all the bits of the input data and outputting the determination result.
The DRAM includes a data inverting unit that inverts the input data and outputs inverted data, and a selection unit that selects either the input data or the inversion data according to the determination result of the data determination unit. A DRA having a bit width for storing all bits of data from the selection unit and bits of the determination result of the data determination unit.
Power consumption reduction method in M. 2. When the selecting section outputs level 1 as a result of the data judging section judging that the number of bits of level 1 of the input data exceeds a majority of the total number of bits of the input data, the selecting section outputs the level 1. The inverted data from the data inversion unit is selected and output, and the data determination unit determines level 0 as a result of determining that the number of bits of level 1 of the input data is equal to or less than the majority of the total number of bits of this input data. 2. The method of reducing power consumption in a DRAM according to claim 1, wherein the input data is selected and output when output.