JPH0727475B2 - Microprogram verification method and apparatus - Google Patents

Description

The present invention relates to a method and apparatus for verifying a microprogram, and more particularly to a microprogram suitable for source-level verification of a violation of microprogram specification restrictions. The present invention relates to a program verification method and apparatus.

[Prior Art] A conventional microprogram verification method is disclosed in Japanese Patent Laid-Open No. 62-14533.
As described in JP-A No. 2 and JP-A-62-6345, etc.,
By actually giving test data from the outside and operating the microprogram, the validity of the logic of the microprogram is confirmed.

By the way, generally, in order to improve the performance of a computer or the like to be controlled, the microprogram has the following specifications:
Strict restrictions and restrictions are imposed, and the micro instruction setting conditions are defined by the processing timing of the target computer. Therefore, programmers must program with all these specification restrictions in mind. For example, in programming in which a specific microinstruction is executed "immediately after" execution of another specific microinstruction, the logic operates consistently during normal operation of the microprogram, but with the hardware. It may cause a malfunction only when some delay occurs on the interface. for that reason,
Since such programming causes a problem, it is prohibited as a specification restriction in advance.

[Problems to be Solved by the Invention] However, the number of these specification restrictions is small, and
Microprograms are so-called hardware-oriented, and specification limits change according to individual hardware configurations, so it is not always easy for programmers to grasp all of them and write programs, and , Programming while confirming the specifications will reduce programming efficiency.
Further, violation of specification restrictions due to carelessness and misunderstanding of programmers will inevitably occur.

The conventional technique described in the above-mentioned Japanese Patent Laid-Open Publication No. Sho Sho is for verifying an error while the microprogram is actually operating on the target data processing system, and not for verifying at the source level. Also, to run all microprogram sequences, namely,
It is necessary to prepare in advance test data for passing all routes. Further, because the specification restriction violation does not always cause an error during execution, it is not easy to detect the specification restriction violation, and even if the error is detected, it is difficult to identify the specification restriction violation.

An object of the present invention is to provide a microprogram verification method and apparatus capable of efficiently verifying specification restriction violations at the source level for all microprogram sequences.

[Means for Solving the Problems] In order to achieve the above object, a microprogram verification method according to the present invention is a microprogram verification method for verifying that a microprogram is correctly written according to specification restrictions. For the microprogram source to be verified, derive all paths that can be traversed at the time of execution of the microprogram, and for each microstep of this derived path, sequentially, according to the specification limits, that microstep becomes the correct description. It is verified whether or not it is present, and the verification result is output.

As a method for deriving all of the above routes, it is conceivable to obtain a pair of its own address and a branch destination address for each microstep, and obtain an address string for each route based on this address pair information. At this time, for an address pair having a branch destination address of another address pair as a branch source address, a staircase structure address table in which the branch source address of the address pair is associated with the branch destination address of the other address pair is obtained. It is preferable to obtain an address string for each route based on this staircase structure address table.

Further, an address sequence common to each route may be extracted based on the staircase structure address table, a source code table corresponding to this address sequence may be created, and this source code table may be used for verification processing. .

When the description content of each microstep is defined, the description position of the microstep address and the branch destination address may be recognized by referring to the microprogram definition information.

The above-mentioned specification limitation can define the number of steps to be verified in the forward direction or the backward direction for the microstep to be verified as a verification range. In addition, this verification range may include its own microsteps. further,
Specification restrictions are specified obligations that require the description of specific content depending on the content of the verified microstep, and / or
A specification prohibition for prohibiting the description of specific contents depending on the contents of the verified microstep may be included.

It is preferable that the specification restriction that requires verification in the reverse direction be replaced with a condition having a relationship with the specification restriction condition, and verification be performed as a forward verification condition.

Of the microsteps of any path, for the microsteps that have already been verified for other paths,
The verification may be omitted.

A microprogram verification device according to the present invention is a microprogram verification device for verifying that a microprogram is correctly written according to specification limits, and stores microprogram sources and microprogram specification limit information. Means, and route derivation means for deriving from the microprogram source all routes that can be traversed at the time of execution of the microprogram, and each microstep of the derived route is a correct description for the microprogram specification restriction. It is provided with a verifying means for determining whether or not there is any, and an output means for outputting a verification result by the verifying means to an output device.

The apparatus may be provided with means for storing microprogram definition information defining at least the address description position of the microstep.

In the "specification limit" of the present invention, in addition to the above-mentioned essential constraint on the hardware configuration or logical configuration, a limit on the functional specification of the microprogram (for example, "condition code must be set by the end of processing"",
"Even if an interrupt occurs during processing, the contents of the memory and the registers are guaranteed").

[Operation] According to the present invention, specification restriction violation is detected at the source level before execution of a microprogram. As a procedure, first, a route that may pass through the microprogram source at the time of execution is detected. All are derived, and it is checked whether or not the derived route complies with a predetermined specification limit, that is, a verification condition.

All routes can be derived based on this pair of addresses by extracting all pairs of the own address and branch destination address of each microstep from the verification target microprogram source. If the address description position in the microstep is defined as the definition information in order to give flexibility to the description of the microstep, the description position of each address is referenced by referring to the definition information before extracting the address. Recognize. The process of deriving all the routes from the address pairs can be easily performed by converting the address pairs into a staircase structure address table (described later) and then performing the processing based on this table.

In the above verification, the source code of sequentially executed microsteps is extracted along each derived path, and this source code, including the relationship with the source code before and after it, meets the predetermined specification limit. Determine whether or not For each route as a single route without multiple branches, there are many overlapping parts with other routes, so at the time of verification, duplicate verification is omitted for the previously verified part, reducing the time required for verification. You can also do it.

If the specification limit requires a trace of microsteps in the opposite direction within the verification range, then the specification limit is preferably interpreted by substituting its kinematic relationship. For example, "In any microstep, the F1
If there is a specification restriction that if there is a description of microinstruction A in the field, or F2 of the microstep before or before that, there is no specification of microinstruction B in the field. If there is a description of microinstruction B in the field, the description of microinstruction A must not be in the F1 field of the next or subsequent microsteps. "And the specification is verified by tracing in the forward direction. . Therefore, the verification of the arbitrary microstep is completed at the same time as the verification of the microstep before or before. As described above, with respect to the specification restriction requiring the backward trace, the specification restriction violation on each path can be efficiently verified according to the microprogram sequence, similarly to the forward specification restriction.

[Embodiment] An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram for explaining a microprogram and specification restrictions to which the present invention is applied. FIG. 1A illustrates a part of hardware controlled by a microprogram, which is composed of LSI1 and LSI2. LSI2 is an ALU (Arithme) that calculates data D0 and D1.
tic Logic Unit), the LSI1 includes a modification processing unit (Modify) that performs processing such as shifting on the output data of this ALU. FIG. 2B shows an example of a program for performing a logical product of the data D0 and the data D1 by the ALU in step 3 and determining (testing) whether or not the data at point A is 0 in the next step 4. There is. The same figure (c) shows data D
It is an example of a micro program for determining whether or not the data at the point B changed by the change processing unit is 0 after taking the logical product of 0 and D1. This process is accomplished in steps 5-7. 2C is a so-called LSI crossover / modify process, and there is a timing restriction that the specification cannot be tested in the next cycle. For this reason, before the step 7 of testing the data at the point B, at least a dummy instruction (NOP) in which no operation is performed in the test field
Is provided in Step 6. A microprogram that does not include step 6 violates the specification restrictions.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

The microprogram verification device of the present embodiment, for the microprogram source 20 that is the verification target, extracts all the paths that can be passed during the execution, reads the source code of the addresses involved in all the paths, tabular,
Also, a table creating unit 2A that extracts a route of a single route that does not include a plurality of branches and tabulates the address string of each route, and specification restriction information 22 that is predetermined for the hardware controlled by this microprogram. With reference to the respective specification restrictions of, the comparison and verification unit 26 that sequentially verifies each microstep for each path, and the edit output unit 27 that edits and outputs the verification result to the printer 28 or console 29 that is an output device. Become. In this embodiment, the table creating unit 2A constitutes a route deriving unit, and the comparison verification unit 27 constitutes a verification unit.

The table creation unit 2A is a microprogram source 20
With reference to the microprogram definition information 21 that defines the meaning of each part of the microstep, with respect to the branch address of the microprogram, the own address / branch address pair table creation unit 23 that tabulates the correspondence relationship between the own address and the branch destination address And a staircase structure address table creation unit 24 that uses this result to create a table of branch addresses in a staircase structure, and a source code that creates a verification target source code table and a table of address strings common to all routes according to this result A table & route-specific address table creation unit 25 is included.

The microprogram definition information 21 and the microprogram specification restriction information 22 are defined in advance when the microprogram is created. The definition information 21 may be defined for each type of microstep, or may be defined for each individual microstep.

The microprogram specification limit information 22 is a collection of individual verification conditions. In this embodiment, a verification range is defined for each verification condition, and designation (description) is prohibited, designation obligation is specified, and its contents. Is specified. A wide variety of verifications can be performed according to this prescribed method. Additions and changes are easy.

In the example of the microprogram specification restriction information shown in FIG. 1, one specification restriction or verification condition is an identifier F / B indicating whether the verification direction is the forward direction or the backward direction, and whether the specification obligation or the specification is prohibited. The identification D / I, the number of steps N that defines the verification range, and the verification content portion. The verification content part is defined as the content of the specific field of the own step and the content of the specific field of the step within the verification range. For example, the specification restrictions described as F, D, 4, F0XX, F2YY are those of the verified microstep (that is, its own step).
If the F0 field contains the description "XX", the verification condition that the description "YY" must exist in the F2 field of the microstep within the range of 4 steps in the forward direction from the relevant step must be specified. become.

Hereinafter, specific processing of the main part of FIG. 1 will be sequentially described.

FIG. 3 shows a flowchart of the processing of the own address / branch destination address pair table creating unit 23 of FIG.

In the process shown in the figure, first, the definition information is read from the microprogram definition information file 21 '(33). Based on this definition information, the description position of the microstep's own step address and branch destination address is identified (34). Next, the microprogram source file 20 '
The source code for each microstep is read out, the own address and the branch destination address are extracted from the previously described address description position, and these are stored in the own address / branch destination address pair table 39 as a pair of entries. It is stored (36). This process is repeated for all microstep source code (37).

Next, FIG. 4 shows a flowchart of the process of the staircase structure address table creation unit 25 of FIG.

In this processing, first, the address pairs in the address pair table 39 obtained in the processing of FIG. 3 are sequentially read (42), and based on this, the address pairs are sequentially constructed in a staircase structure (43). . This procedure is repeated (44) until there are no more address pairs, and finally the staircase structure address table 45 is obtained. In constructing this staircase structure address table, the following conditions are imposed.

1) Assign separate vertical columns to the branch destination addresses of all address pairs.

2) For an address pair in which the branch destination address of another address pair is used as the branch source address, the branch source address is placed below the same column as the branch destination address.

3) The branch destination address and the branch source address of one address pair are arranged at the same height (level), and the branch destination address is located on the right side of the branch source address.

4) Different branch destination addresses of different address pairs are assigned to different columns even if they have the same address.

Table 45 is created to meet all these requirements. The actual data structure of the table 45 may be such that each address is stored in a matrix form.

Further, FIG. 5 shows a flowchart of the processing of the route-based address table creation unit 25 of FIG.

In this process, first, the address of the leftmost column is read from the staircase structure address table 45 obtained in the process of FIG. 4 (52). Next, the source code corresponding to this address is read from the microprogram source file 20 'and output to the table 57 (53). When these steps are sequentially repeated for all columns (54), the source code table 57 common to each path is obtained. With either path, the microprogram sequence proceeds from left to right in the staircase structure address table 45, so
The table 57, which is a table of source codes of addresses appearing along with this progress, is effectively used in each route verification process described later.

Then, based on the staircase structure address table 45, independent address strings for all the routes are extracted by the route information reorganization process (55). As a result, the address string table 58 for each path is obtained.

FIG. 8 shows a one-line flow chart of the route information reorganization process (FIG. 55) for obtaining the route-specific address sequence.
In this process, a counter that functions as an address read pointer for each column n (0, 1, 2, 3, ...) Is assumed, and the value of the counter n is represented by CLM (n). The value of each counter corresponds to the level (1, 2, 3, ...) Of the staircase structure address table. Further, a variable TBLROW is introduced as a pointer for designating an address column of the address column table 58, that is, a row of the table, and a flag CLMFLG (n) for identifying the address already registered in the table 58 as the address of the route 1 is set. I am preparing. Less than,
The process of FIG. 8 will be briefly described by taking as an example the case where the route-specific address string table 58 is created from the contents of the staircase structure table 45 of FIG.

According to the flow of FIG. 8, first, the first address A1 is written in the first row of the table (81 to 85), and after entering the loop, the address pairs are sequentially read downward, and sequentially.
Follow the single route so that the branch destination address becomes the new branch source address, and sequentially table the branch destination addresses.
We will add it to the first line of 58 (85-89,92,93,94,97). In this example, when A1, A2, A3, A4, A7 are reached, the address pair having A7 as a new branch source cannot be read, and the decision block 87 determines that the address sequence of the first route is Considering that it is finished, move to the "YES" side. Therefore, it returns to the address where there were a plurality of branches and finds another branch destination (95 to 97,86 to 88,94), and the table 58 for that branch destination is used.
The branch destination address string from A1 to that is output to the line next to (90, 91). Furthermore, the branch destination address sequence following this new sequence is added (92, 93). In this way, the address sequences A1, A2, A3, A5, A9 of the different routes are obtained. After this address sequence is completed, the branch destination left behind is found, and the address sequence of a new route is obtained.

The address reorganization process is not limited to the flow shown in FIG. 8, and may be another flow as long as the address column table 58 is obtained by utilizing the characteristics of the staircase structure table 45.

6 and 7 are flowcharts of the process of the comparison verification unit 26 of FIG. FIG. 6 corresponds to the forward trace, and FIG. 7 corresponds to the backward trace.

In the forward trace of FIG. 6, first, one specification restriction, that is, the verification condition VC is read from the specification restriction information file 22 '(60). The method of describing the verification condition VC is as described above. Here, the identifier F / B is "1", that is, the forward trace, the verification range is N microsteps, the verification content is the description of the F1 field for its own microstep is "XX", and the description of the F2 field is for the microstep within the verification range. Is "YY". For the identifier D / I,
Consider both designated obligations and prohibited designations. Obligation to specify between fields in own microstep as verification condition,
When it includes those that specify the prohibition of designation, it is possible to include the own microstep in the verification range.

Next, the address sequence of one route is read from the route-specific address sequence table 58 (61), and the source code SC corresponding to the first address is read from the source code table 57 (62). The content of this source code SC is the verification condition VC
Check whether the specified microstep matches the specified content (in this example, the description content of the F1 field is "XX") (63), and if it does not match, the verified microstep is no more Since there is no need to make a judgment, check if there is a source code for the next address on the same route (6B). If they match, the source code of the subsequent microstep within the verification range (or the self microstep if the verification range includes the self microstep) is read (64). Therefore, it is checked whether or not the content of the read microstep is equal to the content specified by the verification condition VC (in this example, the description content of the F2 field is "YY"). If they match, it is checked whether or not the verification condition is specification prohibition (66). If the specification is prohibition, it is determined that the specification restriction is violated, and the verification result is stored in the storage means. In the present embodiment, if the designation is not prohibited, the designation is obligatory. Therefore, it is determined that the obligation is satisfied, and the own address is updated and the source code is read (6B, 62). If the judgment result in the judgment block 65 does not match, it is checked whether or not the verification condition is the designated obligation (67), and if it is not the designated obligation, the verification within the verification range is further continued (6A, 64). If it is a designated obligation, it is checked whether the verification range is completed (68). If it is completed, it is determined that the specified obligation is not satisfied, and the verification result is stored (6).
9). If the verification range has not ended, the verification is continued for the source code of the subsequent address (64). Thereafter, if a match is detected at decision block 65, the designation obligation has been met, as described above.

In this way, after the verification of all the source codes of one path is completed (6B), the path information is updated (6C, 60), and the same specification restriction is verified again.

When the verification of all routes is completed, update the verification condition VC ((6
D, 61), and repeat the above procedure. Separately from the above procedure, first, after verifying all the verification conditions for one route,
The route may be updated.

Next, the backward trace will be described with reference to FIG. In this case, the identifier F / B is “0”.

In the case of the backward trace, as described above, the specification limit, that is, the verification condition is replaced with the corresponding condition and interpreted to enable the forward trace. For example, "If the description of the F1 field of your microstep is" XX ",
"YY" in the F2 field up to two microsteps before that
The prohibition condition "There must be no description"
The even-numbered relation "If the F2 field of the own step has a description of" YY ", the F1 field up to two microsteps after must not have a description of" XX "" is replaced with a prohibition condition. In addition, the mandatory condition "If the description of the F1 field of the own microstep is" XX ", the description of" YY "must be present in the F2 field up to two microsteps before that" is " If there is no description of "YY" in the F2 field, there must be no description of "XX" in the F1 field after 2 microsteps. " For this reason, FIG. 7 shows a slight modification of the flowchart of FIG. The changes are that the contents of the microsteps within the verification range are examined first, and that the designation prohibition judgment block 66 and the designation obligation judgment block 67 in FIG. 6 follow the match judgment block 63 in FIG. That is, the verification range end judgment block 68 in FIG. 6 is omitted. Only the processing from block 63 to block 69, which is different from FIG. 6, will be described below with reference to the flowchart of FIG. 7.

In the decision block 63, the description content of the F2 field of the source code SC is examined in order to examine the description content of the source code SC for the content specified by the verification condition VC for the micro step within the verification range (F2 field is “YY” in this example). Is compared with the contents of the same field of the verification condition VC. As described above, in the case of backward tracing, according to the even-numbered interpretation of the prohibited condition, if the specific field of the own microstep matches the specified content, the following microstep needs to be inspected, and vice versa. According to the even-numbered interpretation of the condition, if the specific field of the own microstep does not match the specified content, the subsequent microstep needs to be examined. Therefore, if a match is detected as a result of the comparison in the decision block 63, it is checked whether the designation is prohibited (76), and if they do not match, it is checked whether the designation is obligatory (77). If the result of decision block 76 or 77 is YES, the source code of the subsequent microstep (which should be the own microstep in the case of backward tracing) is read (6
4) Check the specified contents (in this example, the F1 field is "XX") for the own microstep according to the verification conditions (6
Five). If the contents of the F1 field match, the verification result is stored as a specification restriction violation (69). If they do not match, the subsequent microsteps are inspected within the verification range (6A, 64). If the result in decision blocks 76 and 77 is NO, the address of the microstep is updated and the next source code is read (6B, 62).

In this way, even in the case of the backward trace, efficient verification can be performed as the forward trace. In particular, this conversion to the forward trace is difficult when the number of source codes that can be temporarily stored in the source code table 57 is limited due to storage capacity, or due to the specifications, it is difficult to read the source code table 57 in the reverse direction. It is useful in some cases.For convenience of explanation, the forward trace and the backward trace are described as separate processes.However, in reality, when the individual specification limits are read, they are sorted by the identifier F / B. Since it is known whether it is the direction or the opposite direction, both the flowcharts can be combined as a single process by switching the processes at a necessary time.

Further, in the processing of FIG. 6 and FIG. 7, all the microsteps are verified for each route, but the same verification is repeated for the microsteps before the route branches into two or more. Because,
Such duplicate verification is not always necessary. Therefore,
In view of the fact that the branch point was found when the route-specific address string table 58 was created, the route information read block
At 61, the address sequence after the step before the verification range step from the branch point may be read.

Further, in this embodiment, after the processing of FIG. 5 is completed, the verification processing of FIGS. 6 and 7 is performed.
As the processing of FIG. 5 progresses, that is, the verification processing may be performed in parallel while sequentially updating the source code table and the route-specific address string sufficient to cover the verification range.

The edit output unit 27 of FIG. 1 is not particularly shown,
If there is a specification restriction violation, based on the verification result stored by the previous verification process, for example, the route, microstep address, type of specification restriction, etc. are specified,
Output to the output device in a format that can be recognized by the operator. Based on this output information, the programmer can easily modify the microprogram so as not to violate the specification limit.

[Effects of the Invention] As is clear from the above description, according to the present invention, it is possible to verify a violation relating to the specification limitation of a microprogram at the source level before executing the microprogram, and to use the conventional verification method. In comparison, verification can be performed quickly and efficiently without omission.

[Brief description of drawings]

FIG. 1 is a block diagram of a microprogram verifying apparatus according to the present invention, FIG. 2 is an explanatory view for explaining specification restrictions of a microprogram, and FIGS. 3, 4, and 5 are tables shown in FIG. Flow chart of processing of each part of the department,
6 and 7 are flowcharts of the processing of the verification processing unit in FIG. 1, and FIG. 8 is a flowchart of the route information organization processing in FIG. 20 ... Micro program source 21 ... Micro program definition information 22 ... Micro program specification restriction information 23 ... Own address / branch destination address pair table creation unit, 24 ... Stair structure address table creation unit 25 ... Source code table & route-specific address sequence table Creation unit 26… Comparison verification unit 27… Edit output unit 28… Printer 29… Console 2A… Table creation unit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Zentaro Hirose, 1 Horiyamashita, Horiyamashita, Hadano, Kanagawa Prefecture, Kanagawa Plant, Hiratsugu Co., Ltd. (72) Masakazu Sugihara, 1st, Horiyamashita, Hadano, Kanagawa Prefecture Kanagawa Factory (56) Reference JP 61-199126 (JP, A) JP 62-166445 (JP, A) JP 63-3347 (JP, A)

Claims (11)

[Claims] 1. A microprogram verification method for verifying that a microprogram is correctly described according to specification restrictions, and refers to microprogram definition information defining the description content of a microstep of a verification target microprogram source. Then, the address of each microstep and the description position of the branch destination address are recognized, and for each microstep of the verification target microprogram source, the pair of the address and the branch destination address is obtained based on the recognized description position. By obtaining an address sequence table that defines an address sequence for each route based on the address pair information, all routes that can be passed during execution of the microprogram are derived, and each microstep of the derived route is obtained. In the light of the above specification limits, A microprogram verification method characterized by verifying whether or not the microstep is a correct description and outputting the verification result. 2. A staircase structure address table in which an address pair having a branch destination address of another address pair as a branch source address is arranged in association with a branch destination address of the other address pair of the branch source address of the address pair. Seeking
2. The microprogram verifying method according to claim 1, wherein the address string for each path is obtained based on the staircase structure address table. 3. An address sequence common to each route is extracted based on the staircase structure address table, a source code table corresponding to the address sequence is created, and the source code table is subjected to the verification process. The microprogram verification method according to claim 1, wherein 4. The method for verifying a microprogram according to claim 1, wherein the specification restriction defines, as a verification range, the number of steps to be verified in the forward direction or the backward direction of the microstep to be verified. 5. The microprogram verification method according to claim 4, wherein the verification range also includes a self microstep. 6. The microprogram verification method according to claim 1 or 4, wherein the specification restriction includes a designation obligation for requesting a description of specific content according to the content of the microstep to be verified. 7. The microprogram verification method according to claim 1, 4 or 6, wherein the specification restriction includes specification prohibition for prohibiting the description of specific contents according to the contents of the microstep to be verified. 8. The specification restriction requiring verification in the reverse direction is replaced with a condition having a relationship with the specification restriction condition, and verification is performed as a specification restriction requiring verification in the forward direction. The microprogram verification method according to claim 4, wherein 9. The method according to claim 1, wherein among the micro steps of an arbitrary path, the verification is omitted for the micro steps which have already been verified for other paths.
The described microprogram verification method. 10. A microprogram verification device for verifying that a microprogram is correctly described according to specification restrictions, and means for storing a microprogram source, and address description of the microstep of the microprogram source. Means for storing microprogram definition information defining a position, means for storing microprogram specification restriction information, and an address sequence defining an address sequence for each route based on the microprogram definition information and the microprogram source By obtaining a table, route deriving means for deriving from the microprogram source all routes that can be passed during execution of the microprogram, and each microstep of the derived route is the microprogram specification limit. Microprogram verification apparatus characterized by comprising: a determining verification unit whether a correct statement against, and output means for outputting to the output device a verification result by the verification means. 11. A microprogram verification method for verifying that a microprogram is correctly written according to specification restrictions, wherein a pair of the address and a branch destination address is provided for each microstep of the microprogram source to be verified. Then, by obtaining an address string for each route based on the address pair information, all routes that can be passed at the time of execution of the micro program are derived, and the above-mentioned specification restrictions are sequentially applied to each micro step of the derived route. In light of the above, it is verified whether or not the microstep is a correct description, and at the time of the verification, for the specification restriction that requires verification in the opposite direction, the specification restriction condition and the treatment relationship Replace with a certain condition, perform verification as a specification restriction that requires forward verification, and output the verification result. A microprogram verification method characterized by the above.