JPH07273625A - Ringing preventing circuit - Google Patents

Abstract

PURPOSE:To prevent destruction of an element and malfunction of the circuit by limiting a discharge current through a parasitic capacitance when an output transistor(TR) is active so as to prevent a ringing from being generated in an output waveform. CONSTITUTION:A constant current source 21 is provided between a source electrode of a TR 3 and ground. In this case, let a voltage of a positive power supply VDD be 5V and a negative power supply be set to an earth level, when a potential of an input terminal 1 is 5V, since an output level of an inverter 2 is 0V and the TR 3 is open, a charge is charged in a capacitor 10 via a resistor 5 and a level of an output terminal 7 reaches 5V. When the level of the input terminal 1 changes from 5V to 0V, an output level of the inverter 2 changes from 0V to 5V and the TR 3 changes from the OFF state to the ON state. Thus, the charge charged in the capacitor 10 is discharged via the TR 3, but the discharge current in this case is controlled by the constant current source 21 to suppress a timewise change in the discharge current thereby reducing ringing produced at an output terminal 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ringing prevention circuit for an output section of a semiconductor integrated circuit, and more particularly, it suppresses ringing caused by a capacitance component and an inductance component parasitic on an output terminal section of a semiconductor integrated circuit device. The present invention relates to a ringing prevention circuit.

[0002]

2. Description of the Related Art The basic structure of a conventional output circuit of this type is shown in FIG. In FIG. 3, the input signal from the input terminal 1 is applied to the gate of the output transistor (N-channel MOS transistor) 3 via the inverter 2.
The Drain drain output of this transistor 3 is the circuit output terminal 7
Will be delivered to the outside.

The source of the transistor 3 is connected to the ground which is the reference potential point, the output terminal 7 is connected to the pull-up resistor 5 and is pulled up to the positive power source VDD. The resistor 5 is also used for impedance matching of the transmission line.

If the potential of the positive power source VDD is 5V and the potential of the negative power source is 0V with the ground being 0V, the output of the inverter 2 is 0V and the transistor 3 is off when the potential of the input terminal 1 is 5V at a high level. Then, the load capacitance (parasitic in the circuit package or the like) 10 parasitic on the output terminal 7 is charged through the resistor 5, so that the potential of the output terminal 7 becomes low level 0V.

When the potential of the input terminal 1 becomes a low level of 0 V, the output of the inverter 2 changes from 0 V to 5 V, the transistor 3 changes from off to on, and the charge charged in the load capacitance 10 is in this on state. The low level output voltage is discharged by the transistor 3 of FIG. 1 and is determined by the resistance value RL of the resistor 5 and the ON resistance RON of the transistor 3, and is represented by VDD × RON / (RL + RON).

Since the parasitic inductance component 11 exists between the output terminal 7 and the ground in addition to the capacitance 10, the inductance 11 is discharged when the capacitance 10 is discharged.
A current flows through the output current, which causes ringing in the output waveform.

As a technique for preventing the occurrence of ringing caused by such parasitic capacitance and parasitic inductance of the output circuit section, there is a circuit described in Japanese Patent Laid-Open No. 4-287415, and an example thereof is shown in FIG. There is. In FIG.
The same parts as those in FIG. 3 are designated by the same reference numerals.

The signal from the input terminal 1 is led to the circuit output terminal 2 via the inverter 2. An N channel MOS transistor 8 and a P channel MOS transistor 9 are provided in order to suppress ringing due to the parasitic capacitance 10 and the parasitic inductance 11.

The transistor 8 is provided between the output line and the positive power source VDD, and its gate is grounded. The transistor 9 is provided between the output line and ground, and its gate is biased by the positive power supply VDD. The back gates of both transistors 8 and 9 are both connected to the output line.

Therefore, if the voltage of the output terminal 7 becomes high due to the occurrence of ringing in the output line, the transistor 9
Is turned on, and when it becomes low, the transistor 8 is turned on, and overshoot and undershoot due to ringing are suppressed by these transistors 8 and 9.

The structure of FIG. 4 is a technique for suppressing the occurrence of ringing due to the capacitance and inductance parasitic on the output terminal, but a technique for preventing the delay of the level transition due to the capacitance parasitic on the output terminal is specially described. Kaihei 4-37216
Explain by citing No. 5. FIG. 5 is a diagram showing an example of the circuit.

In FIG. 5, an input signal from the input terminal 1 becomes a positive / negative phase signal via the inverter 2 and becomes a complementary input of the current switching type logic (CML) section 40. This C
The ML section 40 includes a pair of N-channel MOS transistors 3a and 3b whose sources are common to each other, and a current source 20 which supplies an operating current to the common source connection point. A positive / negative phase signal of the input signal is applied.

A pair of complementary signals are output from the drain electrodes of these transistors 3a and 3b, and circuit output terminals 7a and 7a
It is led to 7b. Between these output terminals 7a, 7b and the positive power supply VDD, resistors 5a, 5b for matching with the transmission line are provided.
Is provided and serves as a drain load resistance of the pair of transistors 3a and 3b of the CML unit 40.

These resistors 5a and 5b have parasitic capacitances 6a,
Since 6b is added in parallel, the charges charged in the capacitors 6a and 6b when the transistors 3a and 3b are turned on are discharged by the resistors 5a and 5b when the transistors 3a and 3b are turned off. Output terminals 7a and 7
The rise of b is delayed by the discharge time constant.

Therefore, as shown in FIG.
P-channel MOS transistors 4a and 4b are provided between the drains of a and 3b and the positive power supply VDD, and when the transistors 3a and 3b are turned off, the transistors 4a and 4b are turned on to control the capacitances 6a and 6b. The charged electric charges are rapidly discharged to accelerate the rise time of the output terminals 7a and 7b.

[0016]

In the ringing prevention circuit shown in FIG. 4, it is necessary to provide means for suppressing both overshoot and undershoot above and below the output signal line, which is a good idea in terms of hardware. It has the drawback of not having it.

Further, the output rise delay prevention circuit shown in FIG. 5 does not prevent ringing due to the capacitance and the inductance parasitic on the output terminal, so that the output circuit is designed to operate at high speed. If
Since the current value of the constant current source 20 is designed to be large, the discharge current of the parasitic capacitance becomes large accordingly, and the peak value of ringing becomes large. Therefore, there is a drawback that the element is destroyed or malfunctions due to the ringing of the output waveform generated when the data changes.

An object of the present invention is to provide an output circuit capable of effectively preventing ringing of an output waveform when data changes so as to prevent element destruction or malfunction.

[0019]

According to the present invention, there is provided a ringing prevention circuit for an output circuit, wherein a drain output of the output transistor is derived through a circuit output terminal, the source electrode of the output transistor and a reference. A ringing prevention circuit characterized in that a limiting means for limiting a discharge current value of a parasitic capacitance parasitic on the circuit output terminal is provided between the potential prevention point and the potential point.

[0020]

When the output transistor is turned on, the discharge current of the charge stored in the output parasitic capacitance flows to the reference potential side through the output transistor. In order to limit this discharge current, A constant current source having a current value such that ringing does not occur with the reference potential is connected to suppress ringing.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.
3 to 5 are designated by the same reference numerals. This example is an example applied to the circuit of FIG.

The signal input from the input terminal 1 is passed through the inverter 2 and the N-channel MO that is an output transistor.
It is input to the gate of the S transistor 3. The output from the drain electrode of the transistor 3 is led to the circuit output terminal 7 and pulled up to the positive power supply VDD by the impedance matching resistor 5 with the transmission line.

A constant current source 21 is provided between the source electrode of the transistor 3 and the ground, and the current value is
It shall be set to a value that limits the discharge current of the parasitic capacitance 10.

If the potential of the positive power source VDD is 5V and the potential of the negative power source is ground, the output of the inverter 2 is 0V and the transistor 3 is off when the potential of the input terminal 1 is 5V.
Therefore, the capacitor 10 is charged with electric charge through the resistor 5 and the output terminal 7 becomes 5V.

When the input terminal 1 changes from 5V to 0V,
The output of the inverter 2 changes from 0V to 5V, and the transistor 3 changes from off to on. Therefore, the charge of the capacitor 10 is discharged through the transistor 3, but the discharge current at this time is controlled by the constant current source 21,
The temporal change rate (di / dt) of the discharge current is suppressed, and the ringing generated at the output terminal 7 is reduced.

FIG. 2 is a circuit diagram showing another embodiment of the present invention, and the same portions as those in FIG. 1 are designated by the same reference numerals. In this example, an N-channel MOS transistor 12 is further added to the configuration of FIG. 1, the signal of the input terminal 1 is applied to the gate, and the output terminal 7 is push-pull driven by the transistors 3 and 12.

Thus, when the signal at the input terminal 1 is at a high level of 5 V (when the transistor 3 is off), the transistor 12 is turned on and the parasitic capacitance 10 is charged by the on transistor 12. It is intended to speed up the rising of the output terminal.

[0029]

As described above, according to the present invention, since the discharge current of the parasitic capacitance when the output transistor is on is limited, it is possible to prevent ringing from occurring in the output waveform and destroy the element. This has the effect of preventing malfunctions.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of another embodiment of the present invention.

FIG. 3 is a diagram showing an example of a conventional output circuit.

FIG. 4 is a diagram showing an example of ringing prevention of a conventional output circuit.

FIG. 5 is a diagram showing an example in which a rising speed of a conventional output circuit is increased.

[Explanation of symbols]

 1 Input Terminal 2 Inverter 3, 12 N Channel MOS Transistor 5 Resistance 10 Parasitic Capacitance 11 Parasitic Inductance Generation 21 Constant Current Source

Claims (2)

[Claims] 1. A ringing prevention circuit for an output circuit, wherein a drain output of an output transistor is derived via a circuit output terminal, the circuit output being provided between a source electrode of the output transistor and a reference potential point. A ringing prevention circuit comprising a limiting means for limiting a discharge current value of a parasitic capacitance parasitic on a terminal. 2. The ringing prevention circuit according to claim 1, wherein the limiting means is a constant current source.