JPH07273218A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make up for the resolution limitation of a lithography technique so as to carry out a finer processing by a method wherein a second etching mask material is formed on the side wall of a groove provided to a first etching mask material which is set as wide as prescribed, and a third etching mask material is formed inside the groove and flattened by polishing. CONSTITUTION:A silicon oxide film 12 is formed through an LPCVD on the surface of a semiconductor substrate 11 where an element isolating region 15 is formed through a selective oxidation method, a silicon nitride film 13 is provided on the film 12, and a silicon oxide film 14 is formed on the film 13. A photoresist film is formed on the surface of the silicon oxide film 14 and patterned as large in width as prescribed or a first width W1, the silicon oxide films 12 and 14 and the silicon nitride film 13 are anisotropically etched, and the semiconductor substrate 1 is exposed as wide as W1. In succession, etching is performed so as to leave the silicon nitride film only on the side face of a mask material for the formation of a second mask, and furthermore a third mask is formed the same as above. This mask is polished, photoresist is applied, and then etching is carried out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device,
In particular, it relates to a method for manufacturing a DRAM trench capacitor.

[0002]

2. Description of the Related Art A conventional method of manufacturing a trench capacitor by photolithography will be described with reference to FIGS. First, as shown in FIG. 9, the silicon substrate surface 101 is thermally oxidized to form a silicon oxide film 10 having a film thickness of 30 nm.
Form 2. Next, LPCVD (Low Pressure Chemical Vapor Depositio) is performed on the surface of the silicon oxide film 102.
n) method is used to form a 200 nm-thickness silicon nitride film 103 having a different etching rate from that of the silicon oxide film on the surface of the silicon oxide film 102 as a mask stopper, and to apply resist, silicon is used. A silicon oxide film 104 having a film thickness of 700 nm is formed on the surface of the nitride film 103.
To form.

Subsequently, as shown in FIG. 10, a photoresist is applied to the insulating film on the surface of the semiconductor substrate, and a resist pattern 111 of the trench opening is formed on the region where the trench is to be opened by exposure and development. Next, the silicon nitride film 103 and the silicon oxide films 102 and 104 are etched by RIE using CHF3 to form a mask 112 for trench opening.

Subsequently, as shown in FIG. 11, after removing the photoresist pattern 111 by ashing, the silicon oxide films 102 and 104 and the silicon nitride film 103 are removed.
With the mask as a mask, the trench 121 is opened in the silicon substrate 101 by RIE using SiF4. The width of the trench is 0.8 μm in each length and width, and the depth is 4 μm.
Through the above steps, the trench for the capacitor is formed on the semiconductor substrate.

[0005]

In the conventional method of manufacturing a trench capacitor as described above, a photoresist is applied on the insulating film of the semiconductor substrate to open the trench,
This is patterned by exposure. At this time, there is a limit in the resolution of lithography, and there is a limit in reducing the width and width of the trench capacitor and the distance between two adjacent trench capacitors. According to the conventional manufacturing method, the width of the trench is limited to about 0.8 μm in each length and width. For this reason, the limitation of the resolution limit of lithography has been one obstacle in high integration of devices in recent years. Therefore, it is required to improve the resolution limit of lithography and to develop a new lithography technique that enables fine processing while compensating for the current resolution limit of lithography.

In view of the above problems of the lithography technique, the present invention supplements the resolution limit of the lithography technique,
It is an object of the present invention to provide a technique that enables finer processing in forming a trench.

[0007]

In order to achieve the above object, in the present invention, a groove having a predetermined width is formed in an insulating film on the surface of a semiconductor substrate, and this is etched to form a first etching mask material. Form. A second etching mask material is formed on the side wall of the groove having this predetermined width. next,
A third etching mask material is formed inside a predetermined groove formed by the first etching mask material on which the second etching mask material is formed. The surfaces of these first to third etching mask materials are polished by polishing to flatten the surfaces, and then only the second etching mask material is etched. As a result, a groove composed of the first and third etching mask materials is formed on the semiconductor substrate.
The width of the short side of the trench is formed in a later step based on the width of this groove. Subsequently, a photoresist is deposited on the entire surface, and this is patterned with the width of the long side of a trench formed in a later step to form a mask. The semiconductor substrate is etched using this mask to form trenches.

[0008]

In the method of forming the trench capacitor according to the present invention, the conventional photolithography technique is used,
A trench is formed by modifying the method of forming the etching mask material. The width of one side, which is the space of one trench that can be formed by the current lithography technology, is 0.8 μm.
It is possible to form two trenches in the square.

As described above, according to the present invention, it is possible to form a finer element than that by the conventional forming method by modifying the forming method so as to supplement the resolution limit while using the existing lithography technique. Becomes

[0010]

Embodiments of the present invention will be described below with reference to the drawings. First, as shown in FIG. 1, the surface of the semiconductor substrate 11 having the element isolation region 15 formed by the selective oxidation method is thermally oxidized to form a silicon oxide film 12 having a film thickness of 30 nm.
Next, a silicon nitride film 13 having a film thickness of 200 nm is formed as a mask stopper on the surface of the silicon oxide film 12, and a film having a film thickness of 700 n is formed on the surface of the silicon nitride film 13.
Then, an insulating film consisting of three layers is formed on the surface of the semiconductor substrate 11. All of these insulating films are formed by the LPCVD method.

Subsequently, as shown in FIG. 2 ((a) is a sectional view and (b) is a top view), a photoresist (not shown) is formed on the surface of the silicon oxide film 14, and this photoresist is formed. Pattern with the first width. Using this as a mask, the silicon oxide films 12 and 14 and the silicon nitride film 13
The semiconductor substrate 1 by anisotropic etching.
1 is exposed in the first width, and the first etching mask material 2
Form 2. This first width is twice the width of the short side of the trench 21 formed in a later step and the total width of the element isolation regions 15 which is the width between the adjacent trenches. Here, the first width is 0.8 μ according to the current lithography technology.
It is possible to form up to a width of m. Therefore, in this embodiment, the first width is set to 0.8 μm for the purpose of finely processing the trench.

Subsequently, as shown in FIG. 3, a silicon nitride film 31 having a film thickness corresponding to the width of the short side of a trench formed in a later step is formed on the surface of the first etching mask material 22 by the LPCVD method. To form. In this embodiment, the film thickness is set to 300 nm (0.3 μm).

Subsequently, as shown in FIG. 4, the silicon nitride film other than the side surface is removed by anisotropic etching so that the silicon nitride film 31 remains only on the side surface of the first etching mask material 22. A second etching mask material 41 of 31 is formed. This silicon nitride film 31
Thus, the film thickness of the second etching mask material 41 according to the above corresponds to the width of the short side of the trench formed in a later step. Next, the first etching mask material 2 is formed on the surface of the second etching mask material 41 by the LPCVD method.
A silicon oxide film 42 having an etching rate similar to that of No. 2
Is formed on the entire surface, and this is used as a third etching mask material 51.
And

Then, as shown in FIG. 5 ((a) is a sectional view and (b) is a top view), the surface of the second etching mask material 41 covered with the silicon oxide film 42 is completely exposed. Until the first, second and third etching mask materials 2
2, 41 and 51 are polished. In this embodiment, polishing is performed so that the height of each etching mask material from the surface of the semiconductor substrate 11 is about 500 nm. Next, the first, second and third etching mask materials 2
A photoresist 52 is applied on the surface of 2, 41, 51. This photoresist is selectively removed with a second width in a direction orthogonal to the direction in which each etching mask material is formed, to form a resist pattern 52. In this embodiment, an opening pattern is formed so that a plurality of trenches can be simultaneously etched. The second width, which is the width of the resist pattern 52, is 0.
It is possible to reduce the width to 8 μm, and in the present embodiment, the second width is set to 0.8 μm for the purpose of finely processing the trench. Therefore, the width of the short side of the trench formed in the subsequent step is 0.3 μm, which is the film thickness of the second etching mask material 41, and the width of the long side is 0.8 μm, which is the width of the resist pattern 52. It becomes possible.

Then, as shown in FIG. 6 ((a) is a sectional view and (b) is a top view), a second etching mask material 41 composed of a silicon nitride film is formed by using the resist pattern 52 as a mask. The opening 6 formed by the insulating film is removed by using the anisotropic etching technique having a high selection ratio with the silicon oxide film.
1 to form the semiconductor substrate 11 in the region where the trench is to be formed
Expose. By this step, a mask for opening the trench is formed by the first and third etching mask materials 22 and 51. The reason why the second etching mask material 41 is formed of a silicon nitride film is to obtain a difference in etching rate between the second etching mask material 41 and the first and third etching mask materials 22 and 51. Therefore, as the material constituting the second etching mask material, when etching this, the first,
Any material can be used as long as it has a selection ratio with respect to the third etching mask material, and for example, a polycrystalline silicon film or the like can be used.

Subsequently, as shown in FIG. 7, first and third etching mask materials 22, 51 and a resist pattern 52.
Using the as a mask, a trench 71 is formed in the region corresponding to the opening 61 on the surface of the semiconductor substrate 11 by anisotropic etching. The depth of the trench is 6μ in order to obtain the surface area.
The thickness is about 8 μm.

Through the above steps, it becomes possible to form a trench having a finer width than the conventional one while using the conventional photolithographic technique. Here, FIGS. 8A and 8B are diagrams showing a comparison of the widths of the trench formed by using the conventional technique and the trench formed by the present invention. (A) shows a trench formed by a conventional manufacturing method, and (b) shows a trench formed by a manufacturing method according to the present invention. In the figure, 81 is a trench, 82 is a semiconductor substrate, X is the length of one side of a trench formed by a conventional manufacturing method, and Y is the distance between adjacent trenches. As shown in the figure, according to the conventional method for forming a trench, the width of the trench 81 is determined by the resolution limit of lithography, so that the width X of one side is limited to a square having a minimum width of 0.8 μm.

By using the manufacturing method shown in the above embodiment of the present invention, a square having a side width of 0.8 μm, which is a space for forming one trench that can be formed by the current lithography technique, is formed. It becomes possible to form two trenches. Therefore, the resolution limit of the current lithography technology can be supplemented, and the width X of one side of the trench can be formed to be less than half by the conventional manufacturing method. For example, the vertical and horizontal lengths are 0.8 μm on the long side,
It becomes possible to form a trench having a short side of less than 0.4 μm. The distance Y between adjacent trenches is determined by the width of the short side of the trench. Therefore, since it is not limited by the resolution limit of lithography, it is possible to form the trench with a width smaller than the distance Y between adjacent trenches by the conventional manufacturing method. Further, by forming the film thickness of the second etching mask material to be thinner than that shown in the embodiment, the width of the short side of the trench to be formed can be further reduced, so that the sectional area of the trench is further reduced. It becomes possible.

[0019]

According to the method of forming the trench capacitor of the present invention, the trench is formed by modifying the method of forming the etching mask material while using the conventional photolithography technique. By using the present invention, it becomes possible to form two trenches in a square, which is a space of one trench that can be formed by the current lithography technology. Therefore, while using the current lithography technology, by modifying the formation method so as to supplement the resolution limit, it becomes possible to form a trench with a cross-sectional area of half or less of the cross-sectional area of the trench by the conventional formation method, Further miniaturization of the device becomes possible.

[Brief description of drawings]

FIG. 1 is a sectional view showing a manufacturing process according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the manufacturing process of the embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the manufacturing process of the embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the manufacturing process of the embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the manufacturing process of the embodiment of the present invention.

FIG. 7 is a cross-sectional view showing the manufacturing process of the embodiment of the present invention.

FIG. 8 is an explanatory view showing the effect of the present invention.

FIG. 9 is a cross-sectional view showing a conventional manufacturing process.

FIG. 10 is a sectional view showing a conventional manufacturing process.

FIG. 11 is a cross-sectional view showing a conventional manufacturing process.

[Explanation of symbols]

 11, 101 Semiconductor substrate 12, 14, 102, 104 Silicon oxide film 13, 31, 103 Silicon nitride film 15 Element isolation region 21, 71 Trench 22 First etching mask material 41 Second etching mask material 51 Third etching Mask material 52,111 Resist pattern 61 Opening by insulating film 112 Trench opening mask

Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/822

Claims (8)

[Claims] 1. A step of forming an insulating film on a surface of a semiconductor substrate, and a first etching mask material having a first width and having a groove along a predetermined direction by selectively etching the insulating film. A step of forming a second etching mask material on a side surface of the first etching mask material, and a groove having the first predetermined width in which the second etching mask material is formed. A step of forming a third etching mask material, a step of applying a resist to the surfaces of the first, second and third etching mask materials, and the second etching by selectively removing the resist. Exposing the surface of the mask material to a second width, and removing a portion of the second etching mask material whose surface is exposed by the patterning by etching to form a predetermined opening, And a step of forming a trench in a region of the semiconductor substrate corresponding to the opening, the method for manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the groove having the first width has a width equal to a width of a short side of the trench.
A method of manufacturing a semiconductor device, characterized in that the semiconductor device is formed to have a width longer than twice the width. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the width of the short side of the trench is determined based on the film thickness of the second etching mask material. . 4. The method of manufacturing a semiconductor device according to claim 1, wherein the step of selectively removing the resist is performed along a direction orthogonal to the predetermined direction. Method. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the width of the long side of the trench is determined based on the second predetermined width. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is formed of a multilayer film, and the uppermost film has an etching rate different from that of the second etching mask material. Manufacturing method of semiconductor device. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the third etching mask material has an etching rate different from that of the second etching mask material. 8. The method of manufacturing a semiconductor device according to claim 6, wherein the uppermost film and the third etching mask material are silicon oxide films, and the second etching mask material is a silicon nitride film. A method of manufacturing a semiconductor device, comprising: