JPH07271669A - Cache memory control circuit - Google Patents

Abstract

PURPOSE:To improve the efficiency of a system by enabling data to be written back to a main memory without stopping the operation of a CPU and unnecessarily occupying a system bus. CONSTITUTION:When an address from a CPU 1 makes a cache hit in writing operation, a cache memory part 2 stores the address of the FIFO memory in write-back FIFO 3 as write-back information. A bus control part 4 issues a request with the lowest priority for writing-back operation to the main memory to a control bus 103 and writes the data of the write-back FIFO 3 or the block of the cache memory part 2 back to the main memory when the data are present in the write-back FIFO 3 or when the data of the write-back FIFO 3 are replaced in the main memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory control circuit, and more particularly to a cache memory control system by a write back system.

[0002]

2. Description of the Related Art In recent years, CPU performance has been increasing day by day, and a cache memory is used to satisfy this CPU performance and improve system performance.

Conventionally, a write-through method and a write-through method have been used as a write control method for a cache memory. The write-through method is a method of simultaneously writing to both the main memory and the cache memory when the CPU performs a write operation (write operation), and the write-back method is a method of performing the write operation only to the cache.

In the write-through method, the consistency of data is always maintained between the main memory and the cache memory, but when the frequency of write operation is high, the frequency of access to the main memory increases and the system performance deteriorates. .

The write-back method improves the system performance as compared with the write-through method, but when a cache miss hit occurs, a new block (data in the main memory) and an old block (data in the cache memory).
It is necessary to replace and (and replace).

That is, it is necessary to write the block rewritten by the write operation in the cache memory to the main memory (hereinafter referred to as write back). This write-back may cause contention with other devices on the system bus, and this contention affects system performance.

In order to solve the problem of the write-back method, Japanese Patent Laid-Open No. 3-228150 discloses a technique for detecting the free time of the system bus and executing the write-back operation by utilizing the detected free time. ing.

In this technique, as shown in FIG.
CPU 5, cache memory controller 6, cache SRAM (Static Random Access)
The ssMemory 7 and the system bus availability detection circuit 8 are the address bus 151, the data bus 152, and the control bus 1.
53 and 53 are connected to each other.

In particular, when the system bus vacancy detection circuit 8 detects the vacant time of the system bus, the write-back instruction signal 156 is sent to the cache memory controller 6. At this time, the cache memory controller 6 returns the write-back instruction acknowledge signal 157 to the system bus availability detection circuit 8.

At this time, the operation of the CPU 5 is stopped by the hold request signal 154 from the OR circuit 9, and the cache SRAM 7 is driven by the chip select signal 155 from the OR circuit 10.

The above cache memory controller 6
As shown in FIG. 4, a decoder 61 that inputs and translates an address index, a tag memory 62 that stores tag information, a valid memory 63 that stores valid bits, and a dirty memory 64 that stores dirty bits.
In addition to having, the decoder 65, the pointer 67, and the incrementer 66 are provided.

In the read operation (read operation) from the CPU 5 in the system configured as described above, the CPU
The address from 5 is checked by the cache memory controller 6, and if the address is in the tag memory 62, the corresponding data is retrieved from the cache SRAM 7 by the CPU 5
It is designed to output to.

On the other hand, if the address is not in the tag memory 62, the block in the cache SRAM 7 at the present time starts from the LRU (Least Retry).
Used), FIFO (First In First)
Out) A block to be removed from the cache SRAM 7 is determined because replacement is performed based on the algorithm or the like.

In this case, if the dirty bit of the block to be ejected is "0", the block is purged and a block required by the CPU 5 is newly read into the cache SRAM 7 from the main memory (not shown).

However, if the dirty bit of the block to be ejected is "1", that block is the CPU 5
Indicates that the block has been rewritten, the block is transferred to the main memory, and thereafter, the same processing as that when the dirty bit is "0" is performed.

On the other hand, in the write operation from the CPU 5, the address from the CPU 5 is checked by the cache memory controller 6, and the address is checked by the tag memory 6
If it is 2, the data of the corresponding address existing in the cache SRAM 7 is rewritten and at the same time the dirty memory 64
Set the dirty bit of the corresponding address of "1".

On the other hand, if the address is not in the tag memory 62, the cache memory controller 6 writes the data output from the CPU 5 in the corresponding address in the main memory.

In the above system, when the system bus vacancy detection circuit 8 detects the vacancy of the system bus, the system bus vacancy detection circuit 8 sends a write back instruction signal 156 to the cache memory controller 6.

When the cache memory controller 6 receives the write-back instruction signal 156, it clears the pointer 67 and starts searching for the tag address with the dirty bit "1" in the dirty memory 64.

When the pointer 67 retrieves the dirty bit, the pointer 67 outputs a write-back instruction acknowledge signal 157 to the system bus availability detection circuit 8. If the dirty bit is not found in the pointer 67, the value is incremented by the incrementer 66 and the search is continued until the dirty bit is found.

When the pointer 67 finds a dirty bit, it outputs a write-back instruction acknowledge signal 157 to the system bus vacancy detection circuit 8 and also outputs corresponding tag information from the tag memory 62.

Therefore, the system bus empty detection circuit 8
Simultaneously receives the write-back instruction acknowledge signal 157 and the tag output of the tag memory 62 from the cache memory controller 6, and latches the tag output.

After that, the system bus vacancy detection circuit 8 uses the tag output as a block address for the cache S.
The corresponding block of RAM 7 is transferred to the main memory. When this transfer is completed, the system bus availability detection circuit 8 inactivates the write-back instruction signal 156. As described above, the write back operation is performed by utilizing the free time of the system bus.

[0024]

In the conventional cache memory control system described above, the write-back operation is performed during the free time of the system bus. However, after the free time of the system bus is detected, the dirty in the cache memory controller is detected. Since the bits are searched, there is a time difference of the search operation time from the detection of the free time of the system bus to the write back operation.

For this reason, the system bus is occupied during the write-back operation including the time of the search operation, so that access from the other device to the system bus is kept waiting and the write-back operation is performed. During this period, the CPU is held by the hold request signal from the cache memory controller, and there is a problem that the efficiency of the system deteriorates.

Therefore, an object of the present invention is to solve the above problems and enable write back to the main memory without stopping the operation of the CPU and without wastefully occupying the system bus. , Providing a cache memory control circuit capable of improving system efficiency.

[0027]

A cache memory control circuit according to the present invention is a cache memory control circuit for controlling a write operation only in a cache memory by a write-back method, and is a main memory device in the cache memory. Holding means for holding the data to be written back to and the address thereof, and a request for writing back the data and the address to the main storage device when the holding means holds the bus priority. And the issuing means for issuing at the lowest rank.

[0028]

When the cache memory is rewritten by the write operation of the CPU, the rewritten address and data are stored in the FIFO memory as write back information.

When data is present in this FIFO memory, or when a block of the cache memory is replaced with the main memory, the lowest priority request for write back to the main memory is issued to write back to the main memory. To do.

This enables write back to the main memory without stopping the operation of the CPU and without wastefully occupying the system bus, so that the efficiency of the system can be improved.

[0031]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the CPU 1, the cache memory unit 2, and the write-back FIFO 3 are respectively an internal address bus 111, an internal data bus 112, and an internal control bus 11.
3 and 3 are connected to each other.

In the cache memory unit 2, write back F
FIFO indicating whether or not the storage data from IFO3 is full
-When the FULL signal 131 is recognized and the write operation from the CPU 1 is hit, or when the dirty bit is recognized, the FIFO write signal 121 to the write-back FIFO 3 is validated.

The write-back FIFO 3 is internally equipped with an address and data FIFO memory (not shown), and a FIFO write signal 121 from the cache memory unit 2 and a FIFO read signal 14 from the bus control unit 4 are provided.
1 and 1.

The bus control unit 4 recognizes the FIFO-EMPTY signal 132 from the write-back FIFO 3 indicating the presence or absence of an address and data in the FIFO memory, and outputs the FIFO read signal 141 to the write-back FIFO 3.

The bus control unit 4 is a write-back FIF.
FIFO output address 133 and F output from O3
The IFO output data 134 is latched internally. At this time, the bus control unit 4 uses the FIFO output address 133
And latching the FIFO output data 134,
The latched address is output to the cache memory unit 2 via the address line 124 as a monitor address.

On the other hand, the cache memory unit 2 checks the monitor address from the bus control unit 4, and if the address is valid in the cache memory unit 2, the bus control unit 4
The address valid signal 122 is output to.

The bus control unit 4 is connected to the address bus 101, the data bus 102 and the control bus 103 of the system bus, and receives the address valid signal 122 from the cache memory unit 2 and at the same time gives the control bus 103 the lowest priority. Output the request.

Here, the lowest-priority request is preset as a request having the lowest priority in the device including the above-mentioned units and stored in the bus controller (not shown). The priority of the interval is also preset and stored in the bus controller.

Address bus 101 of the above system bus
The data bus 102 is used for accessing the main memory at the time of replacement and a cache miss.

FIG. 2 is a block diagram showing the configuration of the cache memory unit 2 of FIG. In the figure, the cache memory unit 2 includes a data memory 21, decoders 22 and 23,
The directory 24, the comparator 25, the data memory control unit 26, and the dirty bit search unit 27 are included.

The data memory 21 is an internal data bus 112.
And the data line 123 to store data from the CPU 1 and the main memory. Decoders 22 and 23
Is connected to the internal address bus 111 and decodes the address from the CPU 1.

The directory 24 comprises a tag section 24a for storing a tag address, a valid bit section 24b for storing a valid bit, and a dirty bit section 24c for storing a dirty bit.

The comparator 25 compares the address from the CPU 1 input via the internal address bus 111 with the tag address from the tag section 24a of the directory 24,
When the addresses match, the hit signal 125 is output.

The data memory control unit 26 controls the data memory 21 by the hit signal 125 from the comparator 25 and the dirty bit recognition signal 126 from the dirty bit search unit 27.

The dirty bit retrieving unit 27 always retrieves the dirty bit in the dirty bit unit 24c, and the FIFO-FULL signal 1 from the write-back FIFO 3 is retrieved.
31 controls the FIFO write signal 121 and the dirty bit recognition signal 126.

The dirty bit search unit 27 inputs the monitor address for write back from the bus control unit 4 via the address line 124, and searches the tag address of the tag unit 24a and the valid bit of the valid bit unit 24b. To do.

The dirty bit search unit 27 is the bus control unit 4
If the monitor address from is valid in the directory 24, the address valid signal 122 is output, and at the same time, the dirty bit in the dirty bit portion 24c corresponding to the monitor address is invalidated.

The operation of the embodiment of the present invention will be described with reference to FIGS. Here, the read operation from the CPU 1 and the mishit operation at the time of the write operation are the same as in the conventional example, and therefore the description of those operations will be omitted.

During the write operation from the CPU 1, the comparator 25 in the cache memory unit 2 compares the address from the CPU 1 with the tag address in the tag unit 24a. Comparator 2
5 enables the hit signal 125 if there is a corresponding address in the tag portion 24b.

Therefore, the dirty bit search unit 27 uses the FIFO-FULL signal 13 from the write-back FIFO 3.
If 1 is recognized and the FIFO memory for address and data of the write-back FIFO 3 is not full, the FIFO write signal 121 is enabled for the write-back FIFO 3.

At the same time, the dirty bit search unit 27 validates the dirty bit of the corresponding block in the dirty bit unit 24c and outputs the dirty bit recognition signal 126 to the data memory control unit 26. Therefore, the content of the corresponding block of the data memory 21 is changed to the data memory controller 2
The data from the CPU 1 is rewritten under the control of 6.

On the other hand, the dirty bit search unit 27 receives the FIFO-FULL signal 131 from the write-back FIFO 3.
If the FIFO memory for address and data of the write-back FIFO 3 is full, the FIFO write signal 121 to the write-back FIFO 3 is not validated.

At the same time, the dirty bit search unit 27 validates the dirty bit of the corresponding block in the dirty bit unit 24c and outputs the dirty bit recognition signal 126 to the data memory control unit 26. Therefore, the content of the corresponding block of the data memory 21 is changed to the data memory controller 2
The data from the CPU 1 is rewritten under the control of 6.

At this time, in the write-back FIFO 3, if the FIFO write signal 121 from the cache memory unit 2 is valid, at the same time as the rewriting of the data memory 21 by the data from the CPU 1 in the cache memory unit 2,
CP in the internal FIFO memory for addresses and data
Write the address and write data from U1.

In the bus control unit 4, the write back FI
The FIFO-EMPTY signal 132 from the FO3 is recognized, and if the write-back FIFO3 has data, the FIFO read signal 141 is validated. As a result, the bus control unit 4 reads the write back address and data in the CPU 1 from the write back FIFO 3 and latches them internally.

At the same time, the bus control unit 4 outputs the address latched to the cache memory unit 2 as a monitor address to the cache memory unit 2 via the address line 124.

In the cache memory unit 2, the dirty bit search unit 27 refers to the contents of each of the tag unit 24a and the valid bit unit 24b and determines whether the address to be written back is valid in the cache memory unit 2.

When the cache memory unit 2 determines that the address to be written back is valid, the address valid signal 12
2 is output to the bus control unit 4, and at the same time, the dirty bit of the dirty bit unit 24c corresponding to the address is invalidated. At the same time that the bus control unit 4 receives the address valid signal 122, it issues a lowest priority request for write back to the main memory to the control bus 103.

In the cache memory unit 2, the dirty bit search unit 27 always searches for data that cannot be written because the address and data FIFO memories of the write-back FIFO 3 are full.

In the cache memory unit 2, when the dirty bit search unit 27 searches for a valid dirty bit, F
Writeback F by recognizing IFO-FULL signal 131
The FIFO memory of IFO3 is not full and the CPU
If 1 does not use the internal bus, the dirty bit recognition signal 126 from the dirty bit search unit 27 to the data memory control unit 26 is validated.

Therefore, when the data memory control unit 26 receives the dirty bit recognition signal 126, the write back data is read from the corresponding data memory 21, and the corresponding address is generated from the contents of the directory 24.
The internal address bus 111 and the internal data bus 1
Output to 12.

At the same time, in the cache memory unit 2, the dirty bit search unit 27 causes the write-back FIFO to be executed.
The FIFO write signal 121 to 3 is made valid. When the write-back FIFO 3 receives the FIFO write signal 121, it writes from the cache memory unit 2 to the internal address bus 11
1 and the address and data output to the internal data bus 112 are taken into the internal FIFO memory.

When replacement occurs, write-back at the time of replacement is performed only on the block corresponding to the effective dirty bit among the dirty bits in the dirty bit portion 24c.

In this case, if the write-back data of the block to be replaced still remains in the write-back FIFO 3, the bus control unit 4 checks the validity of the address read from the write-back FIFO 3 in the cache memory unit 2. It is sent to the cache memory unit 2 via the line 124.

In the cache memory unit 2, since the monitor address is input from the bus control unit 4 after the replacement, the contents of the data memory 21 are written back to the main memory. Therefore, the cache memory unit 2
Then, since the valid bit of the corresponding valid bit section 24b is invalid, the address valid signal 122 to the bus control section 4 is never valid.

Therefore, since the corresponding request for write back is not output from the bus control unit 4, both the address and data for write back stored in the write back FIFO 3 are discarded. This prevents overwriting of data in the main memory due to unnecessary writeback after replacement.

As described above, the CPU of the cache memory
The portion rewritten by 1 is sequentially stored in the write-back FIFO 3 under the control of the cache memory unit 2, and the write-back information stored in this write-back FIFO 3 is sent from the bus control unit 4 to the lowest priority request in its own device. By writing back to the main memory, it is possible to prevent the system bus from being unnecessarily occupied by the writing back to the main memory.

As described above, the blocks of the cache memory rewritten by the CPU 1 are sequentially stored in the write-back FIFO 3, and the write-back information stored in the write-back FIFO 3 is written back to the main memory by the lowest priority request. The write back to the main memory can be performed without stopping the operation of the CPU 1 and occupying the system bus unnecessarily. Therefore, the efficiency of the system can be improved, and an efficient cache memory system can be realized.

[0070]

As described above, according to the present invention, the data to be written back to the main memory device in the cache memory and its address are held in the FIFO, and these data and address are given the bus priority in the device. By writing back to the main storage device at the lowest frequency request, it is possible to write back to the main memory without stopping the operation of the CPU and without wastefully occupying the system bus. There is an effect that the efficiency of the system can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a cache memory unit in FIG.

FIG. 3 is a block diagram showing a configuration of a conventional example.

FIG. 4 is a block diagram showing a configuration of a cache memory controller of FIG.

[Explanation of symbols]

 1 CPU 2 cache memory unit 3 write-back FIFO 4 bus control unit 21 data memory 22, 23 decoder 24 directory 24a tag unit 24b valid bit unit 24c dirty bit unit 25 comparator 26 data memory control unit 27 dirty bit search unit

Claims (3)

[Claims] 1. A cache memory control circuit for controlling a write-back operation in which a write operation is performed only to a cache memory, and holding means for holding data to be written back to a main memory device in the cache memory and its address. And an issuing means for issuing a request for writing back the data and address to the main storage device when the data and address are held in the holding means, with the bus priority being the lowest. And a cache memory control circuit. 2. The cache memory according to claim 1, wherein the holding means comprises a first-in first-out memory which outputs data to be written back to a main storage device in the cache memory and addresses thereof in a storage order. Control circuit. 3. The issuing means stores in the cache memory a dirty bit indicating that the data block in the cache memory has been rewritten in the cache memory at the time of replacement for writing back the data block in the cache memory. 3. The cache memory control circuit according to claim 1, wherein the data is written back to the main storage device with priority over the data held in the holding means.