JP2011248389A - Cache memory and cache memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cache memory in which a cache hit rate has been further improved.SOLUTION: A cache memory 6 comprises: a data storage part 16 having lines including four words (Word0, Word1, Word2, and Word3); and a tag storage part 14 for storing a tag identifying each line. The tag storage part stores: refill bits (R) for indicating whether a line is being refilled; dirty bits (D0, D1, D2, and D3) indicating whether data for each word is dirty; and tag bits (Tag) indicating an address in a main storage for the data stored on a line. A hit determination unit 20 determines that it is a read hit if a tag address (AD [31:16]) for read access and an address indicated by a tag bit (Tag) are the same; a refill bit (R) corresponding to a line for a read access target is indicating that the line is being refilled; and a dirty bit corresponding to a word for the read access target on the line is indicating the word is dirty.

Description

The present invention relates to a write-back cache memory.

The write-back method is a method in which, when data is written to the cache memory, basically only the cache memory is written, and the main memory is not written at the same time, but is appropriately rewritten later.
In the write-back method, there is a deviation in the write timing to the cache memory and the main memory, so a Dirty / Clean flag is provided for managing the consistency of the data held by both. Dirty indicates that the data held in the cache memory is updated, etc., and cannot match the data on the main memory, and Clean indicates the opposite. The Dirty / Clean flag can be used to determine whether the target data is dirty or clean. Dirty data must be written back to main memory at an appropriate timing to ensure consistency.

Such a Dirty / Clean flag is generally managed in units of lines (consisting of several words). Of course, in the case of line units, it is unclear which word out of several words included in a line is Dirty, so unnecessary write back may be performed.
Therefore, in Patent Document 1, by managing the Dirty / Clean distinction in units smaller than lines (for example, word units), it is possible to write back only necessary data and reduce unnecessary bus transactions. Yes. In addition, the techniques of Patent Documents 2 to 4 are known.
JP 2003-108439 A Japanese Unexamined Patent Publication No. 2006-91995 JP-A-8-16467 JP-A-8-221270

The cache hit rate is generally improved by accessing the corresponding data on the high-speed cache memory instead of accessing the low-speed main memory. By improving the cache hit rate, the performance of the entire computer system can be improved.
In the cache memory, when a cache miss or the like is performed, a process called refill for exchanging line data is performed. Even during the refill, there is a possibility that there is no problem even if access is permitted by treating the cache hit. However, in the conventional technique, during refilling, access to the line being refilled is treated as a cache miss, and there is a problem that it is necessary to access the main memory.

  In view of such a background, an object of the present invention is to provide a cache memory having a further improved cache hit rate.

  The cache memory according to the present invention includes a plurality of lines each including a plurality of words, a tag indicating an address in the main memory of data stored in the line, and whether or not the line is being refilled for each line. A tag storage unit that stores a refill bit that is indicated and a dirty bit that indicates whether or not the data in the word is dirty for each word, a tag address that is a read access target, and an address indicated by the tag matches If the refill bit corresponding to the line related to the read access indicates that refilling is in progress and the dirty bit corresponding to the word related to the read access included in the line indicates dirty, the hit is determined as a read hit. And determining means.

In the case where the hit determination means indicates that the address of the line related to the write access and the address indicated by the tag match, and the refill bit corresponding to the line indicates that refill is being performed. It may be determined as a write hit.
The hit determination means may determine a read miss hit if the dirty bit corresponding to the word does not indicate dirty.

  Further, the cache memory according to the present invention includes a plurality of lines each including a plurality of words, a tag indicating an address in the main memory of data stored in the line, and whether the line is being refilled for each line. A tag storage unit that stores a refill bit indicating whether or not the data in the word is dirty for each word, a tag address that is a write access target, and an address indicated by the tag When the refill bit matches and indicates that the refill bit corresponding to the line is being refilled, a hit judging means for judging a write hit is provided.

  Further, when the hit determination means determines that a write hit occurs, if there is a write to a word related to the write access, the dirty bit corresponding to the word is asserted, and when the line is refilled, the dirty bit is dirty. There may be provided control means for permitting overwriting of data for a word that does not indicate presence, and prohibiting overwriting of data for a word indicating dirty by the assertion.

  The cache memory system according to the present invention is located in a hierarchy between the central processing unit, the cache memory, the central processing unit, the cache memory, and the storage hierarchy, and the central processing unit is transferred to the cache memory. The first write buffer that holds data to be written, the cache memory, the memory to be written back, and the storage hierarchy are located in a hierarchy, and write back from the cache memory to the memory to be written back A second write buffer that holds data to be read; and a read buffer that is located in a hierarchy between the cache memory, the memory to be written back, and a storage hierarchy and holds data to be read by the cache memory It is characterized by.

The cache memory according to the present invention has conventionally determined that a read miss hit when refilling is in progress, but the hit determination means supports a word included in the line even in the situation where the line is being refilled. If the dirty bit indicates dirty, it is determined as a read hit.
According to this configuration, even in a situation where the line related to the read access is being refilled, the hit determination means determines that it is a read hit. Therefore, the cache read miss can be reduced and the cache read hit rate can be improved. Thereby, the overhead of the computer resulting from a cache read miss can be reduced.

  Further, the cache memory according to the present invention includes a plurality of lines each including a plurality of words, a tag indicating an address in the main memory of data stored in the line, and whether the line is being refilled for each line. A tag storage unit that stores a refill bit indicating whether or not the data in the word is dirty for each word, a tag address that is a write access target, and an address indicated by the tag When the refill bits coincide with each other and indicate that the refill bit corresponding to the line is being refilled, hit judging means for judging a write hit is provided.

  According to this configuration, even in a situation where the line related to the write access is being refilled, the hit determination means determines that it is a write hit, so the cache write hit rate can be improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the write-back cache memory according to the present embodiment employs a direct map method, and in the case of a cache write miss, a write allocation method (first writing a new line to the cache memory and then a write hit It is assumed that the processing is performed in this method.

FIG. 1 is a configuration diagram of the cache memory system 1.
The cache memory system 1 includes a CPU 2, a main memory 4, a cache memory 6, write buffers 8 and 10, and a read buffer 12.
The CPU 2 is a central processing unit that performs various arithmetic processes.
The main memory 4 includes a volatile memory that temporarily stores data such as DRAM.

The cache memory 6 temporarily stores data to be stored in the main memory 4. The access speed is higher than that of the main memory 4 and is interposed between the upper CPU 2 and the lower main memory 4 due to the structure of the storage hierarchy. The cache memory 6 is a write-back method, and writes the data held in the main memory 4 when a cache miss occurs.
The cache memory 6 includes a control unit 6a, a storage unit 6b, a hit determination unit 6c, and an arbitration unit 6d.

The control unit (cache memory control unit) 6a controls each functional block, for example, reads / writes data stored in the storage unit 6b and updates tags. Further, data is output to the CPU 2 according to the hit determination result of the hit determination unit 6c.
The storage unit 6b includes a data storage unit that stores data, and a tag storage unit that includes a tag as information for identifying the stored data.

The hit determination unit 6c performs hit determination as to whether or not the data to be accessed from the CPU 2 is stored in the storage unit 6b. Details will be described later.
The arbitrating unit 6d arbitrates when access to data to the data storage unit in the storage unit 6b competes.
FIG. 2 is a diagram showing the configuration of the cache memory 6.

An address 22 in the upper part of FIG. 2 indicates an address output together with a read / write request from the CPU 2 when the CPU 2 tries to access the cache memory 6.
Address (AD [31: 0]) 22 is 32 bits, and the upper 16 bits (AD [31:16]) are used as tag addresses, and 12 bits (AD [15: 4]) from bit 4 to bit 15 are used. As an index address, 2 bits (AD [3: 2]) from bit 2 to bit 3 are used as a word address for specifying a word included in the line. Since the index address is 12 bits, 4096 (= 2 ^ 12) lines can be specified. A line to be accessed is uniquely specified by this index address.

The cache memory 6 includes a tag storage unit 14, a data storage unit 16, a selector 18, and a hit determination unit 20.
The tag storage unit 14 is provided corresponding to 4096 lines in the data storage unit 16 and stores identification information such as data stored in the line.
Specifically, the tag storage unit 14 stores a valid bit (V) indicating whether or not line data is valid, a refill bit (R) indicating whether or not the line is being refilled, and the line. It has a tag bit (Tag) indicating the address of the main data in the main memory.

  In addition to this, the tag storage unit 14 includes four dirty bits (D0, D1, D2, D3) respectively provided corresponding to four words (Word0, Word1, Word2, Word3) included in the line. It is out. If the dirty bit is dirty, it means that the corresponding word has been updated but not yet written back to the main memory. Therefore, it is necessary to write back to the main memory as appropriate.

  The data storage unit 16 holds 4096 lines with four words as one line. The data storage unit 16 includes an SRAM or the like as a memory separate from the tag storage unit 14. The size per word is 32 bits corresponding to the bit width of access from the CPU 2, and the bit width of the input / output port of the data storage unit 16 is also 32 bits (for one word).

The selector 18 selects one word out of the four words based on 2 bits (AD [3: 2]) of the address 22.
The hit determination unit 20 includes a valid bit (V) of a line specified by a read or write signal (Read or Write), a tag address (AD [31:16]), and an index address (AD [15: 4]). ), Refill bit (R), dirty bit (D0, D1, D2, D3) for each of four words, tag bit (Tag) indicating the address of data stored in the above line, one of the four words It is determined whether it is a hit or a miss hit based on 10 inputs of a word address (AD [3: 2]) that identifies

A circuit configuration example of the hit determination device 20 is shown in FIG.
The hit determination unit 20 includes AND circuits 23, 24, 26, 28, and 30 having two inputs and one output, an OR circuit 32 having three inputs and one output, NOT circuits 34 and 36, a selector 38 having four inputs and one output, and a comparator 40. .
The selector 38 selects and outputs one of four of D0, D1, D2, and D3 based on the input of 2 bits (AD [3: 2]). That is, based on an input (AD [3: 2]) that specifies an access target word included in the line, a dirty bit corresponding to the word is output.

The comparator 40 compares the tag bit (Tag) with the tag address (AD [31:16]) and outputs a HIGH output when they match.
FIG. 4 is a table 50 showing determination results output by the hit determination unit 20 of FIG. 3 in response to input.
There are eight cases from (a) to (h) depending on combinations of input values. Each case will be described in turn. Note that hit determination in cases (a), (b), (d), (e), (f), and (h) that are not being refilled is basically the same as in the prior art. The cases (c) and (g) during refill are characteristic.

  In the case of (a): The tag address (AD [31:16]) included in the address 22 of the write access target data matches the tag bit (Tag), and the refill is not in progress (R = 0). This is a case where the valid bit is valid (V = 1) and a write hit occurs. Then, the cache memory 6 writes to the word indicated by the word address (AD [3: 2]) and asserts a dirty bit corresponding to the simultaneously written word.

In the case of (b): Only the place where the valid bit is invalid (V = 0) is different from that in (a). Since the data is invalid at V = 0, a write miss occurs.
Here, the write miss hit data is temporarily held in the write buffer 8 and written to the cache memory 6 after completion of the refill. In particular, in the present embodiment, the write miss hit data is written in the cache memory 6. At the time of writing, the dirty bit for each written word is updated to dirty, and the tag bit (Tag) is updated to the address of the access that caused the write miss hit. Prior to this, a data read request and an address are output to the bus to the main memory 4 in order to refill the write access target line. At this time, if there is no free space in the read buffer 12, it waits until the read request is output or until it is determined that the read buffer 12 is free before the read data is returned from the main memory 4. Wait for read request output.

In the case of (c): The tag bit (Tag) of the write access target data matches the tag address (AD [31:16]) and refilling is in progress (R = 1). Become. Then, the cache memory 6 writes to the word indicated by the word address (AD [3: 2]) and asserts a dirty bit corresponding to the written word.
In the case of (d): The tag bit (Tag) of the data subject to read access matches the tag address (AD [31:16]), not being refilled (R = 0), and the valid bit is valid ( V = 1), which is a read hit. The CPU 2 reads the data of the word indicated by the word address (AD [3: 2]).

In the case of (e): Only the place where the valid bit is invalid (V = 0) is different from that in (d). Since the data is invalid at V = 0, a read error occurs.
In the case of (f): The tag bit (Tag) of the read access target data matches the tag address (AD [31:16]), refilling is in progress (R = 1), and the word address (AD [ 3: 2]) is a case where the dirty bit (D0 in FIG. 4) corresponding to the word (W0 in FIG. 4) is not dirty (clean). In this case, a miss hit occurs, and the control unit 6a of the cache memory 6 notifies the CPU 2 that refilling is in progress. The CPU 2 waits until the notification is no longer being refilled (waits until the refill is completed), and performs a read hit operation (reads the refilled read access target data) as a read hit after the refill is completed, or the missed read Even if the access is not completed, the process proceeds to the subsequent process.

  In the case of (g): The tag bit (Tag) of the read access target data matches the tag address (AD [31:16]), refilling is in progress (R = 1), and the word address (AD [ 3: 2]) is a case where the dirty bit (D2 in FIG. 4) corresponding to the word (W2 in FIG. 4) is dirty. In this case, a read hit occurs, and the CPU 2 reads the data of the word indicated by the word address (AD [3: 2]).

In the case of (h): This is a case where the tag bit (Tag) and the tag address (AD [31:16]) do not match. This means that the address of the data to be accessed is different from the address of the data that is actually stored in the data storage unit, so it is not necessary to judge other conditions. It becomes.
As described above, the hit determiner 20 determines a read hit if the dirty bit corresponding to the read access target word is dirty even if refilling is in progress as in (g). As a result, the read hit rate can be improved.

Moreover, since the hit determination unit 20 determines as a write hit even if refilling is in progress as in the case of (c), the write hit rate can be improved as compared with the prior art.
Next, the processing flow of the CPU 2, the cache memory 6, and the main memory 4 will be described in order for write access and read access separately.
FIG. 5 is a sequence diagram of the CPU 2, the cache memory 6, and the main memory 4 at the time of write access. In the initial state, it is assumed that the line that is the target of the write access request is not being refilled (R = 0).

Data requested by the CPU 2 for write access is temporarily held in the write buffer 8. The write buffer 8 sends the data and the address (AD [31: 0]) 22 of the data to the cache memory 6 together with the write access request to the cache memory (S0).
The hit determination unit 20 of the cache memory 6 that has received the write access request, as described above, the tag address (AD [31:16]) of the address (AD [31: 0]) 22 of the data sent from the write buffer 8 as described above. Is compared with the tag bit (Tag) of the line of the data subject to the write access request, and the hit determination is performed based on the refill bit (R) of the line.

If it is determined as a write hit (S1: Yes), data is written to the word of the line that is the target of the write access request, and a dirty bit corresponding to the word is asserted as necessary (S11).
If it is determined that there is a write miss (S1: No), the cache memory 6 asserts the refill bit of the line (S2: R = 1), and proceeds to the write back process (S3-S8). At this time, the tag bits (Tag) are updated with the tag address (AD [31:16]) of the write access request in which the write miss occurred.

In the write-back process (S3-S8), if the valid bit is invalid (S3: No, V = 0), the line is invalid and there is no data to be written back, and the process ends.
If the valid bit is valid (S3: Yes, V = 1), only the word in the line where the dirty bit corresponding to the word is dirty (D = 1) is written back to the write buffer 10 (S4, S5). ). The dirty bit corresponding to the word that has been written back is negated cleanly (D = 0) (S6).

Note that the data written back to the write buffer 10 is further written back to the main memory 4 at an appropriate timing such as when the bus is free.
When the processing from S4 to S6 is completed for the four words included in the line (S7: Yes), the valid bit of the line is invalidated (S8: V = 0).
When the write back process (S3-S8) is completed, the cache memory 6 performs refill / tag update (S9). Specifically, the read buffer 12 overwrites the line of the cache memory 6 with the data of the write access target line that has been read from the main memory 4.

In this refill, only words with D = 0 are overwritten, and overwriting of unwritten words is avoided.
When the reading from the read buffer 12 is completed (S9), the cache memory 6 validates the line (S10: V = 1), negates the refill bit (S10: R = 0), and ends a series of refills.

In the flow of FIG. 5, the write back process (S3-S8) is performed first, and then the refill process is performed (S9). However, both processes are not limited to this and may be performed in parallel. I do not care.
FIG. 6 is a sequence diagram of the CPU 2, the cache memory 6, and the main memory 4 at the time of read access. In the initial state, it is assumed that the line that is the target of the read access request is not being refilled (R = 0).

When the CPU 2 requests read access to the cache memory 6 (S20), the cache memory 6 that has received the request performs the hit determination described above in the hit determination unit 20.
If it is determined as a read hit (S21: Yes), the CPU 2 reads data from the word of the line that is the target of the read access request.
If it is determined as a read miss hit (S21: No), the process proceeds to a refill process from S2 to S10. Since this process is the same as that already described with reference to FIG.

Next, an example when a line in the cache memory 6 is being refilled and there is a write / read access to a word in this line will be described.
FIG. 7 is a diagram for explaining the refill of words (W0, W1, W2, W3) on a certain line in time series. The process at the time of write access will be described using (a), and the process at the time of read access will be described using (b).

At the time of write access, as shown in FIG. 7A, the cache memory 6 completes refilling in the order of W0 → W1 → W2 → W3 during t0 → t1 → t2 → t3 → t4. To do. At the start of refill, the refill bit is asserted, and the line tag bit (Tag) is updated to the address of the new line to be refilled.
In this embodiment, the write access request is accepted in the middle of refilling and data overwriting is allowed, so that the tag bit (Tag) of the line does not coincide with the tag of the actually overwritten data. As shown in FIG. 7A, the tag is updated at the start of refilling.

  First, if there is a write access request to the word W2 between t0 and t2, the hit determination unit 20 determines that it is a write hit as described above, and receives the write access to the word W2 to receive the corresponding dirty. Assert bit (D2). Thereafter, since the dirty bit (D2) of the word W2 is asserted between t2 and t3, the cache memory 6 does not overwrite the word W2.

As a method of not performing overwriting, for example, it is conceivable to use a signal that masks writing to a word while performing write access. Further, the processing may be skipped without performing write access to the word itself.
Next, if there is a write access request to the word W2 between t2 and t3, it is determined as a write hit, and the corresponding dirty bit (D2) is asserted in response to the write access to the word W2. In this case, since the word W2 is already being refilled at the time of a write access request, the cache memory 6 arbitrates write control to prevent conflict between the two.

If there is a write access request to the word W2 between t3 and t4, it is determined as a write hit, and the corresponding dirty bit (D2) is asserted in response to the write access to the word W2.
At the time of read access, as shown in FIG. 7B, as in FIG. 7A, the cache memory 6 is in the order of W0 → W1 → W2 → W3 during t0 → t1 → t2 → t3 → t4. It is assumed that refilling is completed in order.

First, if there is a read access request to the word W2 between t0 and t4, if the dirty bit corresponding to the word W2 is valid, the hit determination unit 20 determines a read hit as described above, and Accept read access to word W2.
On the other hand, if there is a read access request to the word W2 between t0 and t4 and the dirty bit corresponding to the word W2 is invalid, the hit determination unit 20 determines that it is a read miss hit as described above. To do. The CPU 2 waits until the refill is completed.

<Supplement>
As mentioned above, although embodiment of this invention was described, this invention is not limited to said content, It can implement also in the various forms for achieving the objective of this invention, the objective related to it, or an incidental, for example, It may be the following.
(1) In the embodiment, the direct map type cache memory has been described as an example. However, the present invention is not limited to this type, and a cache memory employing a full associative method or a set associative method may be used. In these methods, the line to be refilled at the time of a write miss hit is not determined as a unique line as in the direct map method, but based on algorithms such as the LRU (Least Recently Used) method and the round robin method. Is different.

The present invention is also applied as a method for configuring and controlling a write-back cache memory in a shared memory type cache memory system in which a plurality of cache memories share a single lower layer memory via a shared bus. be able to.
(2) In the embodiment, an example of writing back only a word having a dirty bit corresponding to the dirty bit has been described. However, several words including a dirty word or all words included in a line may be written back. At the time of writing back, the data at the address to be written back is read from the main memory 4 before the data accumulated in the write buffer 10 is written back to the main memory 4 as in a known technique. The entire system can be controlled so that there is no.

  (3) In the embodiment, as shown in FIG. 1, write access from the central processing unit to the cache memory is performed by arranging the write buffers 8 and 10 and the read buffer 12 in the path connected to the input / output of the cache memory 6. The write access from the cache memory to the main memory and the write access from the main memory to the cache memory are buffered, so that more flexible cache memory control is possible.

  (4) Although no particular details have been described in the embodiment, it is conceivable to devise the control system by arranging a write buffer as another approach for reducing the overhead of the entire system. Specifically, in response to a write miss, a multi-functional write buffer is placed between the upper layer memory and the cache memory, and writing to the line being refilled overwrites the data in the write buffer. The update of the line being refilled is read out from the write buffer. However, this control is very complicated.

On the other hand, in the embodiment, it is possible to reduce overhead for the entire system through simple control of hit determination of the hit determination unit 20.
(5) Although the configuration of the central processing unit, the cache memory, and the main memory is illustrated as the hierarchical memory system, it may be a cache memory of a memory system having a deeper hierarchical configuration. For example, the cache memory may be composed of a primary cache memory and a secondary cache memory. In this case, the present embodiment may be applied to a primary cache memory or a secondary cache memory.

  The cache memory of the present invention can be used as a cache memory existing in a general semiconductor circuit and is useful because it can improve the cache hit rate.

Configuration diagram of cache memory system 1 The figure which shows the structure of the cache memory 6 Circuit configuration example of hit determination unit 20 FIG. 50 is a table 50 showing determination results output by the hit determination device 20 of FIG. 3 according to input. Sequence diagram of CPU 2, cache memory 6, and main memory 4 during write access Sequence diagram of CPU 2, cache memory 6, and main memory 4 during read access Diagram explaining the refill of a word (W0, W1, W2, W3) on a line in time series

Explanation of symbols

1 cache memory system 2 CPU
4 Main memory 6 Cache memory 8 Write buffer 10 Write buffer 12 Read buffer 14 Tag storage unit 20 Hit determiner 22 Address

Claims (6)

Multiple lines, each containing multiple words,
A tag indicating the address in the main memory of the data stored in the line, a refill bit indicating whether or not the line is being refilled for each line, and whether or not the data in the word is dirty for each word A tag storage unit for storing a dirty bit indicating
The tag address of the read access target matches the address indicated in the tag,
The refill bit corresponding to the line related to the read access target indicates that refill is being performed,
And, if the dirty bit corresponding to the word related to the read access target included in the line indicates dirty,
A cache memory comprising: hit determination means for determining a read hit. The hit determination means writes a write when the address of the line related to the write access and the address indicated by the tag match and the refill bit corresponding to the line indicates that refill is being performed. The cache memory according to claim 1, wherein the cache memory is determined to be a hit. 2. The cache memory according to claim 1, wherein the hit determination means determines a read miss hit if the dirty bit corresponding to the word does not indicate dirty. Multiple lines, each containing multiple words,
A tag indicating the address in the main memory of the data stored in the line, a refill bit indicating whether or not the line is being refilled for each line, and whether or not the data in the word is dirty for each word A tag storage unit for storing a dirty bit indicating
The tag address for write access matches the address indicated in the tag,
If the refill bit corresponding to the line indicates that it is being refilled,
A cache memory comprising: hit determination means for determining a write hit. Further, when it is determined as a write hit by the hit determination means, if there is a write to a word related to the write access, a dirty bit corresponding to the word is asserted,
Control means for permitting overwriting of data for a word whose dirty bit does not indicate dirty, and prohibiting overwriting of data for a word indicating dirty by the assertion when refilling a line The cache memory according to claim 4, further comprising: A central processing unit;
The cache memory according to claim 1 or 4,
A first write buffer located in a hierarchy between the central processing unit and the cache memory and the storage hierarchy, and holding data to be written to the cache memory by the central processing unit;
A second write buffer located in a hierarchy between the cache memory and the memory to be written back and the storage hierarchy, and holding data to be written back from the cache memory to the memory to be written back;
A cache memory system comprising: a read buffer that is located in a hierarchy between the cache memory, the memory to be written back, and a storage hierarchy and holds data to be read by the cache memory.

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