JPH07270500A - Integrated circuit and test mode setting method therefor - Google Patents

Abstract

PURPOSE:To provide a proper test mode setting method for integrated circuit. CONSTITUTION:Data 19 in a data bus is fed to a control data decoder 5 via the first register 3. The decoder 5 operates to decode and feed the internal control data 21 of the data 19 to a random logic circuit 15. Also, the decoder 5 extracts test mode data 23 and a test flag 25 from the data 19 for transmission to an AND circuit 7. This circuit 7 feeds a value of 0 to the second register 9, when the test flag 25 is 0, while sending test mode data 23 thereto when the flag 25 is 1. The next stage test mode decoder 11 of the second register 9 judges that no test mode exists when output from the circuit 7 is 0, and sends relevant information to a test circuit 13. Furthermore, when output from the circuit 7 corresponds to the test mode data 23, the decoder 11 decodes the data 23 and determines test mode. The test circuit 13 causes a logic circuit 15 to implement a test according to a test execution signal 27 and the test mode from the decoder 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit, and more particularly to a test mode setting method for this integrated circuit.

[0002]

2. Description of the Related Art Before showing a conventional example, an example of control by a data bus will be shown. As shown in FIG. 8, the address indicating the integrated circuits 203, 205 and 207 from the microcomputer 201,
An address indicating each control item and a plurality of control amounts are collected into one data, which is placed on a data bus and sent to each integrated circuit 203, 205, 207 together with a clock. Each integrated circuit 20
3, 205 and 207 are controlled by a command from the microcomputer 201. As an example of this control,
When these integrated circuits 203, 205, and 207 are used in a television receiver, control is performed on the level of color signals and the level of luminance signals.

FIG. 6 shows a conventional test mode setting method for an integrated circuit. The integrated circuit 101 includes a first register 103 for data 117 of a data bus such as a plurality of control data sent from a data bus, a control data decoder 105, a second register 107 for test mode data, a test mode decoder. 109, a test circuit 111, and a random logic circuit 113 which is an internal circuit of the integrated circuit 101.

External microcomputer (not shown)
From the data bus, a plurality of control data 119 are sent, and these are stored in the first register 103. The accumulation timing at this time is the clock 115 from the microcomputer. Control data decoder 105
Is the data bus data 119 from the first register 103.
Is decoded and supplied to the random logic circuit 113,
For example, the level of the color signal and the level of the luminance signal are controlled.

Data 11 on the data bus such as the control data
Aside from 7, the test mode data 121 is
It is supplied to the register 107 of and is stored there. The test mode decoder 109 determines the test mode according to the test mode data 121 and sends it to the test circuit 111. The test circuit 111 receives an external test execution signal 123
Are supplied, and the test execution signal 123 activates the test circuit 111. The test circuit 111 switches each signal path of the random logic circuit 113 according to the above-mentioned test mode to test.

However, in this conventional example, since each is independent, an input pin is required for setting the test mode, which leads to an increase in the number of pins and an increase in cost. If the normal operation mode and the test mode are set incorrectly, a malfunction will occur.

FIG. 7 shows another conventional test mode setting method for an integrated circuit. The integrated circuit 101 includes a plurality of control data 119 and test mode data sent via the data bus.
First register 1 for data 117 on the data bus including 121
03, control data decoder 105, test mode data 121
Second register 107 for test mode decoder 109
The test circuit 111 includes a random logic circuit 113 which is an internal circuit of this integrated circuit.

External microcomputer (not shown)
From the data bus, a plurality of control data 119 and test mode data 121 are sent, and these are sent as the first data.
It is stored in the register 103 of. The accumulation timing at this time is the clock 115 from the microcomputer. The control data decoder 121 decodes the control data 119 of the data 117 of the data bus from the first register 103 and supplies it to the random logic circuit 113 to control, for example, the color signal, the level, the level of the luminance signal, and the like. . The control data decoder 105 also extracts the test mode data 121 from the data 117 on the data bus and outputs it as the second data.
It is supplied to the test mode decoder 109 via the register 107 of

The test mode decoder 109 determines a test mode according to the test mode data 121 and sends it to the test circuit 111. A test execution signal 123 is supplied to the test circuit 111 from the outside, and the test circuit 111 enters an operating state by this test execution signal 123. Test circuit
111 switches each signal path of the random logic circuit 113 according to the above-mentioned test mode to test.

In the case of this conventional example, an input pin for setting the test mode is unnecessary, but since the setting of the normal mode and the setting of the test mode are on the same data bus, the setting of the test mode and the normal operation mode are performed. If the setting is wrongly set, the random logic circuit 113 may change to the test operation during the normal operation.

[0011]

In the conventional test mode setting method for an integrated circuit, an input pin is required for setting the test mode, which leads to an increase in the number of pins and an increase in cost. Further, if the normal operation mode and the test mode are set incorrectly, the random logic circuit may malfunction.

Other conventional integrated circuit test setting methods do not require an input pin for setting a test mode, but since the normal operation mode setting and the test mode setting are on the same data bus, the test If the setting of the mode and the setting of the normal operation mode are mistaken, the random logic circuit may change to the test operation during the normal operation.

It is an object of the present invention to provide an integrated circuit having a configuration capable of preventing an increase in the number of input pins and making an appropriate test mode setting. Another object of the present invention is to provide an appropriate test mode setting method for an integrated circuit.

[0014]

[Means for Solving the Problems]

(Structural example) An integrated circuit for receiving data on a data bus having one or more control data, test mode data, and a test flag, the first storage means for accumulating the data on the data bus, and the first storage means. Control data decoding means for decoding the control data contained in the data of the data bus from the storage means and supplying it to an internal circuit, and extracting the test mode data and the test flag from the data of the data bus; Judgment means for judging whether to execute a test from the test mode data from the control data decoding means and the test flag, and outputting the test mode data when the test is executed, and the test mode data from the judgment means. Second storage means for accumulating data and decoding the test mode data from the second storage means A test mode decode unit that comprises a test means for testing said internal circuit in a test mode set by the test mode decode means.

(Test mode setting method) Data bus generating means for generating data of data bus having one or more control data, test mode data, and test flag, and data of data bus from this data bus generating means are accumulated. The first storage means and the control data included in the data of the data bus of the first storage means are decoded and supplied to the internal circuit of the integrated circuit, and the test mode data is selected from the data of the data bus. And control data decoding means for extracting the test flag, and whether or not to execute a test from the test mode data and the test flag from the control data decoding means, and outputs the test mode data when the test is executed. Judging means and second storage means for accumulating the test mode data from the judging means Comprises the test mode decoding means for decoding the test mode data from the second storage means, and testing means for testing the internal circuit of the integrated circuit in the test mode set by the test mode decode means.

[0016]

The data on the data bus includes one or more control data, test mode data, and a test flag. The control data decoder extracts the test mode data and the test flag from the bus data,
Both are supplied to the determination means.

The determination means determines whether or not to execute a test from the input test mode data and the test flag, outputs the test mode data at the time of test execution, and outputs the test mode data via the second storage means. To the test mode decoder means.

As a result, it is possible to prevent a malfunction due to a mistake in setting the mode of the data bus and a malfunction due to noise of data on the data bus.

[0019]

1 shows a first embodiment of a test mode setting method for an integrated circuit according to the present invention, and FIG. 2 shows a flowchart of its operation. The integrated circuit 1 includes a first register 3 for data 19 of a data bus including a plurality of control data 21, test mode data 23 and a test flag 25, a control data decoder 5, an AND circuit 7, and a first register for test mode data 23. 2 register 9, test mode decoder 11, test circuit 13, random logic circuit 15 which is an internal circuit of this integrated circuit 1.
Built in.

The data 19 of the data bus supplied to the first register 3 includes a plurality of control data 21, test mode data 23, and a test flag for determining whether the operation is a test or a normal operation.
Contains 25. Data format of the data bus, for example, when increasing the I ² C BUS which is currently the mainstream as an example, slave address as shown in FIG. 3, sub-address, and a data A, B. The slave address of this data is a unique address assigned to one integrated circuit. The sub address indicates each control item. Data A and B are control amounts of control items defined by subaddresses. 1 bit after slave address, sub address, data A and B is AC
Data called K is data that returns a flag indicating that the transfer has been performed to the microcomputer.

Here, a control item called TEST is provided at a certain subaddress, for example N (arbitrary address), and the test mode data 23 is assigned to the data designated by the subaddress.
And the test flag 25 are provided as a set. For example, when the test flag is 1, the test mode is set, and when the test flag is 0, the normal operation mode is set.

In FIG. 1, the data 19 of the data bus according to the above-mentioned I ² C BUS system is supplied to the first register 3. The first register 3 stores a plurality of control data 21, test mode data 23 and a test flag 25. The accumulation timing at this time is the clock 17 from an external microcomputer (not shown). And the first
Register 3 has a capacity sufficient to store the data 19 of the input data bus.

The control data decoder 5 decodes the control data 21 of the data 19 of the data bus from the first register 3 and supplies it to the random logic circuit 15, for example, the level of the color signal or the level of the luminance signal. To control. The control data decoder 5 also extracts the test mode data 23 and the test flag 25 from the data 19 of the data bus and supplies them to the AND circuit 7.

The AND circuit 7 takes the AND of these two inputs to determine whether or not to execute the test. When the test flag 25 is 0, the test mode data is set to 0 and sent to the second register 9. When the test flag 25 is 1, the AND circuit 7 outputs the test mode data 23 and supplies it to the second register 9. That is, the AND circuit 7 outputs the test mode data 23 only when the test is executed.

The second register 9 stores the output from the AND circuit 7. The timing of this accumulation is either the internal clock or the clock 17 from the microcomputer.

When the output from the AND circuit 7 is 0, the second
The test mode decoder 11 at the next stage of the register 9 determines that it is not in the test mode and sends the information to the test circuit 13. As a result, the test circuit 13 does not test the random logic circuit 15 and sets the random logic circuit 15 in the normal operation mode. When the output from the AND circuit 7 is the test mode data 23, the test mode decoder 11 decodes the test mode data 23, determines the test mode, and sends it to the test circuit 13. A test execution signal 27 is supplied to the test circuit 13 from the outside, and the test execution signal 27 puts the test circuit 13 into an operating state. The test circuit 13 switches each signal path of the random logic circuit 15 according to the test mode,
Have 15 tested. Then, when the test execution signal 27 is not supplied, the test circuit 13 does not operate and the random logic circuit 15 does not perform the test.

The flow chart of the series of operations is shown in FIG.
Shown in.

In this way, the AND circuit 7 and the test execution signal 27 provide multiple guards against the random logic circuit 15 erroneously shifting to the test mode regardless of the normal operation mode. As described above, it is possible to prevent a malfunction due to a mistake in setting the mode of the data bus and a malfunction due to noise of data on the data bus.

FIG. 4 shows a second embodiment of the test mode setting method for an integrated circuit according to the present invention. The same components as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. The difference from FIG. 1 is that instead of the AND circuit 7,
First and second inverter circuits 31, 33 and NOR circuit 35
Is the point that adopted.

That is, the test mode data 23 extracted by the control data decoder 5 is supplied to the first inverter circuit 31 to invert the polarity. Then, the test flag 25 extracted by the control data decoder 5 is supplied to the second inverter circuit 33 to invert the polarity. The outputs of the first and second inverter circuits 31 and 33 are supplied to the NOR circuit 35, and the output of this NOR circuit 35 is supplied to the second register 9.

Even in this case, the test flag is the same as in FIG.
When 25 is 0, the NOR circuit 35 outputs 0.
When the test flag 25 is 1, the NOR circuit 35 outputs the test mode data 25.

Also in this example, it is possible to prevent a malfunction due to a mistake when setting the mode of the data bus and a malfunction due to noise of the bus data of the data bus.

FIG. 5 shows a third embodiment of the test mode setting method for an integrated circuit according to the present invention. The same components as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. The difference from FIG. 1 is that a third register 41 is adopted instead of the AND circuit 7.

That is, the third register 41 uses the test flag 25 extracted from the control data decoder 5 as a capture pulse, and receives the test mode data 23 extracted from the control data decoder 5. Then, the third register 41 takes out the test mode data 23 and supplies it to the second register 9 only when the test flag 25 is 1.

Also in this example, it is possible to prevent a malfunction due to a mistake when setting the mode of the data bus and a malfunction due to noise of the bus data of the data bus.

In the first to third embodiments, the data bus may be either a serial data system or a parallel data system.

[0037]

According to the present invention, with a comparatively simple structure, multiple guards are applied to the setting of the test mode of the integrated circuit, and stable operation can be guaranteed without entering the test mode during normal operation. it can.

Further, it is possible to prevent a malfunction due to a mistake in setting the mode of the data bus and a malfunction due to noise of bus data of the data bus.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of a test mode setting method for an integrated circuit according to the present invention.

FIG. 2 is a flowchart illustrating the operation of the first embodiment of FIG.

FIG. 3 is a diagram showing a data format of I ² CBUS used in the present invention.

FIG. 4 is a diagram showing a second embodiment of the test mode setting method for the integrated circuit of the present invention.

FIG. 5 is a diagram showing a third embodiment of the test mode setting method for the integrated circuit of the present invention.

FIG. 6 is a diagram showing a conventional test mode setting method for an integrated circuit.

FIG. 7 is a diagram showing another conventional test mode setting method for an integrated circuit.

FIG. 8 is a diagram showing an example of control by a data bus.

[Explanation of symbols]

1 ... Integrated circuit, 3 ... First register, 5 ... Control data decoder, 7 ... AND circuit, 9 ... Second register, 11 ... Test mode decoder, 13 ... Test circuit, 15 ... Random logic circuit, 31 ... 1 inverter circuit, 33 ... 2nd inverter circuit, 35 ... NOR circuit, 41 ... 3rd register.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 27/04 21/822

Claims (12)

[Claims] 1. An integrated circuit for receiving data on a data bus having one or more control data, test mode data, and a test flag, comprising: first storage means for storing the data on the data bus; Control data decoding means for decoding the control data included in the data of the data bus from the storage means and supplying it to an internal circuit, and extracting the test mode data and the test flag from the data of the data bus, Judgment means for judging whether to execute a test from the test mode data from the control data decoding means and the test flag, and outputting the test mode data at the time of test execution, and the test mode from the judgment means. Second storage means for accumulating data, and the test mode data from the second storage means Integrated circuit, characterized the test mode decode means for over-de, by comprising a testing means for testing said internal circuit in a test mode set by the test mode decode means. 2. The integrated circuit according to claim 1, wherein the determining means comprises AND means for inputting the test mode data and the test flag. 3. The determining means includes first inverter means for inverting the test mode data, second inverter means for inverting the test flag, and NOR of outputs of the first and second inverter means. 2. The integrated circuit according to claim 1, further comprising NOR means for obtaining 4. The determination means is a register which receives the test mode data and the test flag and outputs the test mode data when the test flag indicates execution of a test. 1. The integrated circuit according to 1. 5. The integrated circuit according to claim 1, wherein the test means is supplied with a test execution signal for bringing the test means into an operating state. 6. The first and second storage means are each configured by a register.
Or the integrated circuit according to 3 or 4 or 5. 7. A data bus generation means for generating data of the data bus having one or more control data, test mode data and a test flag, and a first memory for accumulating data of the data bus from the data bus generation means. Means for decoding the control data contained in the data of the data bus of the first storage means and supplying the decoded data to the internal circuit of the integrated circuit, and selecting the test mode data and the test flag from the data of the data bus. A control data decoding means for extracting the test mode data, a determination means for determining whether to execute a test from the test mode data and the test flag from the control data decoding means, and a means for outputting the test mode data at the time of test execution, Second storage means for accumulating the test mode data from the determination means, and the second storage means. Of the integrated circuit comprising: a test mode decoding means for decoding the test mode data from the test circuit; and a test means for testing the internal circuit of the integrated circuit in a test mode set by the test mode decoding means. Test mode setting method. 8. The test mode setting method for an integrated circuit according to claim 7, wherein the determination means comprises AND means for inputting the test mode data and the test flag. 9. The determining means includes first inverter means for inverting the test mode data, second inverter means for inverting the test flag, and NOR of outputs of the first and second inverter means. 8. The test mode setting method for an integrated circuit according to claim 7, further comprising NOR means for obtaining the above. 10. The determination means is a register which receives the test mode data and the test flag and outputs the test mode data when the test flag indicates execution of a test. 7. A test mode setting method for an integrated circuit according to 7. 11. The test mode setting method for an integrated circuit according to claim 7, wherein a test execution signal for bringing the test means into an operating state is supplied to the test means. 12. The test mode setting method for an integrated circuit according to claim 7, wherein the first and second storage means are each configured by a register.