JPH07263673A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To form a punch through stopper of small source/drain capacitance, regarding the manufacturing method of a FET having a punch through stopper just under a gate electrode. CONSTITUTION:The title method comprises a step of forming a gate electrode 4 on a substrate 1, a step where ions are selectively implanted by applying a gate electrode to a mask, and a source region 6 and a drain region 7 doped with first impurities are formed on the substrate 1 surface on both sides of the gate electrode 4, a step where second impurities having conductivity type opposite to the first impurities are implanted in the substrate 1 surface on which the gate electrode 4 is formed, and a punch through stopper 10a doped with the second impurities which passed the gate electrode 4 is formed just under the gate electrode 4, and a high voltage ion implantation process wherein the deep parts just under the source region 6 and the drain region 7 are doped with the second impurities implanted in forming regions of the source region 6 and the drain region 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a method for forming a punch-through stopper layer having a structure having a small parasitic capacitance in a field effect transistor in a self-aligned manner, and a structure for such a field effect transistor.

In a fine field-effect transistor, a depletion layer extends from the source and drain regions along the channel region to prevent punch-through that causes a short circuit between the source and drain. Is provided.

However, the punch-through stopper extending below the source and drain regions increases the parasitic capacitance of the source and drain and deteriorates the characteristics of the field effect transistor. Further, the structure of the punch-through stopper for avoiding the increase of such parasitic capacitance is difficult to be applied to the production process of a semiconductor device which is normally used.

Therefore, there is a demand for a semiconductor device and a manufacturing method thereof, which can be applied to a punch-through stopper having a structure having a small parasitic capacitance in a normal manufacturing process and which can be formed by a self-alignment technique which is excellent in mass productivity. .

[0005]

2. Description of the Related Art Conventionally, a punch-through stopper for a field effect transistor is produced by ion-implanting a constant depth over the entire element formation region and forming an impurity-embedded layer at a constant depth from the surface. It had been. Hereinafter, a method for forming such a conventional punch-through stopper will be described.

FIG. 2 is a sectional view of a conventional example showing a section of a field effect transistor. First, referring to FIG. 2A, an element isolation region 2 is formed on the surface of a semiconductor substrate 1 by selective oxidation, and the element formation region 1 thus isolated is formed.
1 is formed. Next, the surface of the substrate 1 is exposed in the element formation region 11, and this is thermally oxidized to form the gate insulating film 3.

Next, referring to FIG. 2B, after applying a resist, an opening for exposing the entire element forming region 11 is formed in the resist by photolithography to form an ion implantation mask 8. To do.

Next, using this ion implantation mask 8, a second impurity, which is a dopant for the punch-through stopper, is ion-implanted, and the second impurity is formed in the vicinity of the depths of the source and drain regions directly under the entire surface of the element formation region. 21a is doped.

Next, referring to FIG. 2C, a polysilicon gate electrode is formed on the three lines of the gate insulating film. By the heat treatment at that time, the doped second impurity is diffused and activated, and the punch-through stopper 21 is formed over the entire surface of the element formation region 11.

Next, referring to FIG. 2D, a resist mask 5 having an opening exposing the element formation region 11 is formed, and using this as a mask, the second impurity and the first impurity of the opposite conductivity type are removed. Ions are implanted into the element formation region with low energy. In this ion implantation, since the energy of the implanted ions is low, the implanted ions cannot pass through the gate electrode 4 and the element isolation region 2, and the ion implantation is performed in the element formation region 11 on both sides of the gate electrode 4 and in the gate electrode 4 and the self-alignment. One impurity 6a, 7a is doped.

Next, heat treatment is performed to form the source region 6 and the drain region 7 whose bottoms are in contact with the punch-through stopper 21, as shown in FIG. 2 (e). Thereafter, a semiconductor device having a field effect transistor having a punch-through stopper 21 is manufactured through a normal semiconductor device manufacturing process.

In the conventional punch-through stopper forming method described above, since the punch-through stopper is formed in the entire region of the element forming region, the high-concentration impurity regions of the punch-through stopper are in contact with the entire bottom surfaces of the source region and the drain region. . The junction between the source region and the drain region and the punch through stopper constitutes a pn junction, and a large junction capacitance is produced. Therefore, the field effect transistor manufactured by the above method has a large parasitic capacitance of the source and the drain, which hinders high-speed operation.

In order to reduce the parasitic capacitance of the source and drain, a method of manufacturing a field effect transistor in which a punch-through stopper is provided only under the channel formation region has been devised.

FIG. 3 is a cross-sectional process diagram of a conventional improvement example,
7 illustrates a manufacturing process of an improved field effect transistor. With reference to FIG. 3A, an element formation region 11 having a gate insulating film is formed on the surface of the semiconductor substrate 1 by the element isolation region 2. Next, a lift-off mask 32 having an opening that defines the gate electrode 4 is formed on the substrate 1, the lift-off mask 32 is used as an ion implantation mask, impurities are implanted into the substrate surface through the opening, and punching is performed. The through stopper 31 is formed.

Next, referring to FIG. 3B, a gate electrode material is deposited on the substrate 1 and is deposited on the lift-off mask 32, leaving the electrode material deposited in the opening of the lift-off mask 32. The gate electrode material is removed by lift-off to form the gate electrode 4.

Next, referring to FIG. 3C, a source region 6 and a drain region 7 are formed by ion implantation using the element isolation region 2 and the gate electrode 4 as a mask. According to this method, the punch-through stopper 31 is formed only directly below the gate electrode and does not overlap the source and drain regions, so that a field effect transistor with a small source and drain parasitic capacitance is manufactured. The punch-through stopper 31 is self-aligned with the source region 6 and the drain region 7 with respect to the gate electrode, so that the punch-through stopper 31 is easy to manufacture.

However, the process of forming the gate electrode by lift-off is inferior in reliability to the usual etching process. Further, in the case where the n-channel transistor and the p-channel transistor are formed on the same substrate, in order to form the gates of both transistors by lift-off at the same time, the n- or p-channel opening of the lift-off mask is formed with a resist for each side. Overcoat ion implantation must be followed by gate material deposition. Therefore, the gate material is deposited on the gate insulating film after the resist is removed, which may cause contamination and impair the reliability.

In a further improved device, the punch-through stopper is formed only on the channel-side ends of the source and drain regions, and the punch-through stopper is self-aligned with the gate electrode only by the etching process and the ion implantation process. You can

FIG. 4 is a cross-sectional process diagram of a conventional improved example, showing a cross section of a field effect transistor. In this improved example, referring to FIG. 4A, first, the gate insulating film 3, the polysilicon layer 42, and the S layer are formed on the element formation region where the elements are separated.
An iO ₂ film 44 is sequentially deposited, and a resist pattern 43 that defines the gate electrode 4 is formed thereon. Next, when reactive ion etching is performed using the resist pattern 43 as a mask, as shown in FIG.
Is completely removed in the vicinity of the gate electrode 4, while a polysilicon layer 42 having a uniform thickness remains at a position away from the gate electrode 4. Then, this polysilicon layer 42
When the ions are implanted using the mask as a mask, a punch-through stopper 41 is formed just below the end of the gate electrode 4. Next, referring to FIG. 4B, the source and drain regions 6 and 7 are formed by ion implantation using the gate electrode 4 and the element isolation region 2 as a mask.

In this modified example, the punch through stopper 4 is used.
Since 1 is small, the parasitic capacitance is improved. However, since the punch-through stopper 41 overlaps the source region 6 and the drain region 7, the reduction of the parasitic capacitance is limited and cannot be made sufficiently small. Moreover, since the punch-through stopper is not formed on the lower surface of the punch-through, the effect is poor.

[0021]

As described above, in the conventional method of manufacturing a semiconductor device, the punch-through stopper and the source region and the drain region are formed so as to overlap each other, so that the parasitic capacitance of the source and the drain is large. There is a problem. Furthermore, the parasitic capacitance cannot be sufficiently reduced by the method of forming the punch-through stopper in a part of the source region and the drain region.

Further, the method of forming the punch-through stopper only directly under the gate electrode using the lift-off mask is poor in reliability because the gate electrode is formed by lift-off, and the p-channel and n-channel type field effect transistors are not suitable. It has a drawback that it cannot be applied to the production of mixed semiconductor devices.

According to the present invention, a shallow punch-through stopper is formed only directly under the gate electrode by implanting impurities through the gate electrode, and the source and drain regions where the gate electrode is not formed are deeply ion-implanted. It is an object of the present invention to provide a semiconductor device having a field effect transistor that is implanted and has a small parasitic capacitance between the punch-through stopper and the source and drain, and a method for manufacturing the same.

[0024]

FIG. 1 is a sectional process drawing of an embodiment of the present invention, showing a section of a field effect transistor.

Referring to FIG. 1, a first structure of the present invention for solving the above-mentioned problem is a field effect transistor formed on the surface of a semiconductor substrate 1 and having a punch-through stopper 10a directly under a gate electrode 4. In the method of manufacturing a semiconductor device, the substrate on both sides of the gate electrode 4 is formed by a gate electrode forming step of forming the gate electrode 4 on the substrate 1 and selective ion implantation using the gate electrode 4 as a mask. A low voltage ion implantation step of forming a source region 6 and a drain region 7 by doping the first surface with a first impurity;
A second impurity having a conductivity type opposite to that of the first impurity is ion-implanted into the surface of the substrate 1 on which the gate electrode 4 is formed, and the second impurity that has passed through the gate electrode 4 is located immediately below the gate electrode 4. At the same time that the punch-through stopper 10a doped with is formed, the source region 6 and the drain region 7 are formed or the second impurity implanted into the region where the source region 6 and the drain region 7 are formed is added to the source region 6 and the drain region. 7 is a high-voltage ion implantation step for doping deep underneath, and a second configuration is the method for manufacturing a semiconductor device of the first configuration, wherein the field-effect transistor is the substrate. The low voltage ion implantation process is performed in the device formation region 11 separated by the device isolation region 2 formed on the surface, and the low voltage ion implantation process is performed using the gate electrode 4 and the device isolation region 2 as a mask. Made by ion implantation, the high-pressure ion implantation process constitutes a feature to be done by selective ion implantation using as a mask the element isolation region 2,
And the third configuration is the method for manufacturing a semiconductor device of the second configuration, in which the channel stopper 10c doped with the second impurity that has passed through the element isolation region 2 is added during the high voltage ion implantation step. The fourth structure is characterized in that it is formed in the vicinity of the lower end of the element isolation region 2, and the fourth structure is the method for manufacturing a semiconductor device of the second or third structure, Exposing the forming area 11,
And an ion implantation mask 8 having an opening extending on the element isolation region 2.
The fifth configuration is a semiconductor device having a field effect transistor formed on the surface of the semiconductor substrate 1 and having a punch-through stopper 10a immediately below the gate electrode 4, and the gate electrode 4 formed on the substrate 1 , A source region 6 and a drain region 7 formed on the surface of the substrate 1 on both sides of the gate electrode 4 by selective ion implantation of the first impurity using the gate electrode 4 as a mask, and the first impurity Is a punch-through stopper 1 formed by doping the second impurity having passed through the gate electrode 4 just below the gate electrode 4 by ion implantation of a second impurity of opposite conductivity type.
0a and, simultaneously with the punch-through stopper 10a, a punch-through stopper 10b formed by doping the second impurity ion-implanted deep into the source region 6 and the drain region 7 directly. Configure as.

[0026]

In the structure of the present invention, the second impurities 9a and 9b are ion-implanted in the element forming region 11 in which the gate electrode 4 is formed in the high-voltage ion implantation step with reference to FIG. The second impurity 9a penetrates the gate electrode 4 and forms a punch-through stopper 9a (see FIG. 1F) doped with the second impurity 9a immediately below the gate electrode 4.

In this high-voltage ion implantation step, the gate electrode material, the implanted ion species, and the acceleration voltage are adjusted so that the second impurity 9a transmitted through the gate electrode 4 is formed at a depth close to the bottom of the channel formation region. To be selected. Of course, it can be formed deeper if necessary.

On the other hand, in the source and drain forming regions where the gate electrode does not exist, since the implanted ions are not decelerated by the gate electrode 4, the second impurity 9b is implanted at a deep position from the surface. Therefore, since the punch-through stopper is formed at a position apart from the source region and the drain region, the capacitance between the source / drain and the punch-through stopper is small. Therefore, using the manufacturing method of this configuration,
A field effect transistor having a small parasitic capacitance is manufactured.

The punch-through stopper 10b immediately below the source region 6 or the drain region 7 does not necessarily have to be formed as a punch-through stopper, and the second impurity forming the punch-through stopper is simply implanted at a deep position, It is sufficient that the punch-through stopper 10b is not formed near the source region 6 or the drain region 7. Further, the region outside the gate electrode 4 can be masked as necessary to limit the impurity implantation region other than the punch-through stopper immediately below the gate electrode 4.

Further, in this configuration, FIGS. 1 (c) and 1 (d) are used.
Referring to, the first impurity is ion-implanted using the gate electrode 4 as a mask to form the source region 6 and the drain region 7.

Therefore, the punch-through stoppers 10a, 1
It is not necessary to prepare a special mask for forming 0b. Further, the punch-through stopper 10a, the source region 6 and the drain region 7 which are formed immediately below the gate electrode 4 are formed.
Are self-aligned with the gate electrode 4. Further, since the means of each step of this configuration is a method used in a normal semiconductor device manufacturing process, it is easy to apply the present invention to a conventional manufacturing process.

In applying this structure, the low-voltage ion implantation process for forming the source region 6 and the drain region 7 and the high-voltage ion implantation process for forming the punch-through stoppers 10a and 10b are both performed. May be preceded or followed.

In the second structure of the present invention, referring to FIG. 1B, the element isolation region 2 is formed on the surface of the substrate 1, and the gate is formed on the element formation region 11 isolated by the element isolation region 2. The electrode 4 is formed. Furthermore, FIG. 1 (c) and (d)
In the low voltage ion implantation process for forming the source region 6 and the drain region 7, the gate electrode 4 and the element isolation region 11 are set to an ion acceleration voltage which acts as a mask for ion implantation, while referring to FIG. Referring to e) and (f), in the high voltage ion implantation process for forming the punch through stoppers 10a and 10b, the implanted ions pass through the gate electrode 4 but do not pass through the element isolation region 2 and act as a mask. Ion acceleration voltage.

Therefore, the punch-through stopper is not formed under the element isolation region 2 and is selectively formed only in the element formation region 11, so that the degree of freedom in designing and manufacturing the semiconductor device is increased.

On the contrary, as in the case of the third structure, in the high voltage ion implantation step, referring to FIGS. 1 (e) and 1 (f), the implanted ions pass through the element isolation region 2 to form the element isolation region 2. The ion acceleration voltage can be selected so that the channel stopper 10c is formed in the vicinity of the interface with the substrate 1.

With this structure, it is not necessary to previously form a channel stopper below the element isolation region 2, and the process is simplified. Further, since the depth of the channel stopper can be easily changed, element isolation can be made more complete.

The element isolation region is a normal LOCOS.
In addition to the thermal oxide film formed by the above method, the trench may be embedded and formed with silicon nitride or silicon oxide. In the fourth configuration of the present invention, referring to FIG. 1E, the high voltage ion implantation process is performed using the ion implantation mask 8. The opening of the ion implantation mask 8 is formed so as to extend over the element formation region 11 and the element isolation region 2 around it. Ion implantation is limited to this opening. Therefore, when the p-channel transistor and the n-channel transistor are formed in a mixed manner, the opposite conductivity type impurities can be separately ion-implanted. In this case, since the gate electrode 4 is formed in advance before the ion implantation mask 8 is formed, the gate insulating film 3 immediately below the gate electrode 4 is hardly contaminated.

In the combination with the third structure, the range of the channel stopper 10c immediately below the element isolation region 2 can be limited to the periphery of the element formation region 11. Further, in the combination with the second configuration, the punch-through stoppers 10a and 10b are limited to immediately below the element forming region 11. Therefore, in both cases, when the p-well and the n-well are mixed, the channel in the isolation region is not destroyed and the element isolation is not hindered.

Further, in the present structure, when a mask is used in the low voltage ion implantation step, the ion implantation mask 8 has the same pattern as the mask,
The invention according to this configuration can be implemented without increasing the number of masks for lithography.

[0040]

The present invention will be described in detail with reference to an embodiment in which the present invention is applied to a semiconductor integrated circuit having a MOS transistor.

First, referring to FIG. 1A, an element isolation region 2 made of silicon oxide is formed on the surface of an n-type silicon substrate 1 by using, for example, LOCOS. Next, the gate insulating film 3 made of silicon oxide is formed on the surface of the element formation region 11 where the elements are separated, for example, by thermal oxidation. In the case of a semiconductor device such as CMOS in which pMOS and nMOS are mixed, wells of each conductivity type are formed in the element formation region 11. Hereinafter, the nMOS transistor formation region will be mainly described, but the same applies to the formation of the pMOS transistor except that the conductivity types are opposite.

Next, referring to FIG. 1B, n-type polysilicon is deposited on the entire surface of the substrate 1 and then patterned to form a polysilicon gate electrode 4 on the gate insulating film 3.

Next, referring to FIG. 1C, a resist is applied to the entire surface of the substrate 1, the element forming region 11 is exposed to the resist, and the element isolation region 2 around the element forming region 11 is formed. Open the opening to expose the resist mask 5
To form. When manufacturing a semiconductor device in which pMOS and nMOS are mixed, this resist mask 5 is
When the element formation region 11 of the n-channel transistor is opened, the element formation region of the p-channel transistor is covered, and conversely, when the element formation region 11 of the p-channel transistor is opened, the element formation region of the n-channel transistor is covered.

Next, referring to FIG. 1C, as a low-voltage ion implantation step, the n-type first impurities 6a and 6b are formed.
Are ion-implanted into the element formation region 11. Since this ion implantation is performed under a low acceleration voltage, the gate electrode 4
And the element isolation region 2 both act as a mask, and the substrate 1
The first impurities 6a and 7b implanted in the element are doped only on both sides of the gate electrode 4 in the element formation region 11. Furthermore, the resist mask 5 prevents ion implantation into other regions, for example, the device formation region of the p-channel transistor.

If necessary, p-type impurities as the first impurities are ion-implanted into the element formation region of the p-channel transistor in the same manner. Thereafter, referring to FIG. 1D, the resist mask 5 is removed and then diffusion processing is performed to form a source region 6 and a drain region 7.

Next, referring to FIG. 1E, an ion implantation mask 8 made of a resist having openings having the same pattern as the resist mask 5 used in the low voltage ion implantation process is formed on the substrate 1. To do.

Then, as a high voltage ion implantation step, p
The second impurities 9a, 9b, 9c of the mold are ion-implanted into the surface of the substrate 1. The acceleration voltage of this ion implantation is selected so that the implanted ions pass through the gate electrode 4 and have a concentration peak of the second impurity 9a near the bottom of the channel formation region. In this condition, the ions implanted in the source and drain regions 6 and 7 penetrate the source and drain regions 6 and 7 and reach a second depth to a depth that is not substantially affected by the depletion layer extending from these regions. A concentration peak of the impurity 9b is generated. On the other hand, the ions implanted in the element isolation region 2 exposed in the opening of the ion implantation mask 8 pass through the element isolation region 2 and form a second impurity concentration peak on the substrate surface portion in contact with the bottom surface of the element isolation region 2. To do.

The thickness and accelerating voltage of the gate electrode 2 and the element isolation region 2 are set so that the impurities transmitted through the gate electrode 4 and the element isolation region 2 have a predetermined depth. Further, no impurities are implanted into the substrate 1 in the other regions covered with the ion implantation mask 8. Therefore, by performing the same high-voltage ion implantation as that described above on the formation region of the p-channel transistor, it is possible to form the same impurity concentration distribution with the opposite conductivity type.

Next, referring to FIG. 1F, by activating the second impurities 9a, 9b, 9c,
A punch-through stopper 10a immediately below the channel and close to the channel, a punch-through stopper 10b below the element isolation region 2 around the element formation region 11, and a punch-through stopper at a deep position immediately below the source and drain regions 6 and 7. Form 10b.

Hereinafter, a semiconductor device including a field effect transistor is manufactured through a normal semiconductor device manufacturing process.
In this embodiment, the ion implantation is all self-aligned except for the formation of the channel stopper below the element isolation region. Further, no special process is required for forming the channel stopper below the element isolation region, and no special process other than the process used in the normal semiconductor device manufacturing process is required. Furthermore, the formation of the punch-through stopper and the formation of the source and drain regions can be performed with the mask having the same pattern. Therefore, this embodiment can be easily applied to a normal semiconductor manufacturing process.

In the above embodiment, pMOS and nMO are used.
The manufacturing method when S and S coexist was also explained,
It goes without saying that the effect of the present invention can be obtained even when it is composed of only one of them.

[0052]

As described above, according to the present invention, the punch-through stopper is formed in a shallow position directly below the gate electrode in a self-aligned manner with respect to the gate electrode and deeply formed under the source and drain regions. A semiconductor device having a field effect transistor with a small parasitic capacitance can be manufactured by using a process which is easily applicable to the conventional technique and has excellent reliability.

Further, since the gate electrode is formed and then the ions are implanted, even if the masks are separately used to form the p-channel transistor and the n-channel transistor, the gate insulating film is not contaminated. Thus, it is possible to easily manufacture a semiconductor device in which a p-channel transistor and an n-channel transistor are mixed.

[Brief description of drawings]

FIG. 1 is a sectional process drawing of an embodiment of the present invention.

FIG. 2 is a sectional process diagram of a conventional example.

FIG. 3 is a cross-sectional process diagram of a conventional improvement example.

FIG. 4 is a sectional process drawing of another conventional improvement example.

[Explanation of symbols]

1 substrate 2 element isolation region 3 gate insulating film 4 gate electrode 5 resist mask 6 source region 6a, 7a first impurity 7 drain region 8 ion implantation mask 9a, 9b, 9c second impurity 10a. 10b Punch-through stopper 10c Channel stopper 11 Element formation region 31, 41 Punch-through stopper 32 Lift-off mask 42 Polysilicon layer 43 Resist pattern 44 SiO ₂ film

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical indication location H01L 21/76 H01L 21/265 M J 21/76 SR

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device having a field effect transistor formed on the surface of a semiconductor substrate (1), comprising a punch-through stopper (10a) immediately below a gate electrode (4). , The gate electrode (4)
Forming a gate electrode and the gate electrode (4)
Voltage for forming the source region (6) and the drain region (7) by doping the first impurity on the surface of the substrate (1) on both sides of the gate electrode (4) by selective ion implantation using the mask as a mask Ion implantation step, and ion-implanting a second impurity having a conductivity type opposite to that of the first impurity into the surface of the substrate (1) on which the gate electrode (4) is formed, and directly under the gate electrode (4). A region where the source region (6) and the drain region (7) are formed or formed at the same time when the punch-through stopper (10a) doped with the second impurity that has passed through the gate electrode (4) is formed. High voltage ion implantation step of doping the second impurity implanted into the deep region directly under the source region (6) and the drain region (7), the gate electrode forming step, low voltage ion implantation Process and high voltage ion In order entry process, or the gate electrode forming step, a method of manufacturing a semiconductor device, which comprises carrying out in the order of high-voltage ion implantation process and a low voltage ion implantation process. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the field effect transistor is formed in an element formation region (11) separated by an element separation region (11) formed on the surface of the substrate. , The low voltage ion implantation step is performed by selective ion implantation using the gate electrode (4) and the element isolation region (11) as a mask, and the high voltage ion implantation step masks the element isolation region (11). A method of manufacturing a semiconductor device, comprising: performing selective ion implantation. 3. The method of manufacturing a semiconductor device according to claim 2, wherein in the high voltage ion implantation step, the channel stopper (10c) doped with the second impurity that has permeated the element isolation region (2). Is formed near the lower end of the element isolation region (2). 4. The method of manufacturing a semiconductor device according to claim 2, wherein the high voltage ion implantation step exposes the element formation region (11) and extends over the element isolation region (2). A method for manufacturing a semiconductor device, which is performed using an ion implantation mask (8) having existing openings. 5. A semiconductor device having a field effect transistor formed on the surface of a semiconductor substrate (1) and having a punch-through stopper (10a) immediately below a gate electrode (4), formed on the substrate (1). The gate electrode (4)
And a source region (6) and a drain region formed on the surface of the substrate (1) on both sides of the gate electrode (4) by selective ion implantation of a first impurity using the gate electrode (4) as a mask (7) and ion implantation of a second impurity having a conductivity type opposite to that of the first impurity, whereby the gate electrode (4)
The punch-through stopper (10) formed by being doped with the second impurity that has passed through the gate electrode (4) immediately below.
a) and the punch through stopper (10a) at the same time,
A semiconductor device comprising: a punch-through stopper (10b) formed by doping the second impurity ion-implanted into a deep portion immediately below the source region (6) and the drain region (7).