JPH07263385A - Surface plate for polishing semiconductor wafer - Google Patents

Surface plate for polishing semiconductor wafer

Info

Publication number
JPH07263385A
JPH07263385A JP4915894A JP4915894A JPH07263385A JP H07263385 A JPH07263385 A JP H07263385A JP 4915894 A JP4915894 A JP 4915894A JP 4915894 A JP4915894 A JP 4915894A JP H07263385 A JPH07263385 A JP H07263385A
Authority
JP
Japan
Prior art keywords
polishing
semiconductor wafer
resin film
surface plate
platen
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4915894A
Other languages
Japanese (ja)
Other versions
JP3251419B2 (en
Inventor
Shinsuke Sakai
慎介 酒井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Silicon Corp
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Silicon Corp
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Silicon Corp, Mitsubishi Materials Corp filed Critical Mitsubishi Materials Silicon Corp
Priority to JP4915894A priority Critical patent/JP3251419B2/en
Publication of JPH07263385A publication Critical patent/JPH07263385A/en
Application granted granted Critical
Publication of JP3251419B2 publication Critical patent/JP3251419B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE:To improve the flateness on surface level of a semiconductor wafer by forming a polishing face with a groove, on one main surface of a rigid surface plate where the surface grading is in roughly specified numerical range, and forming a resin film on the surface of the polishing face. CONSTITUTION:A surface plate 1 for polishing is constituted of material being little in mechanical and thermal transformation and besides flat, for example, ceramic material such as high-purity quartz, etc. Grooves 2 crossing each other are made on one main surface (polishing face) 1a of this surface plate for polishing so that polishing liquid may cover all the semiconductor wafer. Moreover, to secure the sticking tendency with a resin film 3, the grading (roughness) of, at least, the polishing face 1a is in the range of about 10-100mum, and a resin film 3 consisting of polyurethane resin or fluoric resin is made on the surface of the polishing face 1a, which enables the chemical mechanical polishing of a semiconductor wafer W to improve the flatness on surface level. Hereby, the stoppage of the polishing by the hard stopper made of resin film is expected.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体ウェーハの表面を
高精度に研磨することができる半導体ウェーハの研磨用
定盤に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polishing platen for polishing a semiconductor wafer capable of polishing the surface of the semiconductor wafer with high precision.

【0002】[0002]

【従来の技術】従来、シリコン(半導体)ウェーハの無
歪鏡面研磨は、厚さが約2mm程度の不飽和ポリエステ
ル繊維からなる研磨布が用いられていたが、半導体ウェ
ーハを研磨布に加圧すると当該ウェーハが柔らかい研磨
布に沈み込んでコロイダルシリカ粒子を懸濁したアルカ
リ液により化学的機械研磨(:ケミカルメカニカル研
磨:CMP=Chemical Mechanical Polishing)されるた
め、半導体ウェーハの周縁にいわゆる面だれが生じると
いう問題があった。また、SOI基板では酸化膜絶縁セ
ルパターンがストッパとなり一定の厚さの活性層を形成
する研磨が行われるが、絶縁壁で囲まれた活性層が中凹
に(中央部が凹面状に)研磨される。そのため、特開平
2ー36069号公報に開示された方法では、高純度石
英などのセラミックス材料からなる剛体定盤を用いて半
導体ウェーハを直接研磨することが提案されている。
2. Description of the Prior Art Conventionally, a polishing cloth made of unsaturated polyester fiber having a thickness of about 2 mm has been used for non-strained mirror polishing of a silicon (semiconductor) wafer. Since the wafer is submerged in a soft polishing cloth and is subjected to chemical mechanical polishing (: CMP = Chemical Mechanical Polishing) with an alkaline liquid in which colloidal silica particles are suspended, so-called sag occurs at the periphery of the semiconductor wafer. There was a problem. On the SOI substrate, the oxide film insulating cell pattern serves as a stopper to form an active layer having a certain thickness, but the active layer surrounded by the insulating wall is polished in a concave shape (the central portion is concave). To be done. Therefore, in the method disclosed in JP-A-2-36069, it is proposed to directly polish a semiconductor wafer using a rigid surface plate made of a ceramic material such as high-purity quartz.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、剛体定
盤による研磨では半導体ウェーハの研磨面にキズが生じ
易いという問題があり、研磨布による研磨に比べて平坦
度は改善されるもののキズの問題は解消できなかった。
However, polishing with a rigid surface plate has a problem that scratches are likely to occur on the polishing surface of a semiconductor wafer. Although the flatness is improved as compared with polishing with a polishing cloth, the problem of scratches is I couldn't solve it.

【0004】本発明は、このような従来技術の問題点を
改善するという観点に鑑みてなされたものであり、半導
体ウェーハの表面基準での平坦度を向上させる研磨を目
的とする。
The present invention has been made in view of the above problems of the prior art, and an object thereof is polishing for improving the flatness of a semiconductor wafer on the basis of the surface.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するため
に、本発明の半導体ウェーハの研磨用定盤は、表面粒度
(表面粗さ)が、ほぼ10〜100μm程度である剛体
定盤の一主面に溝を有する研磨面を形成し、この研磨面
の表面に樹脂皮膜を形成したことを特徴としている。
In order to achieve the above object, the polishing plate of the semiconductor wafer according to the present invention is a rigid platen having a surface grain size (surface roughness) of about 10 to 100 μm. It is characterized in that a polishing surface having grooves on the main surface is formed and a resin film is formed on the surface of the polishing surface.

【0006】[0006]

【作用】剛体定盤を用いて半導体ウェーハを直接研磨す
る方法では、剛体定盤の平坦度が5μm、表面粗さが
0.01μmの精度を確保しておけば、ケミカルメカニ
カル研磨される半導体ウェーハの平坦度も定盤の平坦度
に漸近する。軟性の研磨布を用いた研磨に比べると表面
基準の平坦度が向上し、酸化膜等のストッパが存在すれ
ばこの面で研磨速度が激減し平坦面が得られる。しかし
ながら、剛体定盤に溝を形成する場合には溝の縁が鋭い
角となり、角が欠けると半導体ウェーハにキズが付き、
また、注意深い研磨を行っても半導体ウェーハの挿入お
よび取り出し時にスクラッチキズが付く確率が高い。
In the method of directly polishing a semiconductor wafer using a rigid surface plate, if the accuracy of the rigid surface plate having a flatness of 5 μm and a surface roughness of 0.01 μm is ensured, a semiconductor wafer to be chemically mechanically polished can be obtained. The flatness of is also asymptotic to the flatness of the surface plate. Compared with polishing using a soft polishing cloth, the flatness on the surface basis is improved, and if there is a stopper such as an oxide film, the polishing rate is drastically reduced on this surface and a flat surface is obtained. However, when forming a groove on a rigid surface plate, the edge of the groove becomes a sharp corner, and if the corner is missing, the semiconductor wafer will be scratched,
In addition, even if careful polishing is performed, there is a high probability that scratches will occur during insertion and removal of the semiconductor wafer.

【0007】本発明の半導体の研磨用定盤では、研磨面
の表面に樹脂皮膜を形成することにより半導体ウェーハ
へのキズ付きを防止し、取り扱いを容易にすることがで
きる。また、定盤の表面粒度(粗さ)を、ほぼ10〜1
00μm程度という多孔質定盤にすることにより、定盤
の平坦加工と溝加工が容易になり、定盤の表面に形成さ
れる樹脂が定盤内に浸透し固着するため当該樹脂皮膜の
研磨途中における硬質の酸化膜ストッパと接触しても溝
の縁の欠けや樹脂皮膜の剥がれを防止することができ
る。これに加えて、平坦度の高い剛体研磨盤を使用する
と研磨熱が十分取り除けず研磨面の温度が上昇して研磨
条件が変化するため、溝を形成すると研磨液をウェーハ
全体に行き渡らせたり、研磨により生じる摩擦熱を放散
することにも機能する。
In the semiconductor polishing platen of the present invention, by forming a resin film on the surface of the polishing surface, scratches on the semiconductor wafer can be prevented and handling can be facilitated. In addition, the surface grain size (roughness) of the surface plate is approximately 10 to 1
By using a porous platen of about 00 μm, flattening and grooving of the platen can be facilitated, and the resin formed on the surface of the platen permeates into and adheres to the platen, while polishing the resin film. It is possible to prevent chipping of the edge of the groove and peeling of the resin film even if it comes into contact with the hard oxide film stopper. In addition to this, when a rigid polishing machine with high flatness is used, the polishing heat cannot be sufficiently removed and the temperature of the polishing surface rises and the polishing conditions change, so when the grooves are formed, the polishing liquid can be spread over the entire wafer, It also functions to dissipate the frictional heat generated by polishing.

【0008】[0008]

【実施例】以下、本発明の実施例を図面を参照して説明
する。図1(A)は本発明の実施例の半導体ウェーハの
研磨用定盤を示す半断面図、図1(B)は同じく定盤の
表面を拡大して示す要部拡大断面図、図1(C)は同じ
く定盤の表面を拡大して示す要部拡大断面図であって他
の方法により樹脂皮膜を形成した実施例を示す図であ
る。また、図2は本発明の半導体ウェーハの研磨用定盤
を示す要部平面図、図3は本発明の他の実施例に係る半
導体ウェーハの研磨用定盤を示す要部平面図、図4は本
発明のさらに他の実施例に係る半導体ウェーハの研磨用
定盤を示す要部平面図である。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 (A) is a half sectional view showing a surface plate for polishing a semiconductor wafer according to an embodiment of the present invention, and FIG. 1 (B) is an enlarged sectional view showing an enlarged main part of the surface of the surface plate. FIG. 6C is an enlarged cross-sectional view of a main part showing the surface of the platen in an enlarged manner, showing an example in which a resin film is formed by another method. 2 is a plan view of a main part of a polishing surface plate of a semiconductor wafer according to the present invention, and FIG. 3 is a plan view of a main part of a polishing surface plate of a semiconductor wafer according to another embodiment of the present invention. FIG. 6 is a plan view of a principal part showing a polishing platen for polishing a semiconductor wafer according to still another embodiment of the present invention.

【0009】まず、図1(A)に示すように、本実施例
の研磨用定盤1は機械的、熱的変形が少なく、しかも平
坦な材料、例えば高純度石英などのセラミックス材料に
より構成されている。この研磨用定盤の一主面(研磨
面)1aには、図2〜図4に平面図で示すように縦横に
交差する溝2が形成されており、例えばメカノ・ケミカ
ル研磨を行った場合に生じる半導体ウェーハW全体に研
磨液を行き渡らせるように機能する。また、半導体ウェ
ーハWと研磨用定盤との間に生じる摩擦熱を放散させる
機能をも司る。したがって、溝2の形状は図2に示す格
子状にのみ限定されず、図3に示すサッカーボールの表
面形状、あるいは図4に示す三角形状の他、種々の形状
とすることができる。この溝は、例えば幅1.5mm、
深さ1mm程度とすることができる。
First, as shown in FIG. 1 (A), the polishing surface plate 1 of this embodiment is made of a flat material, for example, a ceramic material such as high-purity quartz, which has little mechanical and thermal deformation. ing. On one main surface (polishing surface) 1a of this polishing platen, grooves 2 that cross vertically and horizontally are formed as shown in plan views in FIGS. 2 to 4, and, for example, when mechano-chemical polishing is performed. Functioning so as to spread the polishing liquid over the entire semiconductor wafer W. Further, it also has a function of dissipating frictional heat generated between the semiconductor wafer W and the polishing platen. Therefore, the shape of the groove 2 is not limited to the lattice shape shown in FIG. 2, and can be various shapes other than the surface shape of the soccer ball shown in FIG. 3 or the triangular shape shown in FIG. This groove has, for example, a width of 1.5 mm,
The depth can be about 1 mm.

【0010】本実施例の研磨用定盤1は剛体であればセ
ラミックスにのみ限定されることはないが、後述する樹
脂皮膜3との固着性を確保するために、少なくとも研磨
面1aの粒度(粗さ)は10〜100μm程度の範囲に
することが望ましい。上述したように研磨用定盤1を多
孔質セラミックス材料により作製する場合には、その粒
度は#20〜#350に相当することになる。
The polishing surface plate 1 of this embodiment is not limited to ceramics as long as it is a rigid body, but at least the grain size of the polishing surface 1a ( The roughness is preferably in the range of about 10 to 100 μm. When the polishing platen 1 is made of a porous ceramic material as described above, the particle size thereof corresponds to # 20 to # 350.

【0011】この研磨用定盤の研磨面1aの表面には、
図1(B)に示すように、例えばポリウレタン系樹脂や
フッ素系樹脂からなる樹脂皮膜3が形成されている。樹
脂皮膜3を構成する樹脂の種類は特に限定されないが、
上述したポリウレタン系樹脂はシリコン(半導体)ウェ
ーハWに対する研磨性に優れている他、研磨用定盤1へ
の皮膜の成形性と薬液による除去性能に優れている。
On the surface of the polishing surface 1a of this polishing platen,
As shown in FIG. 1B, a resin film 3 made of, for example, polyurethane resin or fluorine resin is formed. The type of resin forming the resin film 3 is not particularly limited,
The above-mentioned polyurethane-based resin is excellent in polishability for a silicon (semiconductor) wafer W, and also excellent in moldability of a film on the polishing platen 1 and removal performance by a chemical solution.

【0012】この樹脂皮膜3は、例えば20μm〜10
0μm程度の膜厚とすることが望ましい。図1(B)に
示す研磨用定盤1は、いわゆる湿式処理により薄膜の樹
脂皮膜3を形成した具体例であって、これは以下のよう
にして形成することができる。まず、研磨用定盤1の周
縁にフェンス(ポリウレタン溶液の溢れ防止)を取り付
けた状態で、樹脂皮膜3を構成するポリウレタンDMF
(ジメチルホルムアミド)溶液を研磨面1a全体に流延
して静置する。そして、研磨面1aの表面に液溜まりが
完全になくなるまで十分に含浸・放置したのち、研磨面
1aを下に向けて水に浸漬しポリウレタンDMF溶液を
凝固させる。最後に約40度Cの温風で樹脂皮膜3を乾
燥させると20μm程度の薄膜の樹脂皮膜3を得ること
ができる。
The resin film 3 has, for example, 20 μm to 10 μm.
It is desirable to set the film thickness to about 0 μm. The polishing platen 1 shown in FIG. 1 (B) is a specific example in which a thin resin film 3 is formed by a so-called wet process, which can be formed as follows. First, a polyurethane DMF forming the resin film 3 with a fence (prevention of overflow of polyurethane solution) attached to the periphery of the polishing surface plate 1.
A (dimethylformamide) solution is cast on the entire polishing surface 1a and left standing. Then, after sufficiently impregnating and leaving the surface of the polishing surface 1a until the liquid pool is completely removed, the polishing surface 1a is faced downward and immersed in water to solidify the polyurethane DMF solution. Finally, by drying the resin film 3 with a hot air of about 40 ° C., a thin resin film 3 of about 20 μm can be obtained.

【0013】これに対して、図1(C)に示す研磨用定
盤1は、いわゆる乾式処理により厚膜の樹脂皮膜3を形
成した具体例であって、以下のようにして形成すること
ができる。まず、研磨用定盤1の周縁にフェンスを取り
付けた状態で、まずMEK(メチル・エチル・ケトン)
溶剤を研磨面1aに含浸させる。次に樹脂皮膜3を構成
するポリウレタンMEK溶液を研磨面1a全体に流延し
て静置する。そして、研磨面1aの表面に液溜まりがで
きるまで、以上の流延及び静置を繰り返し、フェンスを
取り外して溝に溜まった余分なポリウレタン溶液を除去
したのち、約140度Cで乾燥・硬化させる。これによ
り100μm程度の厚膜の樹脂皮膜3を得ることができ
る。
On the other hand, the polishing platen 1 shown in FIG. 1 (C) is a specific example in which the thick resin film 3 is formed by a so-called dry process, and can be formed as follows. it can. First, with a fence attached to the periphery of the polishing surface plate 1, first, MEK (methyl ethyl ketone)
The polishing surface 1a is impregnated with the solvent. Next, the polyurethane MEK solution forming the resin film 3 is cast on the entire polishing surface 1a and left standing. Then, the above casting and standing are repeated until the liquid is accumulated on the surface of the polishing surface 1a, the fence is removed to remove the excess polyurethane solution accumulated in the groove, and then it is dried and cured at about 140 ° C. . As a result, the resin film 3 having a thick film of about 100 μm can be obtained.

【0014】このような樹脂皮膜3の膜厚は研磨工程に
よって使い分けることが好ましい。例えば、鏡面研磨の
初期工程では研磨速度の確保を重視することから、半導
体ウェーハ全体の平坦度を高めるのに適した厚膜の樹脂
皮膜(図1(C))を用いることが望ましい。これに対
して、鏡面研磨の仕上げ工程ではマイクロラフネスの確
保が極めて重要であることから、これに適した薄膜の樹
脂皮膜(図1(B))を用いることが望ましい。
It is preferable that the film thickness of the resin film 3 is properly used depending on the polishing process. For example, since it is important to secure a polishing rate in the initial step of mirror polishing, it is desirable to use a thick resin film (FIG. 1C) suitable for increasing the flatness of the entire semiconductor wafer. On the other hand, since it is extremely important to secure microroughness in the finishing step of mirror polishing, it is desirable to use a thin resin film (FIG. 1B) suitable for this.

【0015】次に作用を説明する。セラミックス材料な
どからなる剛体定盤1を用いて半導体ウェーハWを直接
研磨する方法では、剛体定盤1の表面粗さの精度を0.
01μmまで確保しておけば半導体ウェーハWはケミカ
ルメカニカル研磨により平坦化研磨が行われる。そし
て、剛体定盤1の平坦度はウェーハ研磨における平坦度
の確保に比べて容易に達成することができる。したがっ
て、この剛体研磨によれば、従来行われていた軟性の研
磨布を用いた研磨に比べてウェーハの平坦度が著しく向
上することになる。
Next, the operation will be described. In the method of directly polishing the semiconductor wafer W using the rigid surface plate 1 made of a ceramic material or the like, the accuracy of the surface roughness of the rigid surface plate 1 is set to 0.
If the thickness is secured to 01 μm, the semiconductor wafer W is flattened and polished by chemical mechanical polishing. Further, the flatness of the rigid body surface plate 1 can be easily achieved as compared with ensuring the flatness in the wafer polishing. Therefore, according to this rigid polishing, the flatness of the wafer is significantly improved as compared with the conventional polishing using a soft polishing cloth.

【0016】一方、剛体定盤1の粒度が粗いと半導体ウ
ェーハWはケミカルメカニカル研磨が行わず、メカニカ
ル研磨となることから鏡面無歪研磨は行われない。そこ
で、本発明の半導体の研磨用定盤では、研磨面1aの表
面に樹脂皮膜3を形成することにより半導体ウェーハW
のケミカルメカニカル研磨が可能となる。これに加え
て、樹脂皮膜3は所定の薬液にて除去することが容易で
あることから樹脂皮膜3の再生が可能となり、一度平坦
度に優れた定盤を製作しておけば樹脂皮膜3を塗り替え
るだけで何度でも用いることができる。
On the other hand, if the rigid body surface plate 1 has a coarse grain size, the semiconductor wafer W is not subjected to chemical mechanical polishing, and is mechanically polished, so that mirror surface strain-free polishing is not performed. Therefore, in the semiconductor polishing plate of the present invention, the semiconductor wafer W is formed by forming the resin film 3 on the surface of the polishing surface 1a.
It enables chemical mechanical polishing. In addition to this, since the resin film 3 can be easily removed with a predetermined chemical solution, the resin film 3 can be regenerated, and once the platen having excellent flatness is manufactured, the resin film 3 can be formed. Can be used any number of times just by repainting.

【0017】また、研磨面1aの表面粗さがほぼ10〜
100μm程度であるという多孔質セラミックスにする
ことにより、定盤の表面に形成される樹脂皮膜3が定盤
の表面に含浸し凝固する。その結果、樹脂皮膜の固着性
が向上し当該樹脂皮膜の研磨途中における剥がれを防止
することができる。これに加えて、研磨面に溝2を形成
すると研磨液を半導体ウェーハ全体に行き渡らせたり、
研磨液を保持したり、あるいは研磨で生じた研磨生成物
を排出することができる。また、研磨により生じる摩擦
熱を放散することにも機能する。
The surface roughness of the polishing surface 1a is approximately 10 to 10.
By using porous ceramics having a thickness of about 100 μm, the resin film 3 formed on the surface of the surface plate is impregnated on the surface of the surface plate and solidified. As a result, the adhesiveness of the resin film is improved and peeling of the resin film during polishing can be prevented. In addition to this, when the groove 2 is formed on the polishing surface, the polishing liquid is spread over the entire semiconductor wafer,
The polishing liquid can be retained, or the polishing product generated by polishing can be discharged. It also functions to dissipate frictional heat generated by polishing.

【0018】なお、以上説明した実施例は、本発明の理
解を容易にするために記載されたものであって、本発明
を限定するために記載されたものではない。したがっ
て、上記の実施例に開示された各要素は、本発明の技術
的範囲に属する全ての設計変更や均等物をも含む趣旨で
ある。
It should be noted that the embodiments described above are described for facilitating the understanding of the present invention, and not for limiting the present invention. Therefore, each element disclosed in the above-described embodiments is intended to include all design changes and equivalents within the technical scope of the present invention.

【0019】[0019]

【発明の効果】以上述べたように本発明によれば、表面
粒度(粗さ)がほぼ10〜100μm程度である剛体定
盤の一主面に溝を有する研磨面を形成し、この研磨面の
表面に樹脂皮膜を形成しているので、剛体定盤による表
面基準平坦度の向上と同時に樹脂皮膜による硬質のスト
ッパによる研磨停止が期待できる。また、樹脂皮膜の再
生も容易である。加えて、研磨面に溝を形成すると研磨
液を半導体ウェーハ全体に行き渡らせたり、また、研磨
により生じる摩擦熱を放散することもできる。
As described above, according to the present invention, a polishing surface having grooves is formed on one main surface of a rigid surface plate having a surface grain size (roughness) of about 10 to 100 μm. Since a resin film is formed on the surface of the, it is expected that the surface standard flatness of the rigid surface plate will be improved and at the same time polishing by the hard stopper of the resin film will be stopped. In addition, it is easy to regenerate the resin film. In addition, by forming a groove on the polishing surface, the polishing liquid can be spread over the entire semiconductor wafer, and the friction heat generated by polishing can be dissipated.

【図面の簡単な説明】[Brief description of drawings]

【図1】(A)は本発明の半導体ウェーハの研磨用定盤
を示す半断面図、(B)は同じく定盤の表面を拡大して
示す要部拡大断面図、(C)は同じく定盤の表面を拡大
して示す要部拡大断面図であって他の方法により樹脂皮
膜を形成した実施例を示す図である。
FIG. 1A is a half sectional view showing a polishing platen for polishing a semiconductor wafer of the present invention, FIG. 1B is an enlarged sectional view of an essential part showing the surface of the platen in an enlarged manner, and FIG. It is a principal part expanded sectional view which expands and shows the surface of a board | substrate, and is a figure which shows the Example which formed the resin film by another method.

【図2】本発明の半導体ウェーハの研磨用定盤を示す要
部平面図である。
FIG. 2 is a plan view of relevant parts showing a polishing platen for polishing a semiconductor wafer according to the present invention.

【図3】本発明の他の実施例に係る半導体ウェーハの研
磨用定盤を示す要部平面図である。
FIG. 3 is a main part plan view showing a polishing platen for polishing a semiconductor wafer according to another embodiment of the present invention.

【図4】本発明のさらに他の実施例に係る半導体ウェー
ハの研磨用定盤を示す要部平面図である。
FIG. 4 is a plan view of essential parts showing a polishing platen for polishing a semiconductor wafer according to still another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1…研磨用定盤 1a…研磨面 2…溝 3…樹脂皮膜 1 ... Polishing surface plate 1a ... Polishing surface 2 ... Groove 3 ... Resin film

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】表面粒度(粗さ)がほぼ10〜100μm
程度である剛体定盤の一主面に溝を有する研磨面を形成
し、この研磨面の表面に樹脂皮膜を形成した、ことを特
徴とする半導体ウェーハの研磨用定盤。
1. Surface grain size (roughness) is approximately 10 to 100 μm.
A polishing surface plate for a semiconductor wafer, characterized in that a polishing surface having grooves is formed on one main surface of a rigid surface plate, and a resin film is formed on the surface of the polishing surface.
JP4915894A 1994-03-18 1994-03-18 Surface plate for polishing semiconductor wafers Expired - Fee Related JP3251419B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4915894A JP3251419B2 (en) 1994-03-18 1994-03-18 Surface plate for polishing semiconductor wafers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4915894A JP3251419B2 (en) 1994-03-18 1994-03-18 Surface plate for polishing semiconductor wafers

Publications (2)

Publication Number Publication Date
JPH07263385A true JPH07263385A (en) 1995-10-13
JP3251419B2 JP3251419B2 (en) 2002-01-28

Family

ID=12823294

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4915894A Expired - Fee Related JP3251419B2 (en) 1994-03-18 1994-03-18 Surface plate for polishing semiconductor wafers

Country Status (1)

Country Link
JP (1) JP3251419B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0957611A (en) * 1995-06-08 1997-03-04 Matsushita Electric Ind Co Ltd Substrate polishing apparatus and its polishing process
US5921853A (en) * 1995-04-10 1999-07-13 Matsushita Electric Industrial Co., Ltd. Apparatus for polishing substrate using resin film or multilayer polishing pad
US6121143A (en) * 1997-09-19 2000-09-19 3M Innovative Properties Company Abrasive articles comprising a fluorochemical agent for wafer surface modification
JP2000288918A (en) * 1999-04-02 2000-10-17 Applied Materials Inc Improved cmp platen having pattern surface
JP2017144495A (en) * 2016-02-15 2017-08-24 国立研究開発法人海洋研究開発機構 Finish polishing surface plate and finish polishing device
JP2020128008A (en) * 2020-05-26 2020-08-27 国立研究開発法人海洋研究開発機構 Surface plate for finish-polishing, finish-polishing device and polishing method

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5921853A (en) * 1995-04-10 1999-07-13 Matsushita Electric Industrial Co., Ltd. Apparatus for polishing substrate using resin film or multilayer polishing pad
JPH0957611A (en) * 1995-06-08 1997-03-04 Matsushita Electric Ind Co Ltd Substrate polishing apparatus and its polishing process
US6121143A (en) * 1997-09-19 2000-09-19 3M Innovative Properties Company Abrasive articles comprising a fluorochemical agent for wafer surface modification
JP2000288918A (en) * 1999-04-02 2000-10-17 Applied Materials Inc Improved cmp platen having pattern surface
JP4489903B2 (en) * 1999-04-02 2010-06-23 アプライド マテリアルズ インコーポレイテッド Improved CMP platen with patterned surface
JP2017144495A (en) * 2016-02-15 2017-08-24 国立研究開発法人海洋研究開発機構 Finish polishing surface plate and finish polishing device
JP2020128008A (en) * 2020-05-26 2020-08-27 国立研究開発法人海洋研究開発機構 Surface plate for finish-polishing, finish-polishing device and polishing method

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