JPH07262800A - Tester of multiport type memory - Google Patents

Abstract

PURPOSE:To judge a memory element to be nondefective or defective and to improve the test efficiency by executing writing/reading out of data by using a standard address and conversion addresses for several ports, then comparing the data. CONSTITUTION:The standard address and the conversion addresses varying by the number of the reloadable ports of an element 7 to be tested are generated by a pattern generator 6. Further, test data and a writing control signal are generated as well. The generated signals are sent to a test data memory circuit 650 and a programmable signal selecting circuit 62. This selecting circuit 62 writes the test data into the element 7 via a waveform forming circuit 63, an input/output voltage generating circuit 64 and a test head 65 by the selected signal. The same data are also written into the memory circuit 650 at the same address as the address of the element 7. The test data of the element 7 and the memory circuit 650 are read out and are sent to a comparator circuit 66 by the reading out control signal of the pattern generator 6 after the end of the writing. The element 7 is judged by generally considering the test result output by the comparator circuit 66.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-port type memory testing device, and more particularly to a multi-port type memory testing device capable of performing a test for guaranteeing a relationship between multi-ports such as the presence or absence of a short. Regarding test equipment.

[0002]

2. Description of the Related Art In recent years, multiprocessing of computers has become common, and multiport memories have become diversified. However, testing technology for multi-port memory is still under development.

Presently existing multi-port memory test systems perform individual tests for each individual port. FIG. 11 is a block diagram of a conventional multi-port memory testing device.

A conventional test apparatus includes a pattern generation circuit ALPG800 (ALgorithmic Pat) for generating a test pattern.
tern Generator), an address conversion circuit 81 that generates a physical address to be written to or read from the device under test.
0, Programmable selection circuit PDS820 (Programmable Data Selector) that selects control signals, test data, and addresses that are input from the ALPG800 according to specifications, Waveform shaping circuit F that sets the waveform of the signal that is input to the device under test
C830 (Format Controller), input / output voltage generation circuit VI that sets the input / output voltage of the signal input to the device under test
/ VO840, and a test head 850 that serves as an interface with the device under test.

The ALPG800 has test data (WRITE
/ READ DATA), write and read addresses of test data, and control signals (WRITE control signal and READ control signal). The generated test data and control signal are sent to the PDS 820, and the address signal is sent to the address conversion circuit 810. The address conversion circuit 810 converts the address given from the ALPG800 into the physical address of the device under test, and converts the physical address into the PDS.
Send to 820. The PDS820 has a write / read physical address and an AL input from the address conversion circuit 810.
Appropriately select the control signal and test data input from PG800 and send to FC830. The FC830 prepares the input test data and the signal form of the physical address, and the VI / VO84
Send to 0. The VI / VO 840 adjusts the voltage of each signal to match the device under test and sends it to the test head 850.

The device under test is connected to the test head, the test data is written to an address of the device under test, the test data is read from the address, and if the written data and the read data are the same, the address is written. Is considered normal, and the test is performed by repeating this test for all addresses.

In the conventional system, when the device under test has multiple ports, one port is set with one address for testing. For example, write 1 port, read 2
In the case of a multi-port memory of ports, it has two address ports (selection 1 and selection 2), writing is performed using the address of selection 1, and the addresses of selection 1 and selection 2 are used simultaneously. Although reading can be performed, in the conventional test system, an address in selection 1 is set to write test data, and the address is set to selection 1 to read, and if the write data and the read data match. If normal and disagreement, it is regarded as abnormal. When testing the selection 1, only the selection 1 is tested, and no signal is input to the selection 2 (non-selected state). Then, after clearing the state of selection 1, only the selection 2 is tested.

[0008]

However, the conventional method has a problem that a test capable of guaranteeing the relationship between the ports of the multi-port memory cannot be performed.

That is, in the conventional method, only the test of each port among the multiple ports is performed, and the test when signals are simultaneously input to each port is not performed.
For example, in the case of a multi-port memory of the above-mentioned 1-input 2-output (having addresses of selection 1 and selection 2), if there is a short circuit between selection 1 and selection 2, each individual port alone It seems to be working correctly when I am testing. That is, in the case of the conventional multi-port memory, when the address of selection 2 is tested, writing / reading is performed to the address of selection 2 independently of the case of testing the address of selection 1. For this reason, it was not possible to detect that selection 1 and selection 2 were short-circuited.

Japanese Patent Laid-Open No. 63-2295 previously registered
No. 49 (Testing method for multi-port RAM) ”
I am trying to disclose a test method that guarantees the relationship between multiple ports using a plane and a pattern generator, but it does not disclose a means for generating multiple types of signals set for each port of the multiple ports, Poor feasibility.

It is an object of the present invention to disclose a test apparatus capable of guaranteeing the operation of the relationship between multiple ports in testing a multi-port memory, and to improve the test performance of the multi-port memory test. .

[0012]

A functional block diagram of the present invention is shown in FIG. The present invention relates to a host computer 1 and a multi-port type memory testing device connected to an external storage disk device 2, a magnetic tape device 3, an input device 4 and an output device 5 connected to an external bus of the host computer 1. It consists of 6. The host computer 1 performs each process of creating a test program, setting test conditions, and controlling test execution. The external storage disk device 2 and the magnetic tape device 3 are used to store the test program. Further, the input device 4 performs input processing by the user when creating a test program or setting test conditions. The output device 5 also outputs a test program, a test condition setting screen, and the like.

The test apparatus 6 includes a timing generator 60 for setting the processing timing of each unit in the test apparatus, a write / read address of a multiport type memory to be tested, test data, and a pattern generation for generating control signals. vessel
61, a programmable signal selection circuit 62 that appropriately selects each signal output from the pattern generator 61, a waveform shaping circuit 63 that shapes the waveform of each signal output from the programmable signal selection circuit 62, and an output from the waveform shaping circuit 63 The input / output voltage generating circuit 64 for adjusting the output voltage of the device under test 7 by applying a voltage suitable for the device under test 7 to each signal And a comparison circuit 66 for comparing the read data from the device under test 7 with the test data to judge whether the device under test 7 is good or bad.

The pattern generator 61 includes a standard address generating circuit 610 for generating a standard address and a conversion address generating circuit for generating an address from the standard address for each port of the multi-port type memory as the device under test 7.
620, a data generation circuit 630 for generating test data, and a control signal generation circuit 640 for generating control signals such as write / read control signals. Further, a test data storage circuit 650 for writing and storing the same data as the test data to be written in the device under test 7 at the same address is provided.

The standard address generation circuit 610 is a circuit similar to the address generation circuit of the existing test device for a single port memory, and uses the generated address as a standard address. Then, the conversion address generation circuit 620 generates a different address for each port of the multi-port type memory based on the standard address generated by the standard address generation circuit 610.

[0016]

Next, the operation of the block diagram shown in FIG. 1 will be described. Prior to the test of the multi-port memory, the user reads the test program stored in the external storage disk device 2 or the magnetic tape device 3 and inputs the test conditions via the input device 4. The test conditions include capacity information of a multi-port memory that is a device under test, setting information of address terminals, data input / output terminals, control signal terminals, etc., setting information of each signal waveform, input / output voltage, etc. The input test conditions are sent to each unit of the test apparatus 6 via the host computer 1.

During the test, the test apparatus 6 first writes the test data in the device under test 7. The standard address generation circuit 610 of the pattern generator 61 in the test apparatus 6 generates a standard address and sends the standard address to the conversion address generation circuit 620. The conversion address generation circuit 620 generates different addresses for the number of writable ports of the multi-port memory of the device under test 7. For example, when there is one writable port, one translated address is generated, and when there are two writable ports, two different translated addresses are generated. The generated one or more conversion addresses are sent to the test data storage circuit 650 and the programmable signal selection circuit 62 in the pattern generator 610.

A data generation circuit 630 in the pattern generator 61
Generates test data, which is also a test data storage circuit 650 and a programmable signal selection circuit in the pattern generator 610.
Send to 62.

Control signal generation circuit 64 in the pattern generator 61
0 generates a write control signal, which is also sent to the test data storage circuit 650 and the programmable signal selection circuit 62. The programmable signal selection circuit 62 appropriately selects the address of each writable port of the multi-port memory, the test data to be written, and the write control signal, and these signals are the waveform shaping circuit 63, the input / output voltage generation circuit 64, the test head
The data is sent to the device under test 7 via 65 and the test data is written.

At this time, the same write address, test data, and write control signal as those sent to the device under test 7 are also input to the test data storage circuit 650 in the pattern generator 61. The same test data is written in the same address as.

After the process of writing the test data in the device under test 7 and the test data storage circuit 650 is completed, the reading and the pass / fail judgment process are performed. First, as in the case of writing, the standard address generation circuit 610 in the pattern generator 61 is used.
Generates a standard address and sends the standard address to the translated address generation circuit 620. The translation address generation circuit 620
Different addresses are generated for the number of readable ports of the multi-port memory of the device under test 7. For example, when there are two readable ports, two different translation addresses are generated. The generated translation address is the pattern generator 610.
To the test data storage circuit 650 and the programmable signal selection circuit 62.

The control signal generation circuit 640 also generates a read control signal, which is also sent to the test data storage circuit 650 and the programmable signal selection circuit 62. The programmable signal selection circuit 62 appropriately selects the address and read control signal of each readable port of the multi-port type memory, and these signals are selected by the waveform shaping circuit 63 and the input / output voltage generation circuit 6.
4, sent to the device under test 7 through the test head 65,
Data is read from the plurality of readable ports of the device under test 7. The read data is the test head 6
5, sent to the comparison circuit 66 via the input / output voltage generation circuit 64.

At this time, the read control signal is also sent to the test data storage circuit 650, the test data is read from the same address as the device under test 7, and is sent to the comparison circuit 66 via the programmable signal selection circuit 62. Sent.

The comparison circuit 66 sequentially compares the data read from the same read address of the device under test 7 and the test data storage circuit 650, and if they match, the result is judged as good. Send to computer 1. The host computer 1 judges the pass / fail of the device under test 7 by integrating the test results of all pass / fail output from the comparison circuit 66.

In the case of a 1-port write, 2-port read multi-port memory, according to the present invention, when data is read from the first read port according to the standard address, the translated address obtained from the standard address is also obtained from the second read port. And read the data from the first read port and the read data from the second read port with the data read from the addresses corresponding to the first and second read ports of the test data storage circuit 650, respectively. The multi-port memory can be tested. Therefore, for example, when the first read port is short-circuited with the second read port, there is a conflict between the read data from the first read port and the read data from the second read port. Therefore, the data to be read from the first read port and the data to be read from the second read port correspond to the first read port and the second read port from the test data storage circuit 650, respectively. It will not match the data that is read. In this way, the present invention can detect a short circuit between two readable ports in a one-port write, two-port read multi-port memory.

[0026]

2 is a system configuration diagram of an embodiment of the present invention. In this embodiment, a host computer 200 such as a workstation or a personal computer, and an external storage device 210 such as a magnetic disk connected to a bus of the host computer 200 for storing a test program and test data, a test program, Magnetic tape storage device 230 for storing test data, input device 220 for inputting creation and modification of test programs and test data, input of execution commands, etc., display and printing of test programs and test results Assuming an output device 240, the test device 250 of the present invention is connected to the host computer 200.

The test apparatus 250 includes a timing generator TG (Timing Generator) 25 for generating the timing of the test operation.
5, ALPG (ALgorithmic Pat
ternGenerator) 260, a programmable test signal selection circuit PDS265 (Programmabl) for selecting control signals, test data, and addresses generated by ALPG260 according to the test order.
e Data Selector), WRITE / READ DATA storage circuit 270 that stores write / read data, waveform shaping circuit FC275 (Format Controller) that adjusts the signal form of control signals, test data, and address data, reference to be input to the device under test Input / output voltage generation circuit VI / VO that generates a voltage and a reference voltage that is output from the device under test
280, a test head 290 for generating a reference voltage for inputting the device under test and serving as an interface, and a socket 295 for connecting the device under test 299 to the test apparatus 250.

The input / output voltage generating circuit VI / VO 280 is an input voltage power source VI 281 for generating a reference voltage for giving "1" or "0" of data to the device under test 299, and the device under test.
Output voltage power supply VO282 for generating a reference voltage for discriminating between "1" and "0" of the output voltage from 299, device under test 299
Programmable power supply PPS283 for controlling the power supply voltage of
The digital signal comparison circuit DC284 compares the data output from the WRITE / READ DATA storage circuit 270 with the test data output from the device under test 299. Power supply for input voltage VI281, Power supply for output voltage VO282
The voltage setting of the programmable power supply PPS283 is set by the control of the host computer 200. For example, the device under test 299 is a TTL (transistor transistor).
logic), the input voltage power supply VI281 sets + 3V and 0V corresponding to the test data "1" and "0", respectively, and the output voltage power supply VO282 outputs the output voltages "1" and "0".
+ 1.5V is set as a reference voltage for determining the above.

Further, the test head 290 is a device under test 29.
A driver DR291 that drives a signal input to 9 and the voltage of the signal output from the device under test 299 are compared with the reference voltage output from the output voltage power supply VO282 to "1",
It comprises an output voltage comparison circuit 292 for determining "0".

The TG 255 generates test timing data under the control of the host computer 200. TG25
5 receives the signal from the ALPG 260, and the output of the TG 255 becomes the input of the digital signal comparison circuit 284 in the ALPG 260, FC 275 and VI / VO 280. Also AL
The PG 260 outputs test data, write / read control signals, and write / read addresses under the control of the host computer 200, but outputs signals to the TG 255, PDS 265, and WRITE / READ DATA memory circuit 270. Furthermore, PDS265 is ALP
G260, WRITE / READ DATA memory circuit 270
The signal from is input, and the selected address, test data, and control signal are input to FC275.

Further, the input voltage set by VI (power supply for input voltage) 281 in VI / VO 280 becomes the input of driver DR 291 in test head 290. Also, the output voltage set by the VO (output voltage power supply) 282 in the VI / VO 280 is also input to the output voltage comparison circuit CP (Comparator) 292 in the test head 290. VI
The digital signal comparison circuit 284 in the / VO280 is a PDS.
265 and TG255, the signal from the output voltage comparison circuit 292 in the test head 290 is input, and the output signal is ALP.
It becomes the input of G260.

Driver DR291 in test head 290
Is the signal from VI281 and FC275 in VI / VO, and the output is via socket 295 the device under test.
Input to 299. The output voltage comparison circuit 292 in the test head 290 outputs the output signal of the device under test 299 input via the socket 295 and the timing signal input from the digital signal comparison circuit 284 in the VI / VO 280.
The output voltage data set by the VO 282 in the VI / VO 280 is input, and the output signal is output to the digital signal comparison circuit 284 in the VI / VO 280. Although not shown, all the constituent elements in the test apparatus 250 are connected to the host computer 200 via a bus.

Next, the operation of this system configuration will be described.
A test program is created in advance on the host computer 200 and stored in the external storage device 210. Before starting the test, the user sets the test conditions of the device under test according to this test program. That is, as the test conditions, the operation timing of the device under test, the operation waveform of the device under test, the operating voltage level of the device under test, and the signal to be given to each port of the device under test are set. Host computer
The 200 indicates the set test conditions for each unit of the test equipment (TG255, ALPG260, PDS265, FC275, V
I / VO 280, test head 290).

The test pattern of the existing single-port memory is registered in the ALPG 260 as test data. The ALPG 260 also has a circuit that sets different addresses for each port of the multi-port memory. This circuit will be described later.

The operation at the time of executing the test will be described below. The test includes a write cycle for writing test data to the device under test and a read cycle for reading the data written in the write cycle to correctly write the data and determining whether the data can be read.

First, in the write cycle, ALPG26
0 is write address and test data, write control signal is PDS265, write address and test data is WR
Send to ITE / READ DATA memory circuit 270.

The PDS 265 receives the write address, the test data and the write control signal from the ALPG 260,
Send this to FC275. The FC 275 forms a signal waveform of the address signal and the test data signal, for example, an NRZ (no return zero) signal, an RZ signal, or an XO signal in accordance with the timing from the TG 255, and inputs these to the driver 291 of the test head 290. The driver 291 drives a signal with the input voltage of the device under test set by the VI 281 of the VI / VO 280, and sends a write control signal, a write address signal, and a test data signal to the device under test on the socket 295. This allows the device under test to
The test data is written to the write address.

On the other hand, the WRITE / READ DATA storage circuit 270 is composed of RAM and has a sufficient memory capacity. That is, the capacity is set to be larger than the memory capacity of the device under test. And ALPG26
The write address and the test data are received from 0, and the test data is written to the write address on the memory.

Multiport with multiple writable ports
For memory, ALPG 260 generates different write addresses and controls which address the PDS 265 assigns to which port. Then, the same write operation as described above is executed.

In the read cycle, first, ALPG26
0 indicates read address and read control signal PDS265
And WRITE / READ DATA storage circuit 270. The PDS265 sends the read address and the read control signal to the FC275 and the test head driver DR.
Via 291 to device under test 299 on socket 295.
As a result, the content of the read address of the device under test 299 is output from the output port.

When there are a plurality of readable ports,
The ALPG 260 generates different read addresses and controls which address the PDS 265 assigns to which port. Then, the memory contents of different read addresses are simultaneously read from the plurality of readable ports.

On the other hand, the WRITE / READ DATA storage circuit 270 receives the read address from the ALPG 260 and outputs the content of the read address to the digital signal comparison circuit 284 in the VI / VO 280 via the PDS 265.

The output signal output from the device under test 299 is input to the output voltage comparison circuit 292 in the test head 290. The output voltage comparison circuit 292 determines the voltage of the output signal and V
The output voltage of the device under test 299 set by VO282 in the I / VO280 is compared with the specified value to determine whether the output is a digital value "0" or "1". The output signal is converted into a digital signal in accordance with the timing signal input through the digital signal comparison circuit 284 and output to the digital signal comparison circuit 284 in the VI / VO 280.

The digital signal comparison circuit 284 is a WRIT.
E / READ DATA The expected value of the memory content received from the storage circuit 270 via the PDS 265 is compared with the digital value of the output signal of the device under test 299 received from the output voltage comparison circuit 292, and the read data from the device under test 299 is compared. Determines whether is equal to the expected value. If they are equal, it means that writing / reading can be correctly performed on the address, and if they are not equal, it means that the device under test 299 has a defective portion. The result of this determination is sent to the host computer 200 via a connection line (not shown).

When reading from multiple ports simultaneously,
Output voltage comparison circuit 292 and digital signal comparison circuit 28
4 obtains a timing signal from TG255 and sequentially performs comparison processing for each output of the multi-port.

The judgment processing by the digital signal comparison circuit 284 is completed, and the pass / fail result of the address of the memory is shown in the host computer 200.
When the host computer 200 is transmitted via the connection line between the host computer 200 and the digital signal comparison circuit 284 via the connection line between the 284 and the host computer 200, the digital signal comparison circuit 284
Sends a judgment completion signal to the WRITE / READ DATA storage circuit 270 and the ALPG 260.

Here, if, for example, two read ports of the device under test 299 are short-circuited, the data output from the standard address and the conversion address of the device under test 299 compete and the WRITE / READ DATA storage is performed. Circuit 270
It does not match the data read from. This allows
It turns out that two lead ports of the device under test 299 are short-circuited.

According to the present invention, in addition to the short circuit of the read port of the multi-port memory, the short circuit of the write port can be detected when the write port is multi-port. Furthermore, a short circuit between the read port and the write port can be detected.
Furthermore, it is possible to detect not only a short circuit between multiple ports, but also a case where address decoders are stuck or a malfunction occurs due to signal interference between bit lines running in parallel corresponding to the number of ports of a multi-port memory.

For example, when there are one or more writable ports, the short between the two writable ports is such that one is a writable port and the other is a readable port, so that the short circuit causes unsuitable data to be received. It is possible to detect that the data has been written in the test element by discrimination.

Also, there are two writable ports,
When the bit lines or word lines corresponding to the two writable ports in the device under test are short-circuited, the same data is written to the two shorted addresses, and the data is written to the three addresses from the two writable ports. Will be written. Therefore, ALPG26
By performing a test by exchanging scramblers that generate different write addresses for two writable ports within 0, and reading data from the shorted address, it can be seen that abnormal data was written to the shorted address.

Furthermore, when there are two or more writable ports and the conversion addresses output from the scrambler in the ALPG260 are short-circuited, if the scrambler is replaced, three addresses will be output from the two writable ports. Will be written in. Therefore, the abnormality of the read data can be detected.

As described above, the test process in consideration of the relation between the multiple ports of the multi-port memory is executed. Figure 3
FIG. 3 is an explanatory diagram of a multi-port memory that is an element under test of the test apparatus. A dual-port memory with one input and two outputs will be described as an example.

The memory has address lines (address A and address B) for designating two addresses, a data input line (data in), and two data output lines (data ou).
There are terminals for t 1 and data out 2), write control signals, read control signals, and the like.

In the case of a dual-port memory having one input and two outputs, data is written by, for example, designating an address with address A and writing write data from data in. On the other hand, for reading data, two addresses are designated by address A and address B, and data out 1 and data ou are specified.
Data is read simultaneously from two ports of t 2. That is, the address A specifies the WRITE / READ address, and the address B specifies the READ only address.

Recently, a 16 Mbit memory has been manufactured, but in such a large-capacity memory, addressing is divided into several parts. For example, the address is X,
By dividing into three, Y and Z, and specifying each,
One address is designated. Address A is designated by three addresses XADA, YADA, ZADA, and address B is designated by three addresses XADB, YADB, ZADB.

FIG. 4 is a system configuration diagram of an embodiment showing the ALPG 260 portion of FIG. 2 in more detail. This figure shows an example of the configuration of the ALPG 260 shown in FIG. 2, and the other units (host computer 200, external storage device 210, input device 220, magnetic tape storage device 230, output device 240, timing generation circuit TG255). , Programmable signal selection circuit PDS265, waveform shaping circuit FC275,
Input / output voltage generator VI / VO280, test head 290
Is the same as that of FIG. Here, the configuration of the ALPG 260 when the dual port memory as shown in FIG. 3 is used as the device under test will be described.

The ALPG 260 is a circuit (X address standard generation circuit 260 which generates a standard address which becomes an address of either one port of the dual port memory at the time of reading.
1, a Y address standard generation circuit 2611, a Z address standard generation circuit 2621) and an address conversion circuit (X address conversion circuit 2602, Y address conversion circuit 2612, Z address) that generates the address of the other port based on the standard address. Conversion circuit 2622), data generation circuit 2630 for generating test data,
It is composed of a control signal generation circuit 2640 that generates a write / read control signal. In addition, the test data of the device under test is stored at the same address as the device under test in the WRITE / R
An EAD DATA storage circuit 2650 is provided.

Standard address generation circuit (X address standard generation circuit 2601, Y address standard generation circuit 2611, Z address standard generation circuit 2621) and address conversion circuit (X address conversion circuit 2602, Y address conversion circuit 2612, Z address conversion circuit) 2622), as described with reference to FIG. 3, by designating the address of the device under test by dividing it into three addresses X, Y, and Z, there are three addresses for X, Y, and Z, respectively.

Each standard address generation circuit (2601,
2611, 2621) generate addresses similar to existing single-port memory test equipment. On the other hand, each address conversion circuit (2602, 2612, 2622) generates an address different from the standard address based on the standard address generated by the corresponding standard address generation circuit (2601, 2611, 2621). For example, the X address conversion circuit 2602 generates an address different from the X standard address based on the X standard address generated by the X address standard generation circuit 2601.

The data generation circuit 2630 has a memory area for storing test data, and the existing single port
The test pattern used in the memory test device is written. The test data is generated by reading the test pattern data from this memory area.

Next, the operation of this system will be described. The memory test includes a process of writing test data to the device under test 299, a process of reading data from the device under test 299, and a process of comparing the written data with the read data.

First, test data is written in the device under test. A standard address generation circuit (2601, 2611, 2621) in ALPG260 generates a standard address. Generated standard address (X standard address, Y standard address,
Z standard address) is PDS265 and WRITE / RE
It is input to the AD data storage circuit 2650. On the other hand, the data generation circuit 2630 generates test data and inputs it to the PDS 265 and the WRITE / READ data storage circuit 2650. The control signal generation circuit 2640 also generates a write control signal, which is also used by the PDS 265 and the WRITE / REA.
Input to the D data storage circuit 2650.

WRITE / READ data storage circuit 2650
At this time, a standard address, test data, and a write control signal are input, and the test data is written at the standard address of the memory.

The standard address, test data, and write control signal are also input to the PDS 265. PDS26
5 sets the standard address (address consisting of X standard address, Y standard address, Z standard address) to address A of the device under test, dual port memory, and FC275 and V together with the test data and write control signal.
The data is sent to the device under test through the I / VO 280 and the test head 290. As a result, the test data writing process to the standard address is performed.

By repeating the above processing, the device under test 299 and the WRITE / READ data storage circuit 26
Data writing to 50 is executed. Next, a reading process is performed. The control signal generation circuit 2640 generates a read control signal and sends it to the PDS 265. The PDS265 assigns a standard address to the address A of the dual port memory and a conversion address to the other address B, and these two addresses and the read control signal are assigned to the FC275, VI / VO280,
Send to test element via test head 290. As a result, data is simultaneously read from the two output lines (data out1 and data out2) of the device under test. Data out1
From, the data of address A, which is the standard address,
From the data out2, the data of the address B in which the conversion address is set is read. The two read data are sent to the VI / VO 280 via the test head 290.

Then, the comparison processing of the data read from the device under test 299 and the data read from the WRITE / READ data storage circuit 2650 is executed. PDS265 is
First, the data written in the standard address position of the WRITE / READ data storage circuit 2650 is read out VI / VO
Send to 280. VI / VO digital signal comparison circuit 284
Compares this data with the data read from the data out1 of the device under test. If they match, it means that the writing / reading of the address of the device under test is operating correctly, and if they do not match, it means that they are defective. next,
PDS265 is a WRITE / READ data storage circuit 2650
The data written in the converted address position of the above is read and sent to the VI / VO 280, and the VI / VO 280 compares this data with the data read from the data out2 of the device under test to determine whether the address is good or bad.

The two pass / fail results thus obtained are sent to the host computer 200. This read and determination process is repeated to determine the quality of the entire memory.
As described above, in the present system, it is possible to perform the memory test including the relationship between the two ports by writing different data to two different addresses and reading the data from both addresses at the same time.

FIG. 5 is an ALPG signal explanatory diagram of the test apparatus for the n-port memory of one embodiment. The figure mainly shows the configuration of the address generation circuit portion of the ALPG2600, and the data generation circuit 263 in the ALPG2600 is shown.
0, the control signal generation circuit 2640, and the WRITE / READ data storage circuit 2650 are omitted in the drawing. The data generation circuit 2630 and the control signal generation circuit 2640 are included in the ALPG main body portion in the same figure.

In the system configuration of this embodiment for an n-port memory, each address conversion circuit (X address conversion circuit 2602, Y address conversion circuit 2612, Z address conversion circuit 2622) has n-1 addresses. It consists of a conversion part. The X address conversion circuit 2602 comprises an X address conversion circuit A2602-1, an X address conversion circuit B2602-2, ..., An X address conversion circuit n2602-n-1, and the mth X address conversion circuit m2602-m is , X address standard generating circuit 2601 generates an X standard address as an input to generate an X translation address of the (m + 1) th port of the n port memory. The same applies to the Y address conversion circuit 2612 and the Z address conversion circuit 2622.

When the dual port memory is used as the device under test, the standard address generation circuit (2601, 2611, 2621) uses the address A of the dual port memory as the first address conversion circuit B (2602-1, 2612-1). , 2622-1) is designated by the PDS 265 to connect to the address B.

The output (input data D) of the data generation circuit 2630 of the ALPG main body is PDS265 and WRITE / RE.
It becomes an input of the AD data storage circuit 2650, and the output (WRITE control signal W and READ control signal R) of the control signal generation circuit 2640 is also PDS265 and WRITE / RE.
It becomes an input to the AD data storage circuit 2650. The output of each address conversion circuit (2602, 2612, 2622) is also input to the PDS 265 and the WRITE / READ data storage circuit 2650.

At the time of writing data, the output (XAD) of the first address conversion circuit (2602-1, 2612-1, 2622-1) is output.
A, YADA, ZADA) and WRITE control signal W, input data D is PDS265 and WRITE / RE
The data is sent to the AD data storage circuit 2650, and the same data is written in the same address of the device under test 299 and the WRITE / READ data storage circuit 2650.

At the time of data reading, the output of each address conversion circuit and the READ control signal R are sent to the PDS 265,
The PDS265 is a standard address generation circuit (2601,2611,262).
The output (XDA, YDA, ZDA) of 1) is used as the address of the first port of the n-port memory, and the output (XAD of the first address conversion circuit (2602-1, 2612-1, 2622-1)).
A, YADA, ZADA) to the address of the second port of the n-port memory, and the output of the n-1th address conversion circuit (2602-n-1, 2612-n-1, 2622-n-1) (XAD
(n, YADn, ZADn) is assigned as the address of the n-th port of the n-port memory, and the reading process of the device under test is executed.

On the other hand, the output of each address conversion circuit and REA
The D control signal R is the WRITE / READ data storage circuit 26.
Also sent to 50. First, the standard address generation circuit (2601,2
611,2621) output and READ control signal
The test data is read from the address of the E / READ data storage circuit 2650, and the VI / VO280 is read through the PDS265.
Then, the data is compared with the data read from the first port of the device under test 299. Next, the first address conversion circuit (26
02-1, 2612-1, 2622-1) output (XADA, YADA,
ZADA) and READ control signal, WRITE / R
The test data is read from the address of the EAD data storage circuit 2650, sent to the VI / VO 280 via the PDS 265, and compared with the data read from the second port of the device under test 299. The above processing is repeated n times to compare the data read from all the output ports of the n-port memory, which is the device under test, with the written data. FIG. 6 is an explanatory diagram of address conversion. For simplification of description, the case where the address is 2 bits is taken as an example.

For example, the X standard address generation circuit (2601,
(2611, 2621) is '00',
The first X address conversion circuit A2602-1 has an address of "0".
1 ', the second X address conversion circuit B2602-2 outputs the address'10', the third X address conversion circuit C2602-3
Each address conversion circuit generates a different address, such as address '11'.

FIG. 7 is a block diagram of an address conversion circuit of one embodiment. The address conversion circuit of this embodiment comprises an address scrambler 720. For example, the address scrambler 720 receives a standard address as a logical address, translates it into a physical address, and actually reads the translated address from the position of the physical address.

FIG. 8 is a block diagram of the address scrambler 720. Address Scrambler 720 is a decoder circuit
7201, an input buffer 7202, an output buffer 7203, and an address conversion data storage memory 710.

Assuming that one standard address data (for example, XDA) is given by 3 bits of A0, A1, A2, the standard address data (A0, A1, A2)
2) becomes a read address of the address conversion data storage memory 710 by the decoder circuit 7201, and the data of the read address is read as the conversion address data. For example, if the values of A0, A1 and A2 are 0, 0 and 0, the address M0 specified by the decoder is displayed.
, The contents 1, 1, 1 are output as the values 1, 1, 1 of the conversion address data A0A, A1A, A2A via the output buffer 7203. Thus, one standard address data A0, A1, A2 designates one port corresponding to one translation address.

The address conversion data storage memory 710
Data of the truth table A0A, A from the host computer 200 via the input buffer 7202 before the memory test.
It is assumed that 1A and A2A are stored at each address.

Address scrambler 710 as described above
An address conversion circuit consisting of is provided for each port,
Since the contents of the address conversion data storage memory 710 in the address scrambler corresponding to each port are different, different addresses are output from each port for the same standard address.

Such a circuit is used for each address conversion circuit (26
02, 2612, 2622) each port (2602-1, ... 2602-n-1,
2612-1, ... 2612-n-1, 2622-1, ..., 2622-n-1) are connected. The first address conversion circuit (26
02-1, 2612-1, 2622-1) are standard address generation circuits (2601
, 2611, 2621), the address may be converted and output. The address scrambler 720 of each port scrambles the standard address by obtaining the standard address and reading a different translation address from the address translation data storage memory 710 of each port.

FIG. 9 is a diagram for explaining the address conversion circuit of FIG. 7 by taking a case of a 2-bit address as an example. Translation addresses "01", "10", "11", and "00" are written in the address translation data storage memory 710. For example, the first address conversion circuit A (2602-1, 2612-1, 26)
22-1) Address Scrambler 720 has standard address "0"
The address is scrambled so as to obtain "0" and read "01" of the address conversion data storage memory 710. Then, another address conversion circuit has an address conversion data storage memory 710 storing a different conversion address, for example, 3 The address scrambler 720 of the second address conversion circuit C (2602-3, 2612-3, 2622-3) obtains the standard address "00" and reads the address "10" of the address conversion data storage memory 710. Scramble.

Since the capacitance of the device under test will vary, the number of address bits also changes depending on the capacitance of the device under test.
The address translation data storage memory 710 may store translation addresses corresponding to any number of address bits, and the address scrambler 720 may read out the translation address corresponding to the number of standard address bits.

FIG. 10 shows a WRITE / REA of one embodiment.
It is a block diagram of a D data storage circuit. WRITE / REA
The D data storage circuit 2650 is a multi-port RAM, and is configured to have a sufficient capacity equal to the maximum capacity of the device under test to be tested by this test apparatus. A test data storage circuit write / read control circuit for n ports is connected to the test data storage circuit.

Each address conversion circuit (2602-1, ...
・ 2602-n-1, 2612-1, ... 2612-n-1, 2622-1, ..., 26
22-n-1) is connected, the write control signal line W and the read control signal line R are connected to the output of the control signal generating circuit, and the data line D is connected to the output of the data generating circuit.

Further, a control signal for designating the identity of each address / port is set in advance from the host computer 200 to each test data storage circuit read / write control circuit, and the address / port n is write-only, read-only, write / read Specify both possible choices.

Addresses corresponding to each port are port 1
.., XADn are added to each test data storage circuit write / read control circuit together with the feature control signal of each address. further,
The write signal W and the read signal R from the ALPG are also added to each test data storage circuit write / read control circuit.

The function of the test data storage circuit write / read control circuit is as follows. That is, port n
If the feature control signal of is write-only, ALPG26
If only the write signal from 0 is valid and the feature control signal of port n is read-only, ALPG
When only the read signal from 260 is valid and the feature control signal of port n is both writable and readable, both the write signal and read signal from ALPG260 are valid.

Then, for example, when the feature control signal of the port 1 from the CPU is write-only, the write data is controlled by the write signal W from the ALPG to the address of the test data storage circuit designated by the port 1 address XADA. Written.

At the time of reading, data is read from the address position input to the address line, and PDS265
And is compared with the data read from the device under test. At the same time, expected value data (comparison data) read by being addressed by the nth address conversion circuit
Are sent to the PDS 265 and compared with the data read from the device under test. At the same time, the nth expected value data (comparison data) is sent to the PDS 265 and compared with the data read from the device under test.

[0091]

According to the present invention, it is possible to specify different addresses for each port by providing -1 address conversion circuit for the number of ports of the multi-port memory as the device under test. As a result, it becomes possible to perform a test considering the relationship between the ports, and the test performance of the multi-port memory is improved.

Further, it has a WRITE / READ data storage circuit, and the same test data to be written to the device under test is written to the same address as the write address of the device under test.
Reads the test data and the device under test by storing all with the same write signal sent to the device under test and reading the test data with the same read control signal from the same read address as the device under test. It is possible to easily judge whether the data matches or does not match, thus improving the test efficiency.

[Brief description of drawings]

FIG. 1 is a block diagram of the present invention.

FIG. 2 is a system configuration diagram of an embodiment.

FIG. 3 is an explanatory diagram of a multi-port memory (dual port
It is an example of a memory).

FIG. 4 is a system configuration diagram (ALPG configuration diagram) of an embodiment.

FIG. 5 is an ALPG signal explanatory diagram of the test apparatus for the n-port memory according to the embodiment.

FIG. 6 is an explanatory diagram of address conversion (example in the case of 2-bit address).

FIG. 7 is a configuration diagram of an address conversion circuit according to an embodiment.

FIG. 8 is a block diagram of address scrambling.

FIG. 9 is an explanatory diagram of an address conversion circuit (example in the case of 2-bit address).

FIG. 10 is a configuration diagram of a WRITE / READ data storage circuit according to an embodiment.

FIG. 11 is a block diagram of a conventional test apparatus.

[Explanation of symbols]

 1 host computer 2 external storage disk device 3 magnetic tape device 4 input device 5 output device 6 test device 7 device under test 60 timing generator 61 pattern generator 62 programmable signal selection circuit 63 waveform shaping circuit 64 input / output voltage generation circuit 65 test Head 66 Comparison circuit 610 Standard address generation circuit 620 Translated address generation circuit 630 Data generation circuit 640 Control signal generation circuit 650 Test data storage circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location G11C 11/401

Claims (11)

[Claims] 1. An apparatus for reading data from a predetermined address of a device under test (7) and testing the device under test (7), and generating a translated address based on the standard address generating means (610). And a read means (620) for applying the standard address and the translated address to the device under test (7) to read the data of the standard address and the data of the translated address from the device under test (7). 65), a test data storage unit (650) capable of reading data corresponding to the device under test (7) from the standard address and the conversion address corresponding to the device under test (7), and the reading unit (65). The read data is compared with the test data read from the test data storage means (650) to determine the quality of the device under test (7). Test apparatus characterized by comprising a comparison means that. 2. The conversion address generating means (620)
Is based on the standard address generated by the standard address
The n-1 different addresses of the port memory are generated to generate the device under test (7) and the test data storage means (650).
The test apparatus according to claim 1, wherein the test apparatus is sent to the. 3. The test data storage means (650) comprises:
The conversion address and test data for n-1 ports, the same conversion address and test data as the write / read control signal and the write / read control signal sent to the device under test (7) are received, and the device under test (7) is received. 2. The test apparatus according to claim 1, wherein the same test data is written to the same write address as the above, and the test data is read from the same read address as the device under test (7). 4. A host computer (1), an external storage disk device (2) for storing a test program, a magnetic tape device (3) for storing the test program, creation and modification of the test program, and setting of test execution conditions. A test apparatus having an input device (4) for inputting a test result, an output device (5) for displaying a test result, a test program, and a test condition, and a multi-port type memory for testing a multi-port type memory as a device under test. A standard address generation circuit (610) for generating a standard address, which is a pattern generator (61) for generating write / read addresses, test data, and control signals of a multi-port type memory serving as an element under test, From the standard address generated by the standard address generation circuit (610) to each port of the multi-port type memory serving as the device under test (7). A conversion address generating circuit (620) for generating different addresses, a data generating circuit (630) for generating test data, and a control signal generating circuit (640) for generating a control signal, and the pattern A programmable signal selection circuit (62) that appropriately selects each signal output from the generator (61), and a waveform shaping circuit (63) that shapes the waveform of each signal output from the programmable signal selection circuit (62). And an input / output voltage generation circuit (64) for adjusting the output voltage of the device under test (7) by applying a voltage suitable for the device under test (7) to each signal output from the waveform shaping circuit (63). A test head (65) serving as an input / output interface for transmitting each signal output from the input / output voltage generation circuit (64) to the device under test (7), The comparison circuit (66) for comparing the read data from the test device (7) with the test data to judge pass / fail of the device under test (7), the pattern generator (61) and the waveform shaping circuit (63). A timing generator (60) for setting a processing timing; and, the pattern generator (61) outputs the same data as the test data to be written in the device under test (7) to the device under test (7). Test data storage circuit (65
0) and a multi-port type memory testing device. 5. The conversion address generation circuit (620)
Is based on the standard address generated by the standard address
5. The multi-port memory test apparatus according to claim 4, wherein n-1 different addresses of the port memory are generated and sent to the programmable signal selection circuit (62) and the test data storage circuit (650). 6. The standard address generation circuit (610)
Is an X standard address among X standard address, Y standard address, Z standard address, or X standard address and Y standard address, or X standard address and Y standard address, and Z according to the addressing method of the device under test 7. A standard address is generated, and the conversion address generation circuit (620) according to claim 4 is the standard address generation circuit (61).
0) generated X standard address, or X standard address and Y standard address, or X standard address and Y
5. The multi-port memory test apparatus according to claim 4, wherein n-1 different addresses of the n-port memory are generated for each of the standard address and the Z standard address. 7. The data generating circuit (630) generates test data of the same number as the number of conversion addresses generated by the conversion address generating circuit (620), that is, the number of write ports of a multi-port memory, and the programmable data is generated. 5. The multi-port type memory testing device according to claim 4, wherein the test data is sent to a signal selection circuit (62) and a test data storage circuit (650). 8. The control signal generation circuit (640) sends the generated write control signal or read control signal to the programmable signal selection circuit (62) and the test data storage circuit (650). 4. The multi-port type memory testing device according to 4. 9. The test data storage circuit (650) comprises:
The conversion address generation circuit (620), the data generation circuit (630), and the control signal generation circuit (640) generate the conversion address and the test data for n-1 ports which are sent to the program signal selection circuit (62) and written. / Receive the same conversion address and test data as the read control signal, write / read control signal, write the same test data to the same write address as the device under test (7),
The test apparatus for a multi-port memory according to claim 4, wherein the test data is read from the same read address as that of the device under test (7). 10. The test data storage circuit (650).
Sends the read test data to the comparison circuit (66) via the program signal selection circuit (62), and the comparison circuit reads out this data and the target address read from the same address as the storage address of this data. 5. The multi-port type according to claim 4, wherein the data of the test element (7) is compared with each other, and if they match, it is determined that the device under test (7) is performing a normal operation and if they do not match, an abnormal operation is performed. Memory test equipment. 11. The conversion address generating circuit (620).
Is based on the standard address generated by the standard address
N to generate n different types of addresses in the port memory
Each address conversion circuit further comprises an address conversion data storage memory for storing the conversion address and an address scrambler for determining a read address of the address conversion data storage memory based on a standard address. The multi-port type memory testing device according to claim 5.