JPH07262712A - Prml reproducing circuit - Google Patents

Abstract

PURPOSE:To optimally set the distance of a slice level and to execute pertinent maximum likelihood decoding in the PRML reproducing circuit utilizing the formation of a partial response signal by maximum likelihood successive detection. CONSTITUTION:A signal read out of a storage disk by a head is waveform- equalized, and is then maximally likely-decoded and reproduced. For this purpose, the circuit is equipped with waveform equalizer circuits 12-15 for equalizing a waveform of the read-out signal, a maximum likelihood decoder 16 for maximally likely-decoding a decision value after obtaining the decision value by slicing the above equalize output at a +1 side s lice level and a -1 side slice level and a control circuit 19 for vaviably controlling the distance between the +1 side slice level and the -1 side slice level.

Description

Detailed Description of the Invention

(Table of Contents) Industrial Application Field of the Prior Art Problems to be Solved by the Invention Means for Solving the Problems (FIG. 1) Action Example (a) Description of PRML Reproducing Circuit (FIG. 2) (b) Description of maximum likelihood decoder (FIGS. 3 to 7) (c) Description of slice level automatic adjustment processing (FIGS. 8 to 9) (d) Description of adjustment circuit (FIGS. 10 to 11) (e) Adjustment processing (FIGS. 12 to 19) (f) Description of other embodiments

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PRML reproducing circuit that utilizes partial response signalization by maximum likelihood sequential detection, and more particularly to a PRML reproducing circuit that automatically adjusts the characteristics of each circuit according to signal quality.

In order to improve the recording density of magnetic disk and magneto-optical disk devices in recent years, partial response signalization (PRML: Partial-response) by maximum likelihood sequential detection is performed.
signaling with maximum-likelihood sequence detect
ion) is used. In such a PRML system, a PRML reproducing circuit for reproducing the read signal is provided.

[0004]

2. Description of the Related Art In a disk storage device utilizing partial response signalization, a reproducing circuit includes a waveform equalizing circuit,
And a maximum likelihood decoder. The reception filter group of the waveform equalization circuit of the reproduction circuit equalizes and shapes the output signal of the recording channel into a partial response signal. Then, the maximum-likelihood sequential detector (maximum-likelihood decoder) makes a ternary decision on the equalized signal, then performs maximum likelihood detection, and reconstructs the recorded data sequence.

Regarding such a PRML reproducing circuit,
Japanese Patent Publication 1990 No. 150114 (corresponding US Pat. No. 5060088), US Pat. No. 464.
4564, U.S. Pat. No. 4,707,681, U.S. Pat. No. 4,786,890, U.S. Pat.
It is disclosed in the specification of 888775 and the like.

In the conventional PRML reproducing circuit, the parameters of the waveform equalizing circuit and the maximum likelihood decoder are set to constant values when the device is shipped from the factory. Therefore, the characteristics of the waveform equalization circuit and the maximum likelihood decoder were constant. For example, in the ternary decision circuit of the maximum likelihood decoder, the distance between two slice levels for slicing the input signal was constant.

[0007]

However, the prior art has the following problems. Actually, the deterioration of the sampled signal quality due to the defect on the magnetic medium, the deterioration of the sampled signal quality when the inter-signal interference described by the polynomial (1-D) cannot be quantitatively controlled due to the equalization error, and the MR There is deterioration in signal quality due to variations in head characteristics. If an equalization error occurs due to such characteristics of the head, the magnetic medium, and the waveform equalization circuit, there is a problem that the above-described conventional technique in which the slice level distance is constant cannot perform effective maximum likelihood decoding.

On the other hand, if the characteristics of the head and the waveform equalization circuit are not appropriate, there is a problem that equalization error increases and optimum reproduction cannot be performed.

It is an object of the present invention to set a PR for executing optimum maximum likelihood decoding by optimally setting a slice level distance.
It is to provide an ML reproducing circuit.

Another object of the present invention is to provide a PRML reproducing circuit for minimizing the equalization error.

Still another object of the present invention is to set the characteristics of the head to the optimum so as to minimize the equalization error.
It is to provide a reproducing circuit.

Another object of the present invention is to set the characteristics of the waveform equalization circuit to the optimum value so as to minimize the equalization error.
It is to provide an L reproducing circuit.

[0013]

FIG. 1 shows the principle of the present invention. According to claim 1 of the present invention, the head 1
After waveform equalization of the signal read by 0, maximum likelihood decoding is performed,
In the PRML reproducing circuit for reproducing, the waveform equalizing circuits 12 to 15 for waveform equalizing the read signal and the equalized output are sliced at the +1 side slice level and the -1 side slice level to obtain a judgment value. , A maximum likelihood decoder 16 which performs maximum likelihood decoding of the judgment value, and the +1 side slice level and −1.
And a control circuit 19 for variably controlling the distance to the side slice level.

A second aspect of the present invention is the PRML of the first aspect.
The reproducing circuit further includes a memory 20 for holding the distance of each of the plurality of heads 10, and the control circuit 19 sets the distance corresponding to the selected head 10 in the maximum likelihood decoder 16. Characterize.

A third aspect of the present invention is the PRML of the first aspect.
The reproduction circuit further includes a decoder 17 for converting the m-bit output subjected to the maximum likelihood decoding to n bits (m> n), and an ECC circuit 18 for performing error detection and correction from the decoded n-bit output. Having the control circuit 19
Is characterized in that the distance is measured and held by the judgment output of the ECC circuit 18 when the +1 side slice level and the −1 side slice level are changed.

A fourth aspect of the present invention is the PRML of the second aspect.
The reproduction circuit further includes a decoder 17 for converting the m-bit output subjected to the maximum likelihood decoding to n bits (m> n), and an ECC circuit 18 for performing error detection and correction from the decoded n-bit output. Having the control circuit 19
Is characterized in that the distance is measured by the judgment output of the ECC circuit 18 when the +1 side slice level and the −1 side slice level are changed, and stored in the memory 20.

A fifth aspect of the present invention is the PRML of the first aspect.
The reproducing circuit further includes a memory 20 for holding each level width at a plurality of predetermined cylinder positions of each of the plurality of heads 10, and the control circuit 19 corresponds to the selected head 10 and the selected cylinder position. The distance to be set is set in the maximum likelihood decoder 16.

A sixth aspect of the present invention is the PRML of the first aspect.
In the reproducing circuit, the control circuit 19 sets an adjustment value in the waveform equalizing circuits 12 to 15.

A seventh aspect of the present invention is the PRML of the sixth aspect.
In the reproduction circuit, the waveform equalization circuits 12 to 15 are provided with the gain control amplifier 1 that gives a gain to the read signal.
2, an electric filter 13 that fixedly equalizes the output of the gain control amplifier 12, an analog-digital converter 14 that converts the output of the electric filter 13 into a digital value, and a cosine that equalizes the output of the analog-digital converter 14. Equalizer 15
And the control circuit 19 sets an offset value in the analog-digital converter 14.

The claim 8 of the present invention is the PRML of claim 7.
In the reproducing circuit, the control circuit 19 measures the offset value of the analog-digital converter 14 from the output of the cosine equalizer 15.

The claim 9 of the present invention is the PRML of claim 1.
In the reproducing circuit, the head 10 is an MR head, and the control circuit 19 sets a drive current value in the drive circuit 11 of the MR head.

A tenth aspect of the present invention is the PRM of the ninth aspect.
In the L reproduction circuit, the waveform equalization circuits 12 to 15 are
A gain control amplifier 12 for giving a gain to the read signal; an electric filter 13 for fixing and equalizing the output of the gain control amplifier 12; an analog-digital converter 14 for converting the output of the electric filter 13 into a digital value; Cosine equalizer 1 for equalizing the output of the analog-digital converter 14
5, and the control circuit 19 measures the drive current value of the MR head from the output of the cosine equalizer 15.

[0023] Claim 11 of the present invention is the PRM of claim 6.
In the L reproduction circuit, the waveform equalization circuits 12 to 15 are
A gain control amplifier 12 for giving a gain to the read signal; an electric filter 13 for fixing and equalizing the output of the gain control amplifier 12; an analog-digital converter 14 for converting the output of the electric filter 13 into a digital value; Cosine equalizer 1 for equalizing the output of the analog-digital converter 14
5, and the control circuit 19 sets the adjustment value of the filter in the electric filter 13.

The twelfth aspect of the present invention is the PR of the eleventh aspect.
In the ML reproducing circuit, the control circuit 19 measures the adjustment value of the electric filter 13 from the output of the cosine equalizer 15.

A thirteenth aspect of the present invention is the PRM of the sixth aspect.
In the L reproduction circuit, the waveform equalization circuits 12 to 15 are
A gain control amplifier 12 for giving a gain to the read signal; an electric filter 13 for fixing and equalizing the output of the gain control amplifier 12; an analog-digital converter 14 for converting the output of the electric filter 13 into a digital value; Cosine equalizer 1 for equalizing the output of the analog-digital converter 14
5, and the control circuit 19 sets an equalization coefficient in the cosine equalizer 15.

According to claim 14 of the present invention, the PR of claim 13
In the ML reproducing circuit, the control circuit 19 measures the equalization coefficient of the cosine equalizer 15 from the output of the cosine equalizer 15.

[0027]

According to the first and second aspects of the present invention, since the control circuit 19 variably controls the slice level distance of the maximum likelihood decoder 16, it is possible to perform the optimum ternary decision according to the equalization error amount.

The third and fourth aspects of the present invention include the control circuit 19
As a result, the slice level distance of the maximum likelihood decoder 16 is automatically adjusted, so that the optimum slice level width can be set.

According to the fifth aspect of the present invention, since the slice level distance is variable depending on each of the plurality of heads, the optimum slice level distance can be set according to the head variation.

In the sixth, seventh, eleventh and thirteenth aspects of the present invention, since the control circuit 19 sets the characteristics of the waveform equalization circuits 12 to 15, the characteristics can be set to appropriate characteristics with less equalization error.

According to the ninth aspect of the present invention, since the control circuit 19 sets the read characteristic of the MR head, it is possible to obtain an appropriate signal with a small equalization error.

Claims 8, 10, 12, and 14 of the present invention include:
Since the control circuit 19 automatically adjusts the characteristics of the waveform equalization circuit and the MR head, it is possible to set the optimum characteristics with a small equalization error.

[0033]

【Example】

(A) Description of PRML Reproducing Circuit FIG. 2 is a block diagram of a PRML reproducing circuit according to an embodiment of the present invention. This reproducing circuit is a magnetic recording / reproducing circuit to which the partial response class 4 and the maximum likelihood decoder are applied.

As shown in FIG. 3, an MR (magnetoresistive) head 10 is for reading data on a magnetic disk. The head IC circuit 11 is for driving the MR head 10. The gain control amplifier 12 is an MR
By applying a predetermined gain to the read signal of the head 10,
Output. The equalization filter (elecric filter) 13 has a characteristic of 1 + D, and the gain control amplifier 1
The output of 2 is fixed and equalized. The analog-digital conversion circuit 14 converts the binary data string at the signalization speed 1 / T to nT + τ
Sometimes, sampling is performed and a digital sample value Yn is output.

The cosine equalizer 15 is provided to correct the partial response characteristic of the disc in the radial direction. The tap coefficient of the cosine equalizer 4 is optimally adjusted according to the training pattern. And such a cosine equalizer 4
For example, it is configured by a well-known transversal filter as shown in Japanese Patent Publication No. 150114 of 1990 (corresponding US Pat. No. 5060088).

The maximum likelihood decoder 16 processes the output sample Yn of the cosine equalizer 15 and reconstructs the recording data string. The maximum likelihood decoder 16 detects the most probable sequence when reproducing a data sequence recorded by correlating data. For the operation of the maximum likelihood decoder 16, see “Optimal Reception for Bin
ary Partial Response Channels ", The Bell System Te
chnical Journal, Vol.51, No.2, February, 1992 (ATT). The configuration of the maximum likelihood decoder 16 will be described with reference to FIG.

The data sequence decoded by the maximum likelihood decoder 16 is converted into 9-bit data by the 8/9 decoder 17.
Converted to 8-bit data. This decoder 17 also
For example, it is well known from U.S. Pat. No. 4,707,681, U.S. Pat. No. 4,786,890 and the like. ECC
The circuit 18 detects an error in the data sequence decoded by the decoder 17 and corrects the error.

The control circuit 19 is composed of a microprocessor. The control circuit 19 observes an output sample value Yn of a sample detection circuit 21 described later, and automatically adjusts the head drive current of the head IC 11 so that the equalization error is minimized. Similarly, the control circuit 19 automatically adjusts the frequency characteristic of the electric filter 13, the offset voltage of the analog-digital conversion circuit 14, and the equalization coefficient of the cosine equalizer 15. Further, the control circuit 19
Automatically adjusts the slice level distance of the maximum likelihood decoder 16 according to the error detection result of the ECC circuit 18.

The memory 20 stores the adjusted offset voltage value of the analog-digital conversion circuit 14. The memory 20 also includes a head drive current value of the head IC 11 for each head, a frequency characteristic value of the electric filter 13, an equalization coefficient of the cosine equalizer 15, and a maximum likelihood decoder 16.
Stores the slice level distance of.

As will be described later with reference to FIG. 10, the sample detection circuit 21 has a sample value Y of the cosine equalizer 15.
The level of n is judged and the classified sample values are output. The sample detection circuit 21 is used by the control circuit 19 for automatic adjustment to minimize the equalization error.

(B) Description of Maximum Likelihood Decoder FIG. 3 is a block diagram of the maximum likelihood decoder of FIG. 2, FIGS. 4 and 5 are circuit diagrams of the maximum likelihood decoder, and FIG. 6 is a description of the operation of the maximum likelihood decoder. Figure,
FIG. 7 is a flowchart of the maximum likelihood decoding process.

As shown in FIG. 3, the input data string is divided into an odd column and an even column by the interleave circuit 16-3. The data of the odd-numbered columns is the maximum likelihood decoder 16-
Input to 1. Further, the data of even columns is input to the maximum likelihood decoder 16-2 for even columns.

The maximum likelihood decoders 16-1 and 16-2 include level slicers 30-1 and 30-2, slice level update circuits 31-1 and 31-2, and a data buffer 32-1.
32-2, pointers 33-1 and 33-2, and error detection circuits 34-1 and 34-2.

The level slicers 30-1 and 30-2 are +
1-side slice level Δn + 1 and -1-side slice level Δ
Level slicing is performed with n-1 to obtain a ternary judgment value Xn. The slice level update circuits 31-1, 31-2 are
The +1 side slice level Δn + 1 and the −1 side slice level Δn− according to the distance between the slice levels of the control circuit 19.
1 and are output to the level slicers 30-1 and 30-2.

The data buffers 32-1 and 32-2 are composed of serial registers and store a plurality of consecutive judgment values. The pointers 33-1 and 33-2 indicate the judgment value to be inspected. Error detection circuits 34-1, 34-2
Detects an error in the judgment value, and the data buffer 32-
Correct the judgment values of 1 and 32-2.

FIG. 4 shows details of the slice level updating circuit. As shown in FIG. 4, the timing registers 310, 3
11, the timing of the sample value Yn is adjusted.
In the slice amplitude setting register 312, the amplitude A of the slice level from the control circuit 19 is set as the distance.

Memory 20 connected to this control circuit 19
Stores the amplitude A at a predetermined cylinder position 0 to m for each head 0 to n. The stored cylinder positions 0 to m represent, for example, 1000 cylinders as one group, and the amplitude of one of the cylinder positions is represented as the amplitude of the group.

Therefore, when the control circuit 19 receives the head number to be selected and the cylinder position, it reads the amplitude of the group of the cylinder position of the head number from the memory 20, and sets it in the register 312.

The adder 313 subtracts the sample value Yn from the amplitude A set in the register 312. Adder 3
14 subtracts the amplitude A set in the register 312 from the sample value Yn. Slice initial value setting register 3
The initial value of the slice level is set to 15 in the control circuit 19. The polarity bit inversion circuit 316 is provided in the register 3
The 15 polarity bits are inverted to create the initial value of the slice level on the -1 side.

The selector 317 generates select signals for the pair of multiplexers 318 and 319 according to the judgment value 1PJOD. The selector 317 outputs the third input selection at the read start, outputs the first input selection at the time of detecting “1”, and outputs the second input selection at the time of detecting “−1”.

The + side multiplexer 318 has three input terminals and outputs the input of the terminal selected by the select signal as the +1 side slice level. The sample value Yn is input to the first input terminal, the output of the adder 313 is input to the second input terminal, and the initial level of the register 315 is input to the third input terminal. Therefore, the + side multiplexer 318, as shown in FIG.
As the +1 determination level Δn + 1, the initial level is output at the time of start, the sample value Yn is output at the time of detecting “1”, and (the set amplitude−the sample value) is output at the time of detecting “−1”.

The-side multiplexer 319 has three input terminals and outputs the input of the terminal selected by the select signal as the -1 side slice level. The output of the adder 314 is input to the first input terminal, the sample value Yn is input to the second input terminal, and the third input terminal is
The inversion initial level of the inversion circuit 316 is input. Therefore, the-side multiplexer 319, as shown in FIG.
As the −1 determination level Δn−1, the initial level is output at the start, (set amplitude−sample value) is output at the time of detecting “1”, and the sample value Y is detected at the time of detecting “−1”.
Output n.

As shown in FIG. 5, the level slicer 30
Is a comparator 300 that compares the sample value Yn with the + judgment slice level, a comparator 301 that compares the sample value Yn with the −judgment slice level, and both comparators 300 and 3.
And an EOR circuit 302 that takes the EXOR of the output of 01.

The comparator 300 outputs "1" when the sample value Yn is equal to or more than the + judging slice level. The comparator 301 outputs "1" when the sample value Yn is below the-judgment slice level. Therefore, the EOR circuit 302
Outputs "1" when the sample value Yn is above the + judgment slice level and when the sample value Yn is below the-judgment slice level. On the other hand, the EOR circuit 302 outputs “0” when the sample value Yn is between the + judging slice level and the −judging slice level.

The data buffer 32 is a reception register 32.
It has 0, five stages of buffer registers 321-325, and four AND gates 326-329. The reception register 320 holds the output of the EOR circuit 302. The five-stage buffer registers 321 to 325 have five stages because the continuation of “0” is limited by 5.

AND gates 326 to 329 have data clear signal DTCLR and pointer signal CNTFF2OD.
It is the logical product of CNTFF5OD. The data clear signal DTCLR is input to the clear terminal of the register 321. Other registers 322-
The clear terminals of 325 have AND gates 326 to 3 respectively.
29 outputs are input.

The pointer 33 is composed of a 5-bit shift register. The pointer 33 has a clock Clo.
In accordance with ck, pointer signals CNTFF2OD to CNT are sequentially output.
Output NTFF5OD, counter reset signal CNT
Reset by RST.

The error detection circuit 34 includes an AND gate 340.
, A register 341, and a pair of EOR circuits 342, 34.
3 and an OR circuit 344. And gate 340
When the output of the EOR circuit 302 is "1", the clock is output to perform the error detection operation. The register 341 holds the output of the comparator 300.

The EOR circuit 342 takes the EXOR of the output of the register 341 and the output of the comparator 300. The EOR circuit 342 takes the EXOR of the inverted Q output of the register 341 and the output of the comparator 301.
The OR circuit 344 calculates the logical sum of the EOR circuits 341 and 342 and outputs the data clear signal DTCLR.

Therefore, X which is the output of the EOR circuit 302
When (n−j) is not “0”, EOR circuits 342, 3
At 43, it is determined whether the determination value X (n−j) and the determination value X (n) match. If the judgment value X (n-j) and the judgment value X (n) match, the OR circuit 344 outputs the data clear signal DTCLR. As a result, the contents held in the buffer registers 321 to 325 indicated by the pointer signal are cleared to "0", and the error is corrected.

Therefore, by the circuit of FIG. 4, the slice level fluctuates and the amplitude a is variably controlled by each head and each cylinder position, as shown in FIG.

FIG. 7 is a maximum likelihood decoding flow for obtaining the maximum likelihood decoding sequence yn when the sample value Yn is input. Figure 7
As shown in, the determination level is changed by the processing within the dotted line in the figure. When the output X (n−j) of the EOR circuit 302 is not “0”, the EOR circuit 34
2 and 343, the judgment value X (n-j) and the judgment value X (n)
It is determined whether and match. If the judgment value X (n-j) and the judgment value X (n) match, the OR circuit 344 outputs the data clear signal DTCLR. Thereby, the buffer registers 321 to 32 indicated by the pointer signal
The stored contents of 5 are cleared to "0" and the error is corrected.

As described with reference to FIG. 5, in FIG. 7, a modulation / demodulation code is used to limit the number of consecutive 0s in the binary signal sequence to be recorded, in order to limit the circuit scale of the decoder. In FIG. 5 and FIG. 7, the case where 0 continues is limited to “5”. The condition is reflected by j ≦ 5 in FIG.
Further, in FIG. 7, Yn takes three values of [0, +2, −2], but actually, as described in FIG. 5, binary data replaced with [0, 1] is output. Dn of FIG. 7 corresponds to this.

(C) Description of Automatic Slice Level Adjustment Processing FIGS. 8 and 9 are flowcharts of slice level adjustment processing. (S1) The control circuit (hereinafter referred to as a processor) 19 drives an actuator (not shown) to cause the head to seek the target cylinder.

(S2) The processor 19 uses the maximum likelihood decoder 1
The slice level distance (amplitude) A is set to the maximum value in the amplitude setting register 312 of No. 6. Next, the processor 19
Writes the recording data to the cylinder with the head described above. Further, the processor 19 selects the head 0.

(S3) The processor 19 reads print data from the selected head. This read data is
The ECC circuit 18 performs an error check through the route shown in FIG. The processor 19 checks from the judgment output of the ECC circuit 18 whether a data error has occurred with a specified number of bits.

(S4) When the processor 19 determines that a data error has occurred with the specified number of bits, it reduces the slice level distance A by ΔV. And this is register 3
12 is written, and the process returns to step S3.

(S5) When the processor 19 determines that an error has not occurred with the specified number of bits, it stores the slice level distance A as an upper limit value. Next, the processor 19 causes the maximum likelihood decoder 16 to set the amplitude setting register 312.
Then, the slice level distance (amplitude) A is set to the minimum value.

(S6) The processor 19 reads print data from the selected head. This read data is
The ECC circuit 18 performs an error check through the route shown in FIG. The processor 19 checks from the judgment output of the ECC circuit 18 whether a data error has occurred with a specified number of bits.

(S7) When the processor 19 determines that a data error has occurred with the specified number of bits, the slice level distance A is increased by ΔV. And this is register 3
12 is written, and the process returns to step S6.

(S8) When the processor 19 determines that an error has not occurred in the specified number of bits, it stores the slice level distance A as a lower limit value. Next, the processor 19 calculates (upper limit value−lower limit value) / 2. Then, the processor 19 stores this in the memory 20 (see FIG. 4) as the distance A at the slice level of the current cylinder and the current head.

(S9) Next, the processor 19 checks whether the designated head is the maximum (MAX) head. If the designated head is not the maximum head, increment the designated head address by 1,
Return to step S3. On the other hand, if the designated head is the maximum head, the processor 19 checks whether adjustment of all setting cylinders has been completed. For example, the adjustment cylinder is
Set every 100 cylinders. When the processor 19 determines that the adjustment of all the setting cylinders has not been completed, the processor 19 seeks to the next cylinder, and returns to step S2.
On the contrary, when the processor 19 determines that the adjustment of all the setting cylinders is completed, the adjustment is completed.

In this way, as shown in FIG. 4, the optimum slice level distances (amplitudes) at the set cylinder positions of all heads are stored in the memory 20. This operation is performed at the time of factory shipment. Then, at the time of normal access, the processor 19 receives the selected head address and the cylinder address, reads the distance of the cylinder corresponding to the selected head address and set for the cylinder address from the memory 20. This is set in the amplitude setting register 312 of the maximum likelihood decoder 16.

Therefore, it is possible to set the distance having the maximum margin according to the characteristics of the head and the waveform equalizing circuit. As a result, maximum likelihood decoding can be executed at the optimum slice level.
Further, since the characteristics differ depending on the head, the slice level is adjusted to be optimum for each head. Further, since the change of the recording density depending on the cylinder position also affects the reproduction signal, the maximum likelihood decoding is executed at the optimum slice level according to the cylinder position.

(D) Description of Adjustment Circuit FIG. 10 is a block diagram of an adjustment circuit according to an embodiment of the present invention, FIG.
Reference numeral 1 is an explanatory diagram of the memory.

In the magnetic recording / reproducing circuit, the S / N of the signal is deteriorated due to various factors, and there is a high probability that the reproduced signal will be erroneous. This is due to the A / D conversion circuit 14 for sampling.
Offset voltage, the vertical asymmetry of the reproduced signal due to the deviation of the bias magnetic field of the MR head 10, the equalization error due to the adjustment deviation of the electric filter 13, the equalization error due to the adjustment deviation of the cosine equalizer 15, the variation in the characteristics of the reproduction head, and the cylinder position. There is a change in recording density due to.

In FIG. 10, the same components as those explained in FIG. 2 are designated by the same symbols. In the write register 40, the bias current value of the MR head 10 is written by the processor 19. The D / A converter 41 converts the bias current value written in the write register 40 into an analog amount and supplies it to the bias current drive circuit of the head IC 11.

In the write register 42, the frequency characteristic value (cutoff frequency or the like) of the electric filter 13 is written by the processor 19. The D / A converter 43 converts the frequency characteristic value of the electric filter written in the write register 42 into an analog amount, and controls the frequency characteristic of the electric filter 13.

In the write register 44, the offset value of the analog-digital conversion circuit 14 is written by the processor 19. The D / A converter 45 converts the offset value of the analog-digital converter 14 written in the write register 44 into an analog amount, and the addition amplifier 14 provided in the preceding stage of the analog-digital converter 141.
Output to 0. The addition amplifier 140 subtracts the offset amount of the D / A converter 45 from the output of the electric filter 13 to obtain the analog-digital converter 1
Enter in 41.

The write register 46 is written with the coefficient of the cosine equalizer 15 by the processor 19 and outputs it to the coefficient setting register of the cosine equalizer 15.

The sample detection circuit 21 shown in FIG. 2 is a level discriminator 21 for discriminating the sample value Yn into a ternary level.
0, three write registers 211 to 213, and three read registers 214 to 216.

The level determiner 210 compares the level of the sample value Yn with the +1 determination level and the -1 determination level, and classifies them into the determination values Xn of +1, 0, -1. The write register 211 has a sample value Y when the judgment value Xn is +1.
n is written. The write register 212 displays the determination value X
When n is 0, the sample value Yn is written. The write register 213 has a sample value Y when the judgment value Xn is -1.
n is written.

The read register 214 is the processor 19
Holds the contents of the write register 211,
Notify the processor 19. The read register 215 is
According to the instruction from the processor 19, the contents of the write register 212 are held and notified to the processor 19. The read register 216 holds the contents of the write register 213 according to an instruction from the processor 19 and notifies the processor 19 of the contents.

As shown in FIG. 11, the memory 20 has an adjusted drive current value (bias current value), a filter constant value (frequency characteristic value) and a filter at the adjustment cylinder positions 0 to m of the heads 0 to n. Store the coefficient.

At the time of normal access, the processor 19
Receives the selected head address and the cylinder address, and reads the cylinder drive current, the filter constant value, and the filter coefficient corresponding to the selected head address and set for the cylinder address from the memory 20. This is set in the write registers 40, 42 and 46, respectively. As a result, a reproduction signal in which vertical asymmetry due to the characteristics of the MR head 10 is compensated can be obtained. Further, the adjustment deviation of the electric filter 13 can be compensated. Furthermore, the adjustment deviation of the cosine equalizer 15 can be compensated.

(E) Description of Adjustment Process FIGS. 12 and 13 are offset voltage adjustment flow charts of the analog-digital converter.

The adjustment of the offset voltage of the analog-digital converter is to check the offset voltage of the analog-digital converter itself without performing the read operation.

(S1) The processor 19 initializes the parameters A, B, C, D and N to "0". Next, the processor 19 sets the initial operation value of the correction D / A converter 45 of the write register 44 to the default value. Further, the processor 19 stops the read operation and stops the input to the summing amplifier 140 of the analog-digital converter 14.

(S2) In this state, the processor 19
A predetermined number of sample values Yn when Xn = 0 are read from the read register 215. Then, the processor 19 calculates the average value A of the sample values Yn taken in by a predetermined number.

(S3) The processor 19 sets the error C to (B
-It is calculated from the absolute value of A). Here, B is Xn = 0
Is the ideal sample value at. In this example, it is set to "0".

(S4) Next, the processor 19 checks whether the parameter N is "0". (S5) If N is “0”, the processor 19 updates the previous measurement value D with C because it is the first process. Next, the processor 19 stores N in the memory 20 in association with the operation amount of the correction converter. Further, the processor 19
Is added to the operation amount of the correction D / A converter. This is stored in the write register 44 and the correction D / A converter 45
Write as the operation amount of. Further, the processor 19 is
To N + 1. Then, the process returns to step S2.

(S6) When N is not "0", the processor 19 compares the previous measured value D with the present measured value C. If D> C, the previous measurement value is not the minimum value, and the process returns to step S5. On the contrary, if D> C is not established, the previous measurement value is the minimum value. Therefore, the operation amount of the correction D / A converter at the time of N-1 at the previous time is set as the adjustment result, and
Hold at 0.

In this way, the manipulated variable that minimizes the offset voltage of the analog-digital converter 141 is measured and stored in the memory 20. Then, at the time of operation, the optimum manipulated variable is read out and added to the default value and set in the register 44. As a result, the offset voltage of the analog-digital converter 141 can be minimized.

14 and 15 are flow charts for adjusting the characteristics of the MR head. (S1) The processor 19 drives an actuator (not shown) to cause the head to seek the target cylinder.

(S2) The processor 19 initializes the parameters A, B, C, D and N to "0". Next, the processor 19 writes the recording data in the cylinder with the head. Further, the processor 19 selects the head 0.

(S3) The processor 19 uses the correction D / A
The set value of the converter 41 is set to the default value. That is, the default value is written in the write register 40. Next, the processor 19 reads the print data from the selected head.

(S4) In this state, the processor 19
A predetermined number of sample values Yn when Xn = 0 are read from the read register 215. Then, the processor 19 calculates the average value A of the sample values Yn taken in by a predetermined number.
Further, the processor 19 calculates the error C from the absolute value of (BA). Here, B is an ideal sample value when Xn = 0. In this example, it is set to "0".

(S5) Next, the processor 19 checks whether the parameter N is "0". (S6) If N is “0”, the processor 19 updates the previous measurement value D with C because it is the first process. Next, the processor 19 stores N in the memory 20 in association with the operation amount of the correction converter. Further, the processor 19
Is added to the operation amount of the correction D / A converter. This is stored in the write register 40 and the correction D / A converter 41
Write as the operation amount of. Further, the processor 19 is
To N + 1. Then, the process returns to step S4.

(S7) When N is not "0", the processor 19 compares the previous measured value D with the present measured value C. If D> C, the previous measurement value is not the minimum value, and the process returns to step S6. On the contrary, if D> C is not established, the previous measurement value is the minimum value. For this reason, the operation amount of the correction D / A converter at the time of N-1 last time is stored in the memory 20 shown in FIG. 11 as the adjustment result of the cylinder position of the head.

(S8) Next, the processor 19 checks whether the designated head is the maximum (MAX) head. If the designated head is not the maximum head, increment the designated head address by 1,
Return to step S3.

(S9) On the other hand, if the designated head is the maximum head, the processor 19 checks whether adjustment of all setting cylinders has been completed. For example, the adjustment cylinder is
Set every 100 cylinders. When the processor 19 determines that the adjustment of all the setting cylinders has not been completed, the processor 19 seeks to the next cylinder, and returns to step S2.
On the contrary, when the processor 19 determines that the adjustment of all the setting cylinders is completed, the adjustment is completed.

In this way, as shown in FIG. 11, the optimum bias current values at the set cylinder positions of all the heads are stored in the memory 20. This operation is performed at the time of factory shipment. Then, at the time of normal access, the processor 19 receives the selected head address and the cylinder address, reads the bias current value corresponding to the selected head address and set for the cylinder address from the memory 20. This is set in the write register 40.

In this way, the bias current of the MR head 10 is set so as to minimize the level of the sample value Yn at the judgment value Xn = 0.
The vertical asymmetry of the read waveform due to the characteristics of can be minimized. Further, since the change in recording density depending on the cylinder position also affects the reproduced signal, the optimum bias current value is set according to the cylinder position.

16 and 17 are flow charts for adjusting the characteristic of the electric filter. (S1) The processor 19 drives an actuator (not shown) to cause the head to seek the target cylinder.

(S2) The processor 19 initializes the parameters A and B to "0". Next, the processor 19
Writes the recording data to the cylinder with the head. Further, the processor 19 selects the head 0.

(S3) The processor 19 uses the correction D / A
The set value of the converter 43 is set to the default value. That is, the default value is written in the write register 42. Next, the processor 19 reads the print data from the selected head.

(S4) In this state, the processor 19
From any of the read registers 214 to 216, Xn =
A predetermined number of sample values Yn for X are read. This X is
It is one of +1, 0, and -1. Then, the processor 19 calculates (maximum value-
Calculate the minimum value). This is designated as A. This (maximum value −
Instead of calculating the (minimum value), the standard deviation may be calculated and used as A.

(S5) Next, the processor 19 checks whether the parameter N is "0". (S6) If N is “0”, the processor 19 updates the previous measurement value B with A for the first time processing. Next, the processor 19 stores N in the memory 20 in association with the operation amount of the correction converter. Further, the processor 1
9 is added to the operation amount of the correction D / A converter by Δ. This is stored in the write register 42, and the correction D / A converter 4
It is written as an operation amount of 1. Further, the processor 19
Update N to N + 1. Then, the process returns to step S4.

(S7) When N is not "0", the processor 19 compares the previous measured value B with the present measured value A. If B> A, the previous measurement value is not the minimum value, and the process returns to step S6. On the contrary, if B> A is not satisfied, the previous measurement value is the minimum value. For this reason, the operation amount of the correction D / A converter at the time of N-1 last time is stored in the memory 20 shown in FIG. 11 as the adjustment result of the cylinder position of the head.

(S8) Next, the processor 19 checks whether the designated head is the maximum (MAX) head. If the designated head is not the maximum head, increment the designated head address by 1,
It returns to step S3 of FIG.

(S9) On the other hand, if the designated head is the maximum head, the processor 19 checks whether the adjustment of all setting cylinders has been completed. For example, the adjustment cylinder is
Set every 100 cylinders. When the processor 19 determines that the adjustment of all the setting cylinders has not been completed, the processor 19 seeks to the next cylinder, and returns to step S2.
On the contrary, when the processor 19 determines that the adjustment of all the setting cylinders is completed, the adjustment is completed.

Thus, as shown in FIG. 11, the optimum frequency characteristic values at the set cylinder positions of all the heads are stored in the memory 20. This behavior is
It is done at the factory. Then, at the time of normal access, the processor 19 receives the selected head address and the cylinder address, and outputs the frequency characteristic value corresponding to the selected head address and set to the cylinder address.
Read from the memory 20. Write this to the write register 42
Set to.

In this way, the frequency characteristic value of the electric filter 13 is set so as to minimize the difference or standard deviation between the maximum value and the minimum value of the sample value Yn at the judgment value Xn = X. Adjustment error can be minimized. Further, since the characteristics are different for each head, it is set for each head. Furthermore, since the change in the recording density depending on the cylinder position also affects the reproduction signal, the optimum frequency characteristic value is set according to the cylinder position.

18 and 19 are flow charts for adjusting the characteristics of the cosine equalizer. (S1) The processor 19 drives an actuator (not shown) to cause the head to seek the target cylinder.

(S2) The processor 19 initializes the parameters A and B to "0". Next, the processor 19
Writes the recording data to the cylinder with the head. Further, the processor 19 selects the head 0.

(S3) The processor 19 sets the set value of the coefficient setting register of the cosine equalizer to the default value. That is, the default value is written in the write register 46. Next, the processor 19 reads the print data from the selected head.

(S4) In this state, the processor 19
A predetermined number of sample values Yn when Xn = X is read from any of the read registers 214, 215, and 216.
This X is one of +1, 0, and -1. And
The processor 19 calculates (maximum value-minimum value) of the sample values Yn acquired by a predetermined number. This is designated as A. Instead of calculating this (maximum value-minimum value), the standard deviation may be calculated and used as A.

(S5) Next, the processor 19 checks whether the parameter N is "0". (S6) If N is “0”, the processor 19 updates the previous measurement value B with A for the first time processing. Next, the processor 19 stores N in the memory 20 in association with the operation amount of the correction converter. Further, the processor 1
9 is added to the operation amount of the correction D / A converter by Δ. This is written in the write register 46 as the operation amount of the coefficient setting register. Further, the processor 19 sets N to N +
Update to 1. Then, the process returns to step S4.

(S7) When N is not "0", the processor 19 compares the previous measured value B with the present measured value A. If B> A, the previous measurement value is not the minimum value, and the process returns to step S6. On the contrary, if B> A is not satisfied, the previous measurement value is the minimum value. For this reason, the operation amount of the correction D / A converter at the time of N-1 last time is stored in the memory 20 shown in FIG. 11 as the adjustment result of the cylinder position of the head.

(S8) Next, the processor 19 checks whether the designated head is the maximum (MAX) head. If the designated head is not the maximum head, increment the designated head address by 1,
It returns to step S3 of FIG.

(S9) On the other hand, if the designated head is the maximum head, the processor 19 checks whether the adjustment of all setting cylinders has been completed. For example, the adjustment cylinder is
Set every 100 cylinders. When the processor 19 determines that the adjustment of all the setting cylinders has not been completed, the processor 19 seeks to the next cylinder, and returns to step S2.
On the contrary, when the processor 19 determines that the adjustment of all the setting cylinders is completed, the adjustment is completed.

Thus, as shown in FIG. 11, the optimum filter coefficients at the set cylinder positions of all the heads are stored in the memory 20. This operation is performed at the time of factory shipment. At the time of normal access, the processor 19 receives the selected head address and the cylinder address, reads the filter coefficient corresponding to the selected head address and set for the cylinder address from the memory 20. This is set in the write register 46.

In this way, the frequency characteristic value of the cosine equalizer 15 is set so as to minimize the difference or standard deviation between the maximum value and the minimum value of the sample value Yn at the judgment value Xn = X. The adjustment error of can be minimized. Further, since the characteristics are different for each head, it is set for each head. Further, since the change in recording density depending on the cylinder position also affects the reproduction signal, the optimum filter coefficient is set according to the cylinder position.

(F) Description of Other Embodiments In addition to the above embodiments, the present invention can be modified as follows. Although the n / m decoder has been described as an 8/9 decoder, it is also possible to use one having another number of bits.

Although the magnetic disk device has been described, the present invention is also applicable to a magneto-optical disk device and the like. Although the present invention has been described with reference to the embodiments, various modifications are possible within the scope of the gist of the present invention, and these modifications are not excluded from the scope of the present invention.

[0126]

As described above, according to the present invention,
It has the following effects. Since the control circuit 19 variably controls the slice level distance of the maximum likelihood decoder 16, it is possible to perform the optimum ternary determination according to the equalization error amount. Therefore, the optimum maximum likelihood decoding operation according to the characteristics of the equalization circuit and the head becomes possible.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a block diagram of a PRML reproducing circuit according to an embodiment of the present invention.

FIG. 3 is a block diagram of a maximum likelihood decoder according to an embodiment of the present invention.

4 is a circuit diagram (No. 1) of the maximum likelihood decoder in FIG.

5 is a circuit diagram (No. 2) of the maximum likelihood decoder in FIG.

FIG. 6 is an operation explanatory diagram of a maximum likelihood decoding operation.

FIG. 7 is a maximum likelihood decoding flowchart.

FIG. 8 is a flow chart (No. 1) of slice level adjustment processing according to an embodiment of the present invention.

FIG. 9 is a flowchart (No. 2) of slice level adjustment processing according to the embodiment of the present invention.

FIG. 10 is a block diagram of an adjustment circuit.

11 is an explanatory diagram of the memory of FIG.

FIG. 12 is a flowchart (No. 1) of offset voltage adjustment according to an embodiment of the present invention.

FIG. 13 is a flowchart (No. 2) of offset voltage adjustment according to the embodiment of the present invention.

FIG. 14 is a characteristic adjustment flow chart (No. 1) of the MR head according to the embodiment of the present invention.

FIG. 15 is a characteristic adjustment flow chart (No. 2) of the MR head according to the embodiment of the present invention.

FIG. 16 is a characteristic adjustment flow chart (No. 1) of the eleclick filter according to the embodiment of the present invention.

FIG. 17 is a characteristic adjustment flowchart (part 2) of the eleclick filter according to the embodiment of the present invention.

FIG. 18 is a characteristic adjustment flow chart (No. 1) of the cosine equalizer according to the embodiment of the present invention.

FIG. 19 is a characteristic adjustment flow chart (No. 2) of the cosine equalizer according to the embodiment of the present invention.

[Explanation of symbols]

 10 MR Head 11 Head IC 12 Gain Control Amplifier 13 Equalization Filter 14 A / D Conversion Circuit 15 Cosine Equalizer 16 Maximum Likelihood Decoder 17 8/9 Decoder 18 ECC Circuit 19 Control Circuit 20 Memory

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] March 3, 1995

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0071

[Correction method] Change

[Correction content]

(S8) When the processor 19 determines that an error has not occurred in the specified number of bits, it stores the slice level distance A as a lower limit value. Next, the processor 19 calculates (upper limit value + lower limit value) / 2. Then, the processor 19 stores this in the memory 20 (see FIG. 4) as the distance A at the slice level of the current cylinder and the current head.

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Correction target item name] Figure 9

[Correction method] Change

[Correction content]

[Figure 9]

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H03H 17/00 A 8842-5J H03M 13/12 8730-5J H04L 25/497 9199-5K

Claims (14)

[Claims] 1. A PRML reproducing circuit for waveform-equalizing a signal read by a head (10) from a storage disk, performing maximum-likelihood decoding, and reproducing the waveform. 12-
15), slicing the equalized output with a +1 side slice level and a −1 side slice level to obtain a judgment value, and a maximum likelihood decoder (16) for performing maximum likelihood decoding of the judgment value; A PRML reproducing circuit having a control circuit (19) for variably controlling a distance between the side slice level and the -1 side slice level. 2. The PRML reproducing circuit according to claim 1, further comprising a memory (20) for holding a distance of each of the plurality of heads (10), wherein the control circuit (19) includes the selected head (10). ) Is set in the maximum likelihood decoder (16), the PRML reproducing circuit. 3. The PRML reproducing circuit according to claim 1, wherein the maximum likelihood decoded m-bit output is n bits (m>
n), and a ECC circuit (18) that performs error detection and correction from the decoded n-bit output, and the control circuit (19) includes the +1 side slice level. A PRML reproducing circuit, wherein the distance is measured and held by the judgment output of the ECC circuit (18) when the slice level on the 1st and -1 sides is changed. 4. The PRML reproducing circuit according to claim 2, wherein the maximum likelihood decoded m-bit output is n-bit (m>
n), and a ECC circuit (18) that performs error detection and correction from the decoded n-bit output, and the control circuit (19) includes the +1 side slice level. A PRML reproducing circuit, characterized in that the distance is measured by the judgment output of the ECC circuit (18) when the -1 side slice level is changed and stored in the memory (20). 5. The PRML reproducing circuit according to claim 1, further comprising a memory (20) for holding respective distances at a plurality of predetermined cylinder positions of a plurality of heads (10), the control circuit (19). Sets the distance corresponding to the selected head (10) and the selected cylinder position in the maximum likelihood decoder (16). 6. The PRML reproducing circuit according to claim 1, wherein the control circuit (19) includes the waveform equalizing circuit (12 to 1).
A PRML reproducing circuit characterized by setting an adjustment value in 5). 7. The PRML reproducing circuit according to claim 6, wherein the waveform equalizing circuit (12 to 15) includes a gain control amplifier (12) for giving a gain to the read signal, and a gain control amplifier (12). An electric filter (13) for fixing and equalizing the output, and an analog-digital converter (14) for converting the output of the electric filter (13) into a digital value.
And a cosine equalizer (15) for equalizing the output of the analog-digital converter (14), wherein the control circuit (19) sets an offset value in the analog-digital converter (14). PRML playback circuit. 8. The PRML reproducing circuit according to claim 7, wherein the control circuit (19) measures an offset value of the analog-digital converter (14) from an output of the cosine equalizer (15).
RML playback circuit. 9. The PRML reproducing circuit according to claim 1, wherein the head (10) is composed of an MR head, and the control circuit (19) sets a drive current value in a drive circuit (11) of the MR head. PR characterized by
ML reproduction circuit. 10. The PRML reproduction circuit according to claim 9, wherein the waveform equalization circuit (12 to 15) includes a gain control amplifier (12) for giving a gain to the read signal, and a gain control amplifier (12). An electric filter (13) for fixing and equalizing the output, and an analog-digital converter (14) for converting the output of the electric filter (13) into a digital value.
And a cosine equalizer (15) for equalizing the output of the analog-digital converter (14), and the control circuit (19) outputs the drive current value of the MR head from the output of the cosine equalizer (15). A PRML reproducing circuit characterized by measuring. 11. The PRML reproducing circuit according to claim 6, wherein the waveform equalizing circuit (12 to 15) includes a gain control amplifier (12) for giving a gain to the read signal, and a gain control amplifier (12). An electric filter (13) for fixing and equalizing the output, and an analog-digital converter (14) for converting the output of the electric filter (13) into a digital value.
And a cosine equalizer (15) that equalizes the output of the analog-digital converter (14), and the control circuit (19) sets a filter adjustment value in the electric filter (13). PRML reproduction circuit. 12. The PRML reproducing circuit according to claim 11, wherein the control circuit (19) outputs the electric filter (1) from the output of the cosine equalizer (15).
A PRML reproducing circuit characterized by measuring the adjustment value of 3). 13. The PRML reproducing circuit according to claim 6, wherein the waveform equalizing circuit (12 to 15) includes a gain control amplifier (12) for giving a gain to the read signal, and a gain control amplifier (12). An electric filter (13) for fixing and equalizing the output, and an analog-digital converter (14) for converting the output of the electric filter (13) into a digital value.
And a cosine equalizer (15) for equalizing the output of the analog-digital converter (14), wherein the control circuit (19) sets an equalization coefficient in the cosine equalizer (15). PRM
L reproduction circuit. 14. The PRML reproducing circuit according to claim 13, wherein the control circuit (19) outputs the cosine equalizer (15) from the output of the cosine equalizer (15).
A PRML reproducing circuit characterized by measuring the equalization coefficient of