JPH07262564A - Information reproducing device - Google Patents

Abstract

PURPOSE:To set the slice level exactly following up the fluctuation in the amplitude of a reproduced signal by adjusting the slice level at which the reproduced signal is binarized by a comparator circuit in accordance with a relative positional relation between the transition range of the reproduced signal and the edge of a binarilization signal. CONSTITUTION:The reproduced signal by an optical head 2 is binarized by the slice level in the comparator circuit 5 through a binarization preprocessing circuit 4 of an information reproduction processing circuit 10. Simultaneously, the output of the circuit 4 is converted by a one-stage differentiating circuit 6 to a differential signal, which is then supplied to a comparator circuit 7. This comparator circuit forms an edge mask signal. The edge of the binarization signal is detected by an edge detecting circuit 8 and the slice level of the circuit 5 is adjusted in accordance with the relative positional relation between the transition range of the reproduced signal from a head 2 and the edge of the binary signal by a slice level control circuit 9. As a result, the slice level exactly following up the fluctuation ion the amplitude of the reproduced signal is set.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information reproducing apparatus for reproducing information recorded on a recording medium by a mark length recording system.

[0002]

2. Description of the Related Art For example, when reproducing information from a recording medium having a preamble portion in which a synchronization code is recorded, and an information portion in which information is recorded by the mark length recording method following the preamble portion, conventional information is reproduced. The reproducing apparatus performs a binarization preparation in which a DC voltage level having a certain reference value is used as a binarization slice level in a no-signal area, and obtains an average value of the reproduced signals of the sync code after the preamble portion appears. This is used as a slice level and binarized at the center of the reproduced signal amplitude. In the information section, in order to cope with various changes in the amplitude of the reproduction signal and the length of the mark depending on the modulation code, the charge width signal of the data PLL obtained in synchronization with the rising and falling edges of the binarized signal is used. By feedback, slice level control is performed to adjust the slice level deviated from the center of the reproduced signal amplitude. Such a technique is proposed in, for example, Japanese Patent Application No. 3-250668.

[0003]

By the way, the data PL
The L charge width signal is generated by the phase difference between the edge of the binarized signal and the edge of the self clock. If there is a burst error in the reproduced signal, the signal amplitude gradually decreases and disappears as shown in FIG. 5, and the signal remains for a while and a signal appears again, and the signal amplitude gradually increases and the original signal increases. Return to amplitude magnitude. In the no-signal state A2 shown in FIG. 5, the slice level becomes a DC voltage level having a constant reference value. However, after the state A3 in which the signal appears again, the slice level does not become the center b of the reproduced signal amplitude and the position a or c that is an integral multiple of the cycle of the self-clock.
At that point, the PLL is locked, and thereafter, the binarization of the reproduction signal may fail. Further, since it is necessary to use the data PLL circuit and the binarization circuit as a loop circuit, there is a concern that the jitter of the binarized signal may increase due to the delay of the slice level when the speed of the data signal increases. It is an object of the present invention to provide an information reproducing apparatus capable of setting a slice level that personally follows the amplitude fluctuation of a reproduced signal obtained from a recording medium.

[0004]

According to the present invention, an information detecting means for detecting information recorded on a recording medium and a reproduction signal obtained from the information detecting means at a slice level
The slice based on the binarizing means for binarizing, the relative positional relationship between the transition range of the reproduced signal obtained from the information detecting means and the edge of the binarized signal obtained from the binarizing means. There is provided an information reproducing apparatus characterized by comprising slice level control means for adjusting the level.

Further, according to the present invention, the slice level control means differentiates the reproduction signal obtained from the information detecting means, and the transition reference of the reproduction signal in the differentiation signal obtained from the differentiation means. A transition detecting means for detecting a point, an edge error detecting means for detecting an error between a transition reference point of the reproduction signal obtained from the transition detecting means and an edge of the binarized signal, and an edge error detecting means. An information reproducing apparatus is provided, which includes a determining unit that determines an adjustment amount of the slice level according to a change in an error signal that is generated.

Further, according to the present invention, the edge error detecting means is a rising edge detecting means for generating, in positive logic, a first detection signal having a pulse width corresponding to a period in which the differential signal falls below a first predetermined level. , A second pulse width corresponding to a period during which the differential signal rises above a second predetermined level.
Falling detecting means for generating a detection signal in the positive logic is included, the binarizing means includes signal generating means for generating the binarizing signal in positive logic and negative logic, and the determining means is of the positive logic. AND gate means for obtaining a logical product of the first detection signal and the positive logic binary signal as a rising error signal of the reproduction signal, the positive logic second detection signal, and the negative logic binary signal. NAND gate means for obtaining an inverted signal of the logical product of the above as a falling error signal of the reproduction signal, and a signal which changes from a reference level in accordance with the difference in pulse width between the rising error signal and the falling error signal is binarized. There is provided an information reproducing apparatus characterized by including feedback means for feeding back to the means.

[0007]

According to the present invention, the slice level serving as a reference when the reproduced signal obtained from the recording medium is binarized is obtained from the transition range of the reproduced signal obtained from the information detecting means and the binarizing means. It is adjusted based on the relative positional relationship with the edge of the binarized signal. Therefore, the slice level can accurately follow the amplitude fluctuation of the reproduction signal.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 schematically shows the configuration of an optical disc device as the information recording / reproducing device. This optical disc device
The optical disk 1 in which a donut-shaped metal coating layer is coated on the surface of a circular substrate made of, for example, glass or plastics material is used as a recording medium. Information is recorded on the optical disc 1 along tracks formed concentrically or spirally. This track is located in 256 sectors of "0 to 255" with the reference mark of "0". A plurality of blocks of fixed length on which information is recorded are prepared on the optical disc 1, and the number of sectors corresponding to each block differs depending on the position on the optical disc 1. Variable length information is recorded across multiple blocks. At the start position of each block, a block header (header information: preamble portion) including a fixed code such as a synchronization code, a block number, and a track number is recorded. The synchronization code has a fixed period longer than the bit period and shorter than the sector period, and is composed of a synchronization pattern of several bits. The block header described above is recorded in advance at the time of manufacture. Substantial information is recorded in the area (information section) following the block header. If each block does not end corresponding to the sector switching position, a block gap is provided and each block always starts from the position corresponding to the sector switching position. As a fixed code, the width of the pit and the length between the pits have a 1: 1 ratio (duty ratio 5
0%) is used. Alternatively, a ratio of 1 to n (n = 2, 3, ...) May be used.

As shown in FIG. 1, such an optical disc 1 is mounted on a spindle motor 12 when recording and reproducing information, and is rotated at a predetermined rotation speed by the spindle motor 12. On the lower surface side of the optical disc 1,
An optical head 2 is arranged to access the optical disc 1 in recording and reproducing information. The optical head 2 includes, for example, a semiconductor laser oscillator, a collimator lens, a beam splitter, an objective lens, an astigmatism optical system,
It is a well-known one composed of a photodetector, a lens actuator and the like. The optical head 2 is arranged so as to be movable in the radial direction of the optical disc 1 by a moving mechanism (not shown) composed of, for example, a linear motor. The optical head 2 is moved to a target track for recording or reproduction according to an instruction from a control circuit (not shown).

When the information is recorded on the optical disc 1 by the mark length recording method, the above-mentioned semiconductor laser oscillator generates laser light whose light intensity is modulated according to the information to be recorded, and reproduces the information from the optical disc 1. At this time, a laser beam having a constant light intensity is generated. The photodetector detects the laser beam reflected by the optical disc 1 and outputs an analog current according to its intensity. The optical head 2 supplies the current output from the photodetector to the information reproduction processing circuit 10 as a reproduction signal. The information reproduction processing circuit 10 is a circuit that generates a reproduction binarized signal according to a reproduction signal supplied from the optical head 2. The information reproduction processing circuit 10 includes an IV conversion circuit 3, a binarization preprocessing circuit 4, a first comparison circuit 5, a first-order differentiation circuit 6, a second comparison circuit 7, an edge detection circuit 8, and a slice level control circuit 9. It is composed by.

The IV conversion circuit 3 converts the current of the reproduction signal supplied from the optical head 2 into a voltage. The binarization preprocessing circuit 4 amplifies the reproduction signal of the analog voltage supplied from the IV conversion circuit 3 to a signal amplitude required for binarization. The first comparison circuit 5 performs binarization by comparing the reproduction signal supplied from the binarization preprocessing circuit 4 with the slice level control signal supplied from the slice level control circuit 9, and reproduces the result. It is output as a binary signal (that is, an information signal). The first-order differentiation circuit 6
The reproduction signal sent from the binarization preprocessing circuit 4 is converted into a differential signal. This differential signal temporarily changes from the intermediate level to a low level at the transition point where the reproduction signal rises, and temporarily changes to a level higher than the intermediate level at the transition point where the reproduction signal falls. The second comparison circuit 7 generates an edge mask signal from the differential signal generated by the first-order differentiation circuit 6. The edge detection circuit 8 detects a phase difference between the reproduced binarized signal (information signal) obtained by the first comparison circuit 5 and the edge mask signal obtained by the second comparison circuit 7 and detects an edge corresponding to this difference. Generate an error signal. The slice level control circuit 9 generates a slice level control signal from the edge error signal obtained by the edge detection circuit 8 and supplies this slice level control signal to the first comparison circuit 5.

FIG. 2 shows the configuration of the information reproduction processing circuit shown in FIG. 1 in more detail. The IV conversion circuit 1 is composed of an operational amplifier OP1 and a resistor R1, and outputs a reproduction signal having a voltage value determined by the current value of the reproduction signal from the optical head 2 and the resistance value of the resistor R1. The binarization preprocessing circuit 2 is composed of an operational amplifier OP2 and resistors R2 and R3, and amplifies the reproduction signal with an amplification degree determined by the resistors R2 and R3 to make a voltage amplitude suitable for binarization and differentiation. The first comparison circuit 5 binarizes the reproduced signal (analog signal) amplified by the binarization preprocessing circuit 4 and the slice level control signal output from the slice level control circuit 9 by voltage comparison. , And a comparator CMP1 that outputs the result as a reproduced binary signal in inverted and non-inverted form.

The first-order differentiating circuit 6 is composed of an operational amplifier OP3, a resistor R4, and a capacitor C1, and the differential characteristic is determined by the time constants of C1 and R4.
This time constant is determined by the frequency characteristic of the reproduced signal. The second comparison circuit 7 is supplied with the differential output signal of the first-order differentiating circuit 6 as the slice level SL2 and is supplied with the DC reference voltage Vre.
Comparing with f1, the comparator CMP2 which outputs the edge mask signal of the falling portion of the reproduction signal and the differential output signal of the first-order differentiation circuit 6 are compared with the DC reference voltage Vref3 supplied as the slice level SL3, Comparator CMP that outputs rising edge mask signal
3 and 3.

The edge detection circuit 8 includes a comparator CMP.
An AND gate circuit AND for generating a rising edge error signal from a rising edge mask signal of the non-inverted reproduction binary signal supplied by 1 and the reproduction signal supplied by the comparator CMP3, and an inverted reproduction binary value supplied by the comparator CMP1. Signal and comparator CMP2
The NAND gate circuit NAND generates a falling edge error signal from the falling edge mask signal of the reproduction signal supplied from the.

The slice level control circuit 9 is an operational amplifier O
P4, capacitor C2, resistor R5, reference voltage Vref3
(= 2.5V), and diodes D1 and D2. The edge error signal of the edge detection circuit 8 is input to the operational amplifier OP4 of the slice level control circuit 9 through the diodes D1 and D2. The edge error signals cancel each other at the rising and falling portions of the reproduced signal. Therefore, the resistor R5 and the capacitor C2
The output of the operational amplifier (OP4) after being smoothed by is the same as the reference voltage (Vref3) at 2.5V. This circuit smoothes and averages the edge error signal at the rising and falling portions of the reproduction signal and averages the reference voltage (Vre
The slice level based on f3) is output, and this slice level is output to the first comparison circuit 5.

Next, the slice level control performed by this optical disk device will be described. FIG. 3 shows a waveform obtained when the slice level is set at the center of the reproduced signal amplitude.

The reproduced signal from the optical head 2 is current-voltage converted by the IV conversion circuit 3 and has a waveform shown in FIG. The comparison circuit 5 compares the voltage level of the reproduction signal with the slice level SL1 set by the slice level control circuit 9, and outputs the proper binary signals 1 and 2 shown in (b) and (c) of FIG. Generate signal 2. The binarized signal 1 is a signal obtained from the non-inverted output end of the comparison circuit 5, and the binarized signal 2 is a signal obtained from the inverted output end of the comparison circuit 5.

The first-order differentiation circuit 6 generates a differentiation signal shown in FIG. 3D from the reproduction signal shown in FIG. 3A, and supplies this differentiation signal to the comparison circuit 7. In the comparison circuit 7, the comparator CMP2 outputs this differential signal to the slice level SL.
2 (f) by comparing with the voltage Vref1 of FIG.
The edge mask signal 2 shown in FIG.
P3 uses this differential signal as the voltage Vr of the slice level SL3.
The edge mask signal 1 shown in (e) of FIG. 3 is generated by comparing with ef2. The edge mask signal 1 is used to mask the rising edge portion of the binarized signal 1, and the edge mask signal 2 is used to mask the falling edge portion of the binarized signal 1. Therefore, the binarized signal 1 and the edge mask signal 1 are supplied to the AND gate circuit AND of the edge detection circuit 8, and the binarized signal 2 and the edge mask signal 2 are supplied to the NAND gate circuit NAND of the edge detection circuit 8. . The AND gate circuit AND outputs the edge error signal 1 shown in (g) of FIG. 3, and the NAND gate circuit NAND outputs the edge error signal 2 shown in (h) of FIG.

In the slice level control circuit 9, FIG.
The voltage at the point P shown in (2) becomes 2.5V which is equal to the reference voltage Vref3 of the operational amplifier OP4 due to the imaginary short circuit. Here, when the edge error signals 1 and 2 are combined via the diodes D1 and D2, respectively, a pulse that rises and falls around 2.5 V as shown in FIG. 3 (i) is in front of the input resistor R5 of the operational amplifier OP4. It is obtained as a slice level control signal at point i. The slice level control signal is smoothed by the resistor R5 and the capacitor C2 and supplied to the comparison circuit 5. When the slice level SL1 is set at the center of the signal amplitude capable of appropriately binarizing the reproduction signal shown in FIG. 3A, the pulse width of the edge error signal 1 and the pulse width of the edge error signal 2 are almost equal to each other. Same, slice level SL1
Does not change.

On the other hand, FIG. 4 shows a waveform obtained when the slice level is set so as to deviate from the center of the reproduction signal amplitude. The reproduced signal from the optical head 2 is current-voltage converted by the IV conversion circuit 3, and has a waveform similar to that of FIG. 3A as shown in FIG. The comparison circuit 5 compares the voltage level of the reproduction signal with the slice level SL1 set by the slice level control circuit 9 to generate the binarized signal 1 and the binarized signal 2 described with reference to FIG. This binarized signal 1 is shown in FIG. In this figure, SIG1 represents the binarized signal 1 obtained when the slice level SL1 is set at the center of the reproduction signal amplitude, and SIG2 is obtained when the slice level SL1 is set higher than the center of the reproduction signal amplitude. SIG3 is a binary signal 1 obtained when the slice level SL1 is set lower than the center of the reproduction signal amplitude.
Represents The binarized signal 2 (not shown) is the SIG1
It is generated as an inverted signal of -SIG3.

The first-order differential circuit 6 generates a differential signal similar to that shown in FIG. 3D from the reproduced signal shown in FIG. 4A, as shown in FIG. Supply to. In the comparison circuit 7, the comparator CMP2 compares the differential signal with the voltage Vref1 of the slice level SL2 to generate the edge mask signal 2 shown in (f) of FIG. 4, and the comparator CMP3 converts the differential signal of the slice level SL3. By comparing with the voltage Vref2, FIG.
The edge mask signal 1 shown in (e) is generated.

When the slice level SL1 is set lower than the center of the reproduction signal amplitude, the AND gate circuit AN
D outputs an edge error signal 1 having a pulse width wider than that shown in FIG. 3G, as shown in FIG. 4G, and the NAND gate circuit NAND has a pulse width larger than that shown in FIG. The edge error signal 2 having a narrow pulse width is output as shown in FIG. At this time, the slice level control circuit 9
Then, the slice level control signal shown in the upper part of (i) of FIG. 4 is obtained at point i before the input resistor R5. This slice level control signal is set to SCAv1 higher than 2.5V by being smoothed by the resistor R5 and the capacitor C2. As a result,
The slice level SL1 rises and stabilizes at the center of the reproduced signal signal amplitude.

When the slice level SL1 is set higher than the center of the reproduction signal amplitude, the AND gate circuit AND outputs the edge error signal 1 having a pulse width narrower than that shown in (g) of FIG. NAND gate circuit NAN
D outputs an edge error signal 2 having a pulse width wider than that shown in FIG. At this time, in the slice level control circuit 9, the slice level control signal shown in the lower part of (i) of FIG. 4 is obtained at point i before the input resistor R5. The slice level control signal is smoothed by the resistor R5 and the capacitor C2, and thus set to SCAv2 lower than 2.5V. As a result, the slice level SL1 drops and stabilizes at the center of the reproduced signal signal amplitude.

In the above-described embodiment, in the recording medium having the preamble part in which the synchronization code is recorded and the information part in which the information is recorded by the mark length recording method,
It is possible to accurately detect the width of the pit as the record information of the information section and the length between the pits, and to suppress the occurrence of large-scale propagation error due to erroneous reproduction triggered by burst error etc. it can.

[0025]

According to the present invention, there is provided an information reproducing apparatus capable of setting a slice level which accurately follows the amplitude fluctuation of the reproduced signal when the reproduced signal obtained from the recording medium is binarized. To be done.

[Brief description of drawings]

FIG. 1 is a block diagram schematically showing a configuration of an optical disc device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing the information reproduction processing circuit shown in FIG. 1 in more detail.

3 is a time chart showing waveforms of various signals generated in the information reproduction processing circuit shown in FIG. 2 when a slice level for binarizing a reproduction signal is appropriate.

4 is a time chart showing waveforms of various signals generated when the slice level for binarizing a reproduction signal is not appropriate in the information reproduction processing circuit shown in FIG.

FIG. 5 is a diagram for explaining a slice level that is erroneously set when a burst error occurs in a conventional information reproducing apparatus.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Optical disk, 2 ... Optical head, 3 ... IV conversion circuit, 4 ... Binarization preprocessing circuit, 5 ... 1st comparison circuit, 6 ... 1
Second-order differentiation circuit, 7 ... Second comparison circuit, 8 ... Edge detection circuit,
9 ... Slice level control circuit, 10 ... Information reproduction processing circuit.

Claims (3)

[Claims] 1. An information detecting means for detecting information recorded on a recording medium, a binarizing means for binarizing a reproduction signal obtained by the information detecting means at a slice level, and an information detecting means obtained by the detecting means. The transition range of the reproduced signal and the above 2
An information reproducing apparatus, comprising: a slice level control means for adjusting the slice level based on a relative positional relationship with an edge of a binarized signal obtained from the binarizing means. 2. The slice level control means, differentiating means for differentiating the reproduction signal obtained from the information detecting means, and transition detection for detecting a transition reference point of the reproduction signal in the differential signal obtained from the differentiating means. Means, edge error detecting means for detecting an error between the transition reference point of the reproduction signal obtained from the transition detecting means and the edge of the binarized signal, and a change in the error signal obtained from the edge error detecting means. The information reproducing apparatus according to claim 1, further comprising: a determining unit that determines the adjustment amount of the slice level according to the determination. 3. The rising edge detecting means for positively generating a first detection signal having a pulse width corresponding to a period in which the differential signal falls below a first predetermined level, the edge error detecting means, and the differential signal 2: Falling detection means for generating, with the positive logic, a second detection signal having a pulse width corresponding to a period of rising above a predetermined level, and the binarization means converts the binarized signal into positive logic and negative logic. And AND gate means for obtaining a logical product of the positive logic first detection signal and the positive logic binarized signal as a rising error signal of the reproduction signal. NAND gate means for obtaining an inverted signal of the logical product of the positive logic second detection signal and the negative logic binarization signal as the falling error signal of the reproduction signal, and the rising error signal. And an information reproducing apparatus according to claim 2, characterized in that it comprises a feedback means for feeding back a signal that varies from a reference level to the binarizing means in accordance with the difference between the pulse width falling error signal.