JP3056871B2 - Information playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information reproducing apparatus for reproducing information from an optical disk on which information is recorded by mark length recording.

[0002]

2. Description of the Related Art Recently, in an optical disk on which information is recorded by a mark length recording method, of a reproduced raw signal obtained from the optical disk, a preamble part and an information part have two parts.
There has been proposed a method in which a control circuit of a slice level for binarization is switched and a stable binarized signal is obtained by always following an accurate binarization determination point. As a result, the problem that the recorded information is not correctly reproduced can be avoided.

However, in this method, when there is no reproduced signal, there are independently provided circuits having the same function in each of the preamble part and the information part of the reproduced signal.
The charge width detection means at the rising and falling edges of the reproduced raw signal in the information section becomes large-scale and complicated overall,
There has been a problem that reliability is lowered.

[0004]

As described above, in the prior art, a circuit having the same function in each of the preamble section and the information section of a reproduced raw signal obtained from an optical disk exists independently. However, there is a problem that the charge width detecting means at the rising and falling edges of the reproduced raw signal is large-scale and complicated as a whole, causing a reduction in reliability. SUMMARY OF THE INVENTION It is an object of the present invention to provide a highly reliable information reproducing apparatus which shares a circuit and has a relatively small and simple configuration.

[0005]

An information reproducing apparatus according to the present invention comprises a detecting means for detecting information including a preamble part on a recording medium and an information part following the preamble part, and a detecting signal from the detecting means for a predetermined slice. Binarizing means for binarizing at a level, generating means for generating a channel clock signal, a charge width signal, and channel data for a bit period based on the binarized signal from the binarizing means; Demodulating means for demodulating the channel data of the above by using the channel clock signal, detecting means for detecting the preamble portion pre-recorded on the recording medium from the output signal of the demodulating means, and preamble portion by the detecting means. Is detected, a first control signal generator that generates the slice level control signal in accordance with the binarized signal from the binarizing means. Means for controlling the slice level in response to the binarization signal from the binarization means and the charge width signal from the generation means when the detection of the preamble section by the detection means is completed and the process proceeds to the information section. A second control signal generating means for generating a signal, and a slice of the binarizing means using a slice level control signal generated by the second control signal generating means or the first control signal generating means. And control means for controlling the level.

An information reproducing apparatus according to the present invention comprises a detecting means for detecting information including a preamble part and an information part following the preamble part on a recording medium, and a control means for controlling a slice level based on a predetermined reference value. A binarizing means for binarizing a detection signal from the detecting means at a slice level from the control means; a channel clock signal for a bit period by a binarizing signal from the binarizing means; Generating means for generating a width signal and channel data;
Demodulating means for demodulating channel data from the generating means using the channel clock signal, detecting means for detecting the preamble portion prerecorded on the recording medium from an output signal of the demodulating means, First control signal generating means for generating the slice level control signal in response to the binarized signal from the binarizing means when the preamble part is detected by the means, and detecting the preamble part by the detecting means Ends and moves to the information department,
Second control signal generating means for generating the slice level control signal in accordance with the binarized signal from the binarizing means and the charge width signal from the generating means, and the second control signal generating means Or correction means for correcting a slice level around a reference value of the control means using a slice level control signal generated by the first control signal generation means.

[0007]

According to a first aspect of the present invention, information including a preamble portion and an information portion following the preamble portion on a recording medium is detected, and the detection signal is binarized by a predetermined slice level by binarization means. A signal generates a channel clock signal, a charge width signal, and channel data for a bit period by a generating means, and the generated channel data is demodulated by a demodulating means using the channel clock signal. Detecting the preamble portion prerecorded on the medium, and when detecting the preamble portion, generates a slice-level control signal according to a binarization signal from the binarization means to generate a first control signal. Means, and when the detection of the preamble part by the detection means is completed and the processing proceeds to the information part, the binarization signal from the binarization means and the generation means The control signal of the slice level generated by the second control signal generating means in response to a charge width signal, the second control signal generating means or said first,
The slice level of the binarizing means is controlled using the slice level control signal generated by the control signal generating means.

According to a second aspect of the present invention, information including a preamble portion and an information portion following the preamble portion on a recording medium is detected, and a slice level is controlled by control means based on a predetermined reference value. , The above detection signal is binarized by binarizing means, and a channel clock signal, a charge width signal, and channel data for a bit period are generated by the generating means using the binarized signal. The demodulation means demodulates using the channel clock signal, detects the preamble portion pre-recorded on the recording medium from the output signal, and when the preamble portion is detected, outputs the signal from the binarization means. A slice level control signal is generated by the first control signal generation means in response to the binarized signal, and the detection of the preamble portion by the detection means is completed. When moving to the reporting section, the second control signal generating means generates the slice level control signal in accordance with the binarized signal from the binarizing means and the charge width signal from the generating means. The slice level is corrected around a reference value of the control means using a slice level control signal generated by the second control signal generation means or the first control signal generation means. .

[0009]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 schematically shows a configuration example of an embodiment of an optical disk device as an information reproducing device of the present invention.

An optical disc 1 as an information recording medium used in the optical disc apparatus shown in FIG. 1 has a doughnut-shaped metal coating layer such as tellurium or bismuth coated on a surface of a substrate formed in a circle of, for example, glass or plastics. Have been. A notch, that is, a reference mark is provided near the center of the metal coating layer.

On the optical disk 1, tracks for recording information are formed concentrically or spirally. The tracks are defined as "0" with a reference mark of "0".
２５255 ”into 256 sectors.

On the optical disc 1, a plurality of blocks of a fixed length for recording information are prepared. Each block has a different number of sectors depending on the position on the optical disc 1. Variable length information is recorded over a plurality of blocks.

At the start position of each block, a block header (header information: preamble portion) including a fixed code such as a synchronization code, a block number, a track number and the like is recorded. The synchronization code has a fixed period longer than the bit period and shorter than the sector period, and is composed of a synchronization pattern of several bits.

The above-mentioned block header is recorded in advance at the time of manufacture. Information is recorded in an area (information section) following the block header. If each block does not end in accordance with the sector switching position, a block gap is provided, and each block always starts from a position corresponding to the sector switching position.

As the fixed code, a code having a pit width and a length between pits of 1: 1 (duty ratio 50%) is used. In addition, a ratio of 1: n (n = 2, 3,...) May be used. Such an optical disc 1 is mounted on a spindle motor (not shown). The optical disc 1 is rotated at a predetermined rotation speed by the spindle motor.

As shown in FIG. 1, an optical head 2 is provided on the lower surface of the optical disk 1. The optical head 2 is used for recording information on the optical disk 1 or reproducing information from the optical disk 1.

The optical head 2 is a well-known one comprising a semiconductor laser oscillator (not shown), a collimator lens, a beam splitter, an objective lens, an astigmatism optical system, and a lens actuator.

The optical head 2 is disposed so as to be movable in the radial direction of the optical disk 1 by a moving mechanism (not shown) constituted by, for example, a linear motor or the like. The optical head 2 is moved to a target track to be recorded or reproduced according to an instruction from a control circuit (not shown).

The above-mentioned semiconductor laser oscillator is used for the optical disk 1
When the mark length information is recorded on the optical disc 1, a laser beam whose light intensity is modulated according to the information to be recorded is generated, and when the information is read from the optical disc 1 and reproduced, a laser beam having a constant light intensity is generated. I do. When reproducing information, the optical head 2
The signal output from the photodetector in is supplied to the information reproduction processing circuit 3.

The information reproduction processing circuit 3 is a circuit for outputting a reproduction information signal according to a detection signal supplied from the optical head 2. The information reproduction processing circuit 3, as shown in FIG.
A comparison circuit 4 as a binarization circuit, a data PLL circuit 5,
It comprises a demodulation circuit 6, a preamble detection circuit 7, a write area detection circuit 8, and a slice level control circuit 9.

The slice level control circuit 9 includes an edge portion charge width detection circuit 10, a preamble portion slice level detection circuit 11, and a smoothing circuit 12.

The comparison circuit 4 converts a current value as a detection signal supplied from the optical head 2 into a voltage value (analog signal), amplifies it, binarizes it with a slice level from the smoothing circuit 12, and binarizes it. The binarized signal is output to a data PLL circuit 5, a write area detection circuit 8, an edge charge width detection circuit 10, and a preamble slice level detection circuit 11, respectively.

The data PLL circuit 5 includes a resistor, a capacitor, and a voltage frequency converter (for example, a VCO). The channel clock signal is a binary clock signal from the comparison circuit 4, and the channel is phase-synchronized with the channel clock signal. Data is generated by extracting a charge width signal indicating the phase difference between the rising and falling of the binary signal and the channel clock signal.

The channel clock signal and channel data from data PLL circuit 5 are output to demodulation circuit 6,
The charge width signal is output to the edge portion charge width detection circuit 10.

The preamble detection circuit 7 detects a preamble part from the output signal of the demodulation circuit 6 and outputs a preamble detection signal to the preamble part slice level detection circuit 11.

The write area detection circuit 8 detects a write area of information including a preamble section and an information section based on the binarized signal from the comparison circuit 4 and outputs a write area signal. The write area signal is output to the edge part charge width detection circuit 10, preamble part slice level detection circuit 11, and smoothing circuit 12.

The slice level control circuit 9 includes a comparison circuit 4
The slice level is determined by the binarized signal from the controller, the charge width signal from the data PLL circuit 5, the preamble detection signal from the preamble detection circuit 7, and the write area signal from the write area detection circuit 8. The slice level is output to the comparison circuit 4.

The slice level control circuit 9 includes the edge portion charge width detection circuit 10, the preamble portion slice level detection circuit 11, and the smoothing circuit 12, as described above. FIG. 2 shows an example of this specific circuit.

The edge portion charge width detection circuit 10 includes an AND circuit 21, a NAND circuit 22, diodes D1 and D2,
And an inverter circuit 23. The AND circuit 21 and the NAND circuit 22 store data P
A charge width signal from the LL circuit 5 and a write area signal from the write area detection circuit 8 are supplied. The AND circuit 21 is supplied with a binary signal from the comparison circuit 4, and the NAND circuit 22 is supplied with the binary signal from the comparison circuit 4 inverted by an inverter circuit 23.

Thus, when the write area signal is supplied, the gates of the AND circuit 21 and the NAND circuit 22 are opened, and the AND circuit 21 and the NAND circuit 22 serve as gates of the charge width signal. The AND circuit 21 outputs a signal corresponding to the charge width of the rising edge of the binarized signal, and the NAND circuit 22 outputs a signal corresponding to the charge width of the falling edge of the binarized signal.

Preamble section slice level detection circuit 1
1 is an AND circuit 24, a NAND circuit 25, a diode D
3, D4 and an inverter circuit 26. A preamble detection signal from the preamble detection circuit 7 and a write area signal from the write area detection circuit 8 are supplied to the AND circuit 24 and the NAND circuit 25. The AND circuit 24 is supplied with a binary signal from the comparison circuit 4, and the NAND circuit 25 is supplied with the binary signal from the comparison circuit 4 inverted by an inverter circuit 26.

As a result, when the write area signal is supplied, the gates of the AND circuit 24 and the NAND circuit 25 are opened to serve as the gates of the preamble detection signal.
An average value of the binarized signal and the preamble detection signal is output by the AND circuit 24 and the NAND circuit 25 as a slice level control signal.

The smoothing circuit 12 includes resistors R1 and R2, a changeover switch 27, a DC power supply 28 as a fixed slice level source, a capacitor C, an operational amplifier 29, and a reference voltage source 30. The slice level control signal supplied from the edge portion charge width detection circuit 10 or the preamble portion slice level detection circuit 11 is smoothed by the resistor R1 or R2 and a capacitor and output to the inverting input terminal of the operational amplifier 29.

The voltage value (2.5 volts) from the reference voltage source 30 is supplied to the non-inverting input terminal of the operational amplifier 29. The operational amplifier 29 amplifies the smoothed slice level control signal and outputs a slice level based on the voltage value (2.5 volts) from the reference voltage source 30.

When the write area signal is supplied to the changeover switch 27, its contact is switched, and the slice level based on 2.5 VDC from the fixed slice level source 28 is connected to the edge portion charge width detection circuit 10 and The control signal is switched to the control signal of each slice level of the preamble section slice level detection circuit 11.

A raw reproduction signal is generated, the preamble detection signal from the preamble detection circuit 7 is input to the preamble section slice level detection circuit 11, and the slice level control signal generated by the preamble section slice level detection circuit 11 The current flows into the capacitor C through R2 and the changeover switch 27, is smoothed, and is output as a slice level by the operational amplifier 29.

During this time, the edge portion charge width detection circuit 10
Outputs a slice level control signal based on the charge width corresponding to the rising and falling edges of the reproduced raw signal of the preamble portion, but is ignored because the polarity is the same as the slice level control signal based on the preamble detection signal. .

When the reproduced raw signal shifts from the preamble section to the information section, the preamble detection signal from the preamble detection circuit 7 is no longer output, so that the preamble section slice level detection circuit 11 stops operating. Immediately, the edge portion charge width detection circuit 10 combines the charge width signals at the rising and falling edges of the reproduced raw signal and outputs a slice level control signal. The slice level control signal is supplied to the capacitor C through the resistor R1 and the changeover switch 27.
, And is smoothed and output as a slice level by the operational amplifier 29.

FIG. 3 shows a binarized signal and a slice level in the preamble part and the information part when a reproduced raw signal is present. 3A shows the preamble part, the information part and the slice level of the reproduced raw signal, FIG. 3B shows the binarized signal, and FIG. 3C shows the slice detected in the preamble part and the information part, respectively. FIG. 3D shows a level control signal, and FIG. 3D shows a smoothed slice level control signal.

FIG. 4 shows the principle of setting a binarized slice in the preamble portion. FIG. 4A shows a reproduced raw signal of the preamble portion and a slice level v _S at an accurate position.
If shows a slice level when the shifted upward v _H or lower v _L, than the exact position.

FIG. 4B shows a binarized signal when sliced at an accurate position, FIG. 4C shows a preamble detection signal, and FIG. 4D shows a preamble section slice at this time. This is a slice level control signal before smoothing detected by the level detection circuit 11.

FIG. 4E shows a binarized signal when sliced at the position of v _H in FIG. 4A, and FIG.
Is a slice level control signal before smoothing at this time.

FIG. 4G shows a binary signal when sliced at the position of v _L in FIG. 4A, and FIG.
Is a slice level control signal before smoothing at this time.

FIG. 5 shows the principle of setting a binary slice in the information section. FIG. 5 (a) shows the reproduced raw signal of the information section, the slice level v _S at the correct position, and v above the correct position. _H indicates the slice level at the time of shifting to v _L or lower v _L.

FIG. 5B shows a binarized signal when sliced at the position of v _S in FIG. 5A, and FIG.
5 is the channel clock signal of the data PLL circuit 5, FIG. 5D is the charge width signal extracted from the data PLL circuit 5, and FIG. 5E is only the rising edge of the binary signal of the charge width signal. Extracted charge width signal, FIG.
(F) is a charge width signal obtained by extracting and inverting only the falling edge of the binarized signal from the charge width signal, and (g) of FIG. Is a slice level control signal produced by synthesizing the inverted charge width signals.
FIG. 5 (h) is a binarized signal when sliced at the position of v _{H in} FIG. 5 (a), and FIG. 5 (i) is a slice level control signal before smoothing at this time. is there. FIG. 5 (i) is a binarized signal when sliced at the position of v _{L in} FIG. 5 (a), and FIG. 5 (k) is a slice level control signal before smoothing at this time. is there. Next, the operation in such a configuration will be described.

The optical head 2 reads from the optical disk 1,
When the raw reproduction signal is input to the comparison circuit 4, a binary signal is generated. The write area detection circuit 8 immediately converts the write area signal to the edge charge width detection circuit 10 and the preamble slice level detection circuit 1 upon detecting the binarized signal.
1 and output to the changeover switch 27 in the smoothing circuit 12. Data PLL circuit 5 outputs a channel clock signal, channel data, and a charge width signal from the input binary signal. The channel clock signal and the channel data are output to the demodulation circuit 6, and the charge width signal is output to the edge portion charge width detection circuit 10. Further, the preamble detection circuit 7 detects a preamble part from the output signal of the demodulation circuit 6 and outputs a preamble detection signal to the preamble part slice level detection circuit 11.

In FIG. 2, the write area signal includes an AND circuit 21 and a NAND circuit 22 of the edge portion charge width detection circuit 10 and a preamble portion slice level detection circuit 11.
And an AND circuit 24 and a NAND circuit 25. The write area signal is also input to the changeover switch 27, and from the slice level of the fixed slice level source 28 at DC 2.5 volts, each of the edge charge width detection circuit 10 and the preamble slice level detection circuit 11 Switch to slice level by control signal output.

When the preamble portion is binarized at the position of v _{S in} FIG. 4A with a reproduced raw signal which becomes active when the write area signal is detected by the write area detection circuit 8, FIG. ), And the binary signal is inverted by an AND circuit 24 and an inverter 26 and input to a NAND circuit 25. FIG. 4C shows a preamble detection signal in which the preamble detection circuit 7 detects a preamble portion. This preamble detection signal is input to the AND circuit 24 and the NAND circuit 25. The outputs of the AND circuit 24 and the NAND circuit 25 are diodes D3 and D4.
And the preamble section slice level detection circuit 1
4 is a slice level control signal shown in FIG.

When binarized at the position of v _S , the control signal of this slice level is smoothed by the resistor R2 and the capacitor C, and the average value of the binarized signal becomes 2.5 volts. At the connection point A, the voltage becomes 2.5 volts, and an imaginary short circuit occurs with the non-inverting input of the operational amplifier 29.

The output of the smoothing circuit 12 becomes 2.5 volts as an average value of the binarized signal and is input to the comparison circuit 4. Therefore, there is no change in the slice level, and the slice level is maintained at the current position.

As described above, when the preamble portion of the reproduced raw signal is binarized at the position of v _{H in} FIG.
4 (e), and the output of the preamble section slice level detection circuit 11 becomes a slice level control signal indicated by a solid line in FIG. 4 (f). In the smoothing circuit 12, the slice level control signal is smoothed by the resistor R2 and the capacitor C, and is input to the comparison circuit 4 as a value lower than 2.5 volts as shown by a dotted line. Therefore, the slice level moves downward (slice level v _H is reduced).

As described above, when the preamble portion of the reproduced raw signal is binarized at the position of v _{L in} FIG.
4 (g), and the output of the preamble section slice level detection circuit 12 becomes a slice level control signal indicated by a solid line in FIG. 4 (h). In the smoothing circuit 12, the slice level control signal is smoothed by the resistor R2 and the capacitor C, and becomes a value higher than 2.5 volts as shown by a dotted line and is input to the comparison circuit 4. Therefore, the slice level moves upward (slice level v _L is raised).

When the information portion of the reproduced raw signal is binarized, the preamble detection signal from the preamble detection circuit 7 is not output, so that the preamble slice level detection circuit 11 does not operate.

When the binarization is performed at the position of v _{S in} FIG. 5A in the information section of the reproduced raw signal, the binarized signal becomes as shown in FIG. 5B, and the data PLL at this time is obtained. Circuit 5
5 (c), and the charge width signal is as shown in FIG. 5 (d).

In the edge portion charge width detection circuit 10, an inverted signal and a non-inversion signal of the binarized signal are gated, and the output of the AND circuit 21 in the edge portion charge width detection circuit 10 is shown in FIG. The charge width signal at the rising edge is output from the NAND circuit 22 as shown in FIG.
At the falling edge of the signal.

The charge width of the rising edge from AND circuit 21 and the charge width of the falling edge from NAND circuit 22 are combined by diodes D1 and D2.
This synthesized signal becomes a slice level control signal as shown in FIG. 5G as an output of the edge portion charge width detection circuit 10.

When binarization is performed at the position of v _S, the slice level control signal is smoothed by the resistor R2 and the capacitor C, and the average value of the binarized signal becomes 2.5 volts. At the connection point A, the voltage becomes 2.5 volts, and an imaginary short circuit occurs with the non-inverting input of the operational amplifier 29.

The output of the smoothing circuit 12 becomes 2.5 volts as an average value of the binarized signal and is input to the comparison circuit 4. Therefore, there is no change in the slice level, and the slice level is maintained at the current position.

As described above, when the information portion of the reproduced raw signal is binarized at the position of v _H in FIG.
A binary signal as shown in (h) is obtained. The charge width signal at this time is such that the charge width at the rising edge is narrow, the charge width at the rising edge is wide, and the diodes D1 and D2
Thus, the output of the edge portion charge width detection circuit 10 becomes a slice level control signal as shown by the solid line in FIG.

In the smoothing circuit 12, the slice level control signal shown in FIG.
And a value lower than 2.5 volts is input to the comparison circuit 4 as shown by the dotted line. Therefore, the slice level moves downward (slice level v _H is reduced).

As described above, when the information portion of the reproduced raw signal is binarized at the position of v _L in FIG.
A binary signal as shown in (j) is obtained. At this time, the charge width signal has a wide charge width at the rising edge portion and a small charge width at the falling edge portion.
2 and becomes a slice level control signal as shown by a solid line in FIG. 5 (k) as an output of the edge portion charge width detection circuit 10.

In the smoothing circuit 12, the slice level control signal shown in FIG.
And a value higher than 2.5 volts is input to the comparison circuit 4 as shown by the dotted line. Therefore, the slice level moves upward (slice level v _L is raised).

By repeating the above operation, the slice level is controlled so as to always maintain the optimum value. When the signal area changes to the no-signal area and the write area signal is no longer output, the changeover switch 27 is switched, and the slice level becomes DC 2.5 volt which is the voltage of the fixed slice level 28, and the reproduced raw signal is input. Wait for it to be done.

As described above, according to the above embodiment,
The reference value of the binarized slice level control signal is DC 2.5
By using volts, a slice level control circuit according to the type of the reproduction signal can be easily configured by a logic circuit, and a smoothing circuit and the like can be shared, so that a simple and highly reliable circuit can be provided.

In the above embodiment, the case where the recording medium is an optical disk has been described. However, the present invention is not limited to this, and the present invention can be similarly applied to a recording medium such as a magnetic disk and a magneto-optical disk.

[0066]

As described in detail above, according to the present invention,
Circuits can be shared, and a highly reliable information reproducing apparatus can be provided with a relatively small and simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing the configuration of an optical disk device according to the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a slice level control circuit of FIG. 1;

FIG. 3 is a view showing signal waveforms of main parts of the slice level control circuit of FIG. 1;

FIG. 4 is a diagram showing signal waveforms in a preamble section.

FIG. 5 is a diagram showing signal waveforms in an information section.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Optical disk (recording medium), 2 ... Optical head, 3 ... Information reproduction processing circuit, 4 ... Comparison circuit, 5 ... Data PLL circuit, 6 ... Demodulation circuit, 7 ... Preamble detection circuit, 8 ... Write area detection circuit, 9 ... Slice level control circuit, 1
0: edge portion charge width detection circuit, 11: preamble portion slice level detection circuit, 12: smoothing circuit.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Mitsuki Tagami 70 Yanagicho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Yanagicho Plant (56) References JP-A-63-285774 (JP, A) JP-A-4 −341928 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11B 20/10 321 G11B 7/00

Claims (2)

(57) [Claims] A detecting means for detecting information including a preamble part and an information part following the preamble part on a recording medium; a binarizing means for binarizing a detection signal from the detecting means at a predetermined slice level; Generating means for generating a channel clock signal, a charge width signal, and channel data for a bit period based on the binarized signal from the binarizing means; and demodulating the channel data from the generating means using the channel clock signal. Demodulating means for detecting the preamble portion pre-recorded on the recording medium from the output signal of the demodulating means; and when the preamble portion is detected by the detecting means, First control signal generating means for generating the slice level control signal in accordance with the binarized signal, and a preamble by the detecting means. When the detection of the control unit is completed and the process proceeds to the information unit, the second slice level control signal is generated according to the binarization signal from the binarization unit and the charge width signal from the generation unit. Control signal generation means; and control means for controlling the slice level of the binarization means using the second control signal generation means or the slice level control signal generated by the first control signal generation means. An information reproducing apparatus, comprising: 2. A detecting means for detecting information including a preamble part and an information part following the preamble part on a recording medium; a controlling means for controlling a slice level based on a predetermined reference value; Binarizing means for binarizing a detection signal from the detecting means at a slice level of: a channel clock signal, a charge width signal, and channel data for a bit period by the binarizing signal from the binarizing means. Generating means for generating; demodulating means for demodulating channel data from the generating means using the channel clock signal; detecting the preamble portion pre-recorded on the recording medium from an output signal of the demodulating means. Detecting means for detecting a preamble portion by the detecting means, the slice level according to a binarized signal from the binarizing means; A first control signal generating means for generating a control signal of the digital signal, and when the detection of the preamble section by the detecting means is completed and the processing proceeds to the information section, the binary signal from the binarizing means and the generating means A second control signal generating means for generating the control signal of the slice level in response to the charge width signal, and a slice level generated by the second control signal generating means or the first control signal generating means. An information reproducing apparatus, comprising: a correction unit that corrects a slice level around a reference value of the control unit using the control signal.