JPH07260901A - Input characteristic measurement time detection method for semiconductor ic device and detection device for the time - Google Patents

Abstract

PURPOSE:To automatically provide a time suitable for measuring input characteristics. CONSTITUTION:A logic simulator section 4 enters each of data 6 to 8, and changes the level of a signal sent to the input terminal of each logic gate, on the basis of a test signal. Furthermore, an input characteristic measurement time detection section 3 makes judgement as to whether the level of the input terminal of the logic gate agrees to other input terminal logics stored in logic library data 7, when the data 6 to 8 are inputted and the level of the test signal changes. When agreement is found, the time of the test signal inputted to an external input pin is used as a time for measuring input characteristics, and an input equivalent base number for the external input pin at that time is stored.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting the input characteristic measuring time of a semiconductor integrated circuit device and its input characteristic measuring time detecting device, and more particularly, to input a test signal to the semiconductor integrated circuit device by using a tester. The present invention relates to an input characteristic measurement time detection method and an input characteristic measurement time detection apparatus for preliminarily determining the measurement time at which the input characteristic of the semiconductor integrated circuit device is measured when inspecting the semiconductor integrated circuit device. Is.

In recent years, with the increase in complexity and density of semiconductor integrated circuit devices, the inspection by a tester before shipping products has become complicated and takes a long time. Therefore, the inspection by the tester can be performed with high accuracy and in a short time. Is desired. Therefore, it is necessary to obtain the measurement time at which time of the test signal used in the inspection should be measured for the inspection. Then, the measurement time needs to be obtained in advance in a more efficient and short time and with high accuracy.

[0003]

2. Description of the Related Art Conventionally, as an LSI test method, signal data in which a change in the level of a signal to be input to an external input pin is preset with respect to predesigned circuit data is created. Then, based on the circuit data and the signal data, and a logic library in which various characteristics (logic of the output with respect to the input, delay time, etc.) of the logic elements forming the circuit data are stored, the output signal with respect to the input signal of each logic element. There is a logic simulator for simulating the change of the above and judging the defect of the LSI at the circuit level.

In addition, the LSI is actually connected to a test apparatus, a signal based on preset signal data is input to its input terminal to operate the LSI, and various items are identified by a signal appearing at its output terminal. The inspection is performed, and the defect of the LSI is judged based on the inspection result.

For measuring the characteristics of the LSI in this test apparatus, for example, a signal is input to the LSI based on signal data, a certain operating state is set, the change of the input signal is temporarily stopped, and the LSI is flown to the LSI when the change is stopped. Some measure current (leakage current).

Similarly, based on the signal data, the LSI
A signal is input to, the attention is paid to one external input pin, and the external input pin is disconnected from the signal source. Then, a variable power supply and an ammeter are connected to the separated external input pin, the voltage of the variable power supply is changed, the current flowing through the focused external input pin is measured, and the input characteristic of the external input pin is measured. is there. FIG. 9 shows a schematic configuration of a test device for measuring the input characteristic.

The semiconductor device 50 inserted into the test device is provided with power input pins 51 and 52.
1 is connected to the high potential side power supply Vcc, and the power supply input pin 52 is connected to the ground GND. In addition, the semiconductor device 5
0 has a plurality of external input pins 53 and a plurality of external output pins 54. The signal lines 55 are connected to the external input pins 53, respectively, and the preset signal data 5
A test signal is input based on the test signal No. 6, and the semiconductor device 50 is tested before shipment.

When measuring the input characteristics of the semiconductor device 50, the signal line 55 is disconnected from the external input pin 53 during the test before shipment, and is connected in series between the separated external input pin 53 and the ground GND. The variable power source 57 and the ammeter 58 are connected. At this time, the external output pin 54
Is disconnected from the test equipment. And the variable power source 5
The output voltage of 7 is varied, the current flowing through the external input pin 53 at that time is measured by the ammeter 58, and it is determined whether the semiconductor device 50 is normal or not depending on whether the current value is within a predetermined range. It is like this.

[0009]

By the way, the measurement time of the above-mentioned input characteristic is the condition of the signal inputted to the external input pin 53 and the signal inputted to the other external input pin 53, which is the object of measurement. The method of measuring the characteristics of the semiconductor device 50 at the measurement time has been adopted.
Then, the designer has previously decided this input characteristic measurement time.

However, as the integration of semiconductor devices progresses, the number of external input pins 53 increases, and the amount of signal data 56 applied to the increased external input pins 53 becomes enormous and complicated. As a result, the signal data 56
However, it takes a lot of time to accurately and surely set the time suitable for the measurement of the input characteristic, and there is a problem that the test before shipping the product becomes longer.

The present invention has been made to solve the above problems, and an object thereof is to measure an input characteristic of a semiconductor integrated circuit device capable of automatically obtaining a time suitable for measuring an input characteristic. It is an object to provide a detection method and an input characteristic measurement time detection device thereof.

[0012]

In order to solve the above problems, the present invention provides circuit data 6 in which externally designed external input pins, logic gates, and their connection information are stored.
Corresponding to another input logic in which the level of the other input terminal is preset for each input terminal of the logic gate of the circuit data 6 and each logic gate is equivalently expressed by a plurality of transistors and flows to the base of the transistor. The logic library data 7 in which the set input equivalent base number is stored, the test signal input to the external input pin to check the logic of the circuit data 6, and the time at which the input characteristic of the external input pin is measured. Is a preset measurement time setting, and the input equivalent base number of the logic gate connected to the external input pin when measuring the input characteristic of the external input pin with respect to the external input pin is a preset expected value. And the respective data 6 to 8 are input, and the level of the signal input to the input terminal of each logic gate is changed based on the test signal. The logic simulator unit 4 for inputting the data 6 to 8 and whether the level of the input terminal of the logic gate when the level of the test signal changes matches the other input logic stored in the logic library data 7 If it matches, the time of the test signal input to the external input pin at that time is used as the time to measure the input characteristics, and the input equivalent base number for the external input pin at that time is stored. The gist is that the measurement time detection unit 3 is provided.

[0013]

Therefore, according to the present invention, the logic simulator section 4 inputs each data 6 to 8 and changes the level of the signal input to the input terminal of each logic gate based on the test signal. The input characteristic measurement time detection unit 3 uses each data 6 to
8 is input, and the level of the input terminal of the logic gate when the level of the test signal changes is the logic library data 7
It is determined whether or not it matches the other input logic stored in.
When they match, the time of the test signal input to the external input pin at that time is set as the time at which the input characteristic is measured, and the input equivalent base number for the external input pin at that time is stored.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment embodying the present invention will now be described with reference to FIGS.
This will be described with reference to FIG. For convenience of explanation, the same components as those shown in FIG. 9 are designated by the same reference numerals, and the description thereof is partially omitted.

FIG. 1 is a schematic diagram showing the configuration of an input characteristic measurement time detection device. The input characteristic measurement time detection device (hereinafter, simply referred to as a detection device) 1 includes a data storage unit 2, an input characteristic measurement time detection unit (hereinafter, simply referred to as a detection unit) 3, a logic simulator unit 4, and a detection result storage unit 5. It is configured.

The data storage unit 2 stores preset circuit data 6, logic library data 7 and signal data 8. The circuit data 6 stores logic gates logically designed based on the specifications of the semiconductor device and connection information indicating connections between the logic gates and between the logic gates and external input / output pins of the semiconductor device.

The logic library data 7 stores various characteristics such as the logic of the output level with respect to the input level of each logic gate and the delay time of the change of the output level with respect to the change of the input level.

The logic library data 7 also stores other input logic in which the levels of the other input terminals for the respective input terminals of the respective logic gates are preset. In the other input logic, the level at which the input characteristic is measured for an input terminal other than the input terminal is set in the logic gate whose input terminal is connected to the external input pin 53 focused on for measuring the input characteristic. ing. And the other input logic is
It is set for all the logic gates connected to the external input pin 53 focused on for measuring the input characteristic.

Further, the logic library data 7 stores the input equivalent base number of each logic gate. The input equivalent base number is a coefficient for finding the value of the current flowing through the input terminal of the logic gate.If the logic gate is equivalently expressed by multiple transistors, the number of bases of the transistors connected to the input terminal is calculated. It is a value expressed as a multiple of the unit current. The number of input equivalent bases is preset corresponding to the level of each input terminal of the logic gate. That is, as shown in FIG. 8A, when an H level signal is input to the input terminal of the logic gate (AND circuit) 21, the number of transistors connected to the external input pin 53 of the semiconductor device 50 is also increased. Then, the input equivalent base number N1 becomes N1 = 10. On the other hand, as shown in FIG. 8B, when an L level signal is input to the other input terminal, the input equivalent base number N1 of the AND circuit 21 is N1.
= 2. The input equivalent base number is set for each level of the input terminal of each logic gate.

A test signal input to each external input pin 53 of the semiconductor device 50 is set in the signal data 8. An example of the test signal is shown in FIG. Test signal L
1 to L3 are external input pins 53 of the semiconductor device 50 of FIG.
The signals are respectively input to the semiconductor device 50 and are set to a level at which the operation of the semiconductor device 50 can be confirmed.
Then, the test signals L1 to L3 are input to the logic simulator unit 4, and the signals are propagated to the respective logic gates of the circuit data 6 based on the levels of the test signals L1 to L3. The test signals L1 to L3 are started at the test time T _0, and the time at which the level of at least one test signal among the test signals L1 to L3 changes from the test time T ₀ is the next test time T ₁ It is set in order from. Then, the time when the logic simulator unit 4 finishes the simulation is set as the end time T _E.

The signal data 8 can be preset with a measurement time setting for measuring the input characteristic of each external input pin 53. The set measurement time can specify any test time from the test time T ₀ when the logic simulator section 4 starts the simulation to the end time T _E when the simulation ends. For the measurement time setting, different test times can be set for the respective external input pins 53 of the semiconductor device 50. Further, in the measurement time setting, the test time can be set only for an arbitrary external input pin among the external input pins 53 of the semiconductor device 50.

Further, the signal data 8 stores an expected value. For the expected value, the input equivalent base number for the level of the other input terminal when measuring the input characteristic is set for the external input pin 53 focused on for measuring the input characteristic. That is, a value is set when the level of the other input terminal of the logic gate is a level suitable for measurement at the time when the level changes. Then, at the measurement time when the input characteristic is measured by the logic simulation, the expected value is compared with the input equivalent base number at the measurement time.

When the input equivalent base number at the measurement time is smaller than the expected value, it can be determined that the other input terminal of the logic gate is not suitable for measuring the input characteristic of the external input pin 53. On the other hand, when the input equivalent base number at the measurement time is equal to or larger than the expected value, it can be determined that the other input terminal in the logic gate is suitable for measuring the input characteristic of the external input pin 53. It has become.

The detection unit 3 inputs the respective data 6 to 8 stored in the data storage unit 2. Then, the detection unit 3 detects the time suitable for the input measurement of the external input pin 53 of the semiconductor device 50 based on the input data 6 to 8. That is, the detection unit 3 inputs the circuit data 6 and develops the circuit data 6 into data that can be simulated by the logic simulator unit 4. Further, the detection unit 3 inputs the logic library data 7 and the signal data 8. Detection unit 3
In the logic simulator unit 4, the test signal stored in the signal data 8 is propagated to each external input / output pin of the circuit data 6 and each logic gate based on the truth value stored in the logic library data 7. Then, at each test time T of the test signal, the detection unit 3 performs a time determination process to detect whether the test time T is suitable for measuring the input characteristic of the external input pin 53.

That is, when the measurement time is not stored in the signal data 8 in advance, the detector 3 is connected to the external input pin 53 of interest at the test time T (eg, test time T _{3 in} FIG. 4). Perform X propagation to the logic gate. In this X propagation, in the logic gate connected to the external input pin 53 of interest, the output signal changes in response to the input signal, and the output signal passes through the other logic gate as shown in FIG. It may come back to the other input terminal of the gate.

For example, as shown in FIG. 7, the external input pin 53 is connected to the input terminals of the AND circuit 21 and the OR circuit 22. An L level signal is input to the other input terminals of the AND circuit 21 and the OR circuit 22, and the external input pin 53
The level is suitable for measuring the input characteristics of.
The output terminal of the OR circuit 22 is connected to the input terminal of the NAND circuit 23, and the output terminal of the NAND circuit 23 is connected to the input terminal of the OR circuit 22 via another logic gate (shown by the dotted line in FIG. 7). .

Now, the signal input to the external input pin 53 is set to L
When the level is changed to the X level, the level of the output terminal of the OR circuit 22 changes from the L level to the X level based on the change of the level, and the change of the level is input to the input terminal of the NAND circuit 23. Then, NAND circuit 23
The level of the output terminal of is changed from H level to X level. Then, the change in the level is propagated to the input terminal of the OR circuit 22 through another logic gate, the level of the input terminal changes from the L level to the X level, and the input characteristic of the external input pin 53 is measured. The level is not suitable for.

As a result, at this test time T ₃ ,
Since the level of the input terminal of the logic gate changes from the L level, even if the input characteristic of the focused external input pin 53 is measured, the measurement result will not be accurate.
Therefore, it is necessary to obtain a test time at which the level of the input terminal does not change with respect to the returned signal.

The X propagation is performed by the logic simulator unit 4
In (2), an X level signal is input to the focused external input pin 53, and it is checked that the level of the other input terminal of the logic gate connected to the external input pin 53 does not change. Here, the X level signal has a potential of the L level signal (ground GND: 0 volt).
Higher and H-level signal potential (high-potential-side power supply Vcc)
This signal has a lower potential. FIG. 6A shows an example of the truth table of the AND circuit including the X level signal, and FIG. 6B shows an example of the truth table of the OR circuit including the X level signal.

Next, the detecting section 3 calculates the input equivalent base number of the logic gate of the logic gate resulting from the X propagation at the test time T ₃ . And the detection unit 3
Checks the other input, and for the other input terminal of the input terminal connected to the external input pin 53 focused on the logic gate, the level of the input terminal is compared with the other input logic stored in the logic library data 7. Judge whether or not they match. If another input logic match, detecting unit 3 is configured to store the test time T ₃ at this time and measurement time, the detection result storing unit 5 together with the input equivalent based number previously calculated. On the other hand, when the other input logics do not match, the detection unit 3 compares the previously calculated input equivalent base number with the stored input equivalent base number. When the calculated input equivalent base number is larger, the detection unit 3 sets the test time T _{3 at} that time as the measurement time, and the detection result storage unit for the external input pin 53 together with the calculated input equivalent base number. The data of 5 is updated.

When the measurement time is designated, the detection unit 3
Only when the test time T matches the designated time, the X propagation, the other input check, and the input equivalent base number are calculated in the same manner as described above, and the measurement time or error is sent to the detection result storage unit 5 based on the respective results. It is supposed to be stored.

The logic simulator section 4 inputs the expanded data obtained by expanding the circuit data 6 into data that can be logically simulated. Then, the logic simulator unit 4 propagates the level from the external input pin 53 to each logic gate based on the truth value of the logic gate stored in the logic library data 7 based on the input signal data 8. Then, the level between the logic gates is changed. Then, it is possible to confirm whether the change in the level is changing so as to satisfy the specifications of the semiconductor device. This confirmation is possible by displaying a change in the level at that time on a display (not shown) every time the level of the signal input to the external input pin 53 changes. At this time, it is possible to display only the input or output terminals of a plurality of logic gates of interest set in advance,
The logic of a semiconductor device can be verified more efficiently. In addition, a change in the level of the input / output terminal of each logic gate at each time when the simulation is executed for all the signal sequences stored in the signal data 8 is stored and displayed on the display after the simulation is completed.
It is possible to confirm by printing the simulation result.

The detection result storage unit 5 stores a time suitable for measuring the input characteristic of each external input pin 53 detected by the detection unit 3. Further, when the measurement time for measuring the input characteristic is not set in the detection result storage unit 5, the time when the number of input equivalent bases becomes the largest for the external input pin 53 is the measurement time detected. It is supposed to be stored as.

Further, in the detection result storage unit 5, when the time suitable for measuring the input characteristic cannot be detected, that is, when the measurement time is set in the signal data 8, the logical library data 7 is stored. When the set levels of other inputs do not match, the external input pin 53 is stored as a detection error.

Next, the detection device 1 configured as described above.
The operation will be described according to the processing flows of FIGS.
The detection unit 3 of the detection device 1 reads the circuit data 6 in step (hereinafter, simply referred to as S) 1 (circuit data expansion means). Then, the detection unit 3 expands the read circuit data 6 into data that can be simulated by the logic simulator unit 4. Further, the detection unit 3 includes the semiconductor device 50.
Each external input pin 53 is stored as an unmeasured pin group.
Then, the detection unit 3 moves from S1 to S2.

Next, S2 is a logic simulator means, and the detection unit 3 reads the logic library data 7 and the signal data 8 and performs a logic simulation based on the signal data 6 developed by the logic simulator unit 4. To do. At this time, the logic simulator unit 4 simulates the circuit data 6 at each test time T of the signal data 8. That is, when the simulation is started, the logic simulator section 4 receives the test signal L at the test time T ₀ .
The levels 1 to L3 are input to each external input pin 53. Then, the logic simulator unit 4 propagates the level input to each external input pin 53 based on the truth value of the logic gate stored in the logic library data 7 via the logic gate of the circuit data 6. Then, when the levels of the input and output terminals of each logic gate are determined, the simulation at the test time T ₀ ends.

When the simulation of the logic simulator section 4 is completed, the detecting section 3 moves to S3. Then, S3 is a signal storage means, and the detection unit 3 stores the signal level of each part of the circuit data 6 at the simulated test time T ₀ . Then, the detection unit 3 moves from S3 to S4.

S4 is a target pin focusing means, and the detecting unit 3 focuses on one external input pin 53 of the external input pins 53 of the unmeasured pin group stored in S4,
The external input pin 53 is the target pin for determining the measurement time. Then, the detection unit 3 determines the input characteristic of the external input pin 53 at the present time with respect to the input characteristic measurement time determination unit (hereinafter, simply referred to as time determination unit) in S5, that is, the external input pin 53 which is the target pin in S4. Time determination processing is performed to determine whether the time is suitable for measurement.
The time determination process in S5 is performed according to the flowchart shown in FIG.

That is, S21 is a measuring time setting judging means, which judges whether or not the measuring time for measuring the input characteristic with respect to the target pin is preset. First, the case where the measurement time is not set will be described. When the measurement time is not preset for the target pin, the detection unit 3
Moves to S22.

S22 is an X propagation means, and the detection unit 3 causes the logic simulator unit 4 to carry out X propagation. And
S23 is an input equivalent base number calculation means, which is the detection unit 3
Calculates the input equivalent base number for the target pin based on the level of the result of X propagation in S22 for the other input terminal of each logic gate connected to the target pin. Then, the detection unit 3 moves to S24.

S24 is another input determining means, which determines whether the level of the other input terminal of each logic gate connected to the target pin matches the other input logic preset in the logic library data 7. To judge. When the level of the other input terminal and the other input logic match, the detection unit 3 moves to S25.

S25 is a time registration means, which is the detection unit 3
Stores the test time T at that time as the measurement time in the detection result storage unit 5 together with the input equivalent base number calculated in S23. For example, the logic library data 7 describes that the input characteristic of the external input pin 53 is measured when all the other input logics with respect to the external input pin 53 are L level. Then, at the test time T ₃ , the AND circuit 21 and the OR circuit 2 connected to the external input pin 53 which is the target pin.
It is assumed that the levels of the other two input terminals are all L level as shown in FIG. At this time, since the other input logic and the level of the other input terminal match, the detection unit 3 calculates the input equivalent base number of the external input pin 53 which is the target pin.

At this time, as shown in FIG. 8A, the input equivalent base number N1 of the AND circuit 21 is "10" and the input equivalent base number N2 of the OR circuit 22 is "20". Then, the input equivalent base number ΣN of the external input pin 53
Is the input equivalent base number N1 of the AND circuit 21 and the OR circuit 2
It becomes the sum of the input equivalent base number N2 of 2 and the value is "3.
It becomes "0". The detection unit 3 has a test time T ₃ which is a measurement time.
And the input equivalent base number ΣN (= 30) are stored in the detection result storage unit 5. Further, the detection unit 3 has its external input pin 53.
Since the measurement time has been determined for, the external input pin 53 that is the target pin is deleted from the unmeasured pin group. Then, the detection unit 3 ends the time determination process.

On the other hand, if the level of the other input terminal does not match the other input logic in S24, the detecting section 3 moves to S26. Then, S26 is the input equivalent base number determining means, and the detecting unit 3 compares the previously calculated input equivalent base number with the stored input equivalent base number. For example, in FIG.
As shown in (b), the previously calculated input equivalent base number ΣN at the test time T ₄ is “22” (N1 = 2 and N2 =
20)) and the test time T _{5 in} S23.
There is a case where the input equivalent base number ΣN in Σ is ΣN = “30” (the sum of N1 = 10 and N2 = 20) as shown in FIG. 8A. At this time, since the input equivalent base number at the test time T ₅ is larger, S27 (time updating means)
In, the detection unit 3 replaces the test time T ₅ with the test time T _4, and at the same time, the input equivalent base number ΣN
(= 30) and the input equivalent base number ΣN (= 2)
2) is replaced, the detection result storage unit 5 is updated, and the time determination process ends.

In S26, if the previously calculated input equivalent base number ΣN is larger than the input equivalent base number calculated in S23, the detection unit 3 ends the time determination process without performing replacement.

Next, the case where the measurement time is set in advance for the target pin in S21 will be described. In this case, the detection unit 3 moves from S21 to S31. S3
Reference numeral 1 is a measurement time determination means, and the detection unit 3 determines whether or not the test time at that time matches the set measurement time. When the test time at that time and the set measurement time do not match, the detection unit 3 ends the time determination process.
On the other hand, when the test time at that time matches the set measurement time in S31, the detection unit 3 determines from S31 to S3.
Move to 2.

S32 is an X-propagation processing means, and the detecting section 3 carries out X-propagation similarly to S22, and then proceeds to S33. S
Reference numeral 33 is another input determination means, and the detection unit 3 determines the level of the other input terminal of each logic gate connected to the target pin and the other input logic preset in the logic library data 7 as in S24. Judge whether or not they match. When the level of the other input terminal and the other input logic match, the detection unit 3 moves to S34.

S34 is an input equivalent base number calculating means, and the detecting unit 3 for the target pin based on the level of the result of the X propagation in S32 for the other input terminal of each logic gate connected to the target pin. Calculates the input equivalent base number. Then, the detection unit 3 moves to S35.

S35 is the input equivalent base number determining means, and the detecting section 3 compares the input equivalent base number calculated in S34 with the expected value preset and stored in the signal data 8. When the calculated input equivalent base number and the expected value match, the detection unit 3 moves from S35 to S36.

S36 is an evaluation result registering means, and the detection unit 3 stores in the detection result storage unit 5 that the measurement time set for the external input pin 53 as the target pin is correct. Further, since the measurement time is determined for the external input pin 53, the detection unit 3 deletes the external input pin 53 that is the target pin from the unmeasured pin group. Then, the detection unit 3 ends the time determination process.

On the other hand, in S33, if the levels of the other input terminals and the other input logic do not match, the detecting section 3 determines S3.
Move from 3 to S37. Then, S37 is an error registration means, which makes the external input pin 53 which is the target pin an error and stores the error information in the detection result storage unit 5. Then, the detection unit 3 deletes the external input pin 53 from the unmeasured pin group, and ends the time determination process.

If the calculated input equivalent base number and the expected value do not match in S35, the detection unit 3 determines in S3.
Move from 5 to S37. Then, in S37, the external input pin 53 that is the target pin is set as an error, and the error information is stored in the detection result storage unit 5. And the detection unit 3
Deletes the external input pin 53 from the unmeasured pin group,
The time determination process ends.

When the time determination process is completed, the detection unit 3 proceeds to S
Go to 6. S6 is a remaining pin determination means, which is the detection unit 3
Confirms whether or not there is an external input pin 53 for which the time determination processing has not been performed for the test time at that time. If there is a remaining external input pin 53 that has not undergone the time determination process, the detection unit 3 moves to S7. S7 is a signal reproducing means, which reproduces the signal level of each part of the circuit data 6 at the test time T ₀ stored in S3. To reproduce this signal, in the time determination process of S5, the level of the signal is changed to determine the suitability of measuring the input characteristic at the test time. Therefore, since the levels of the input and output terminals of the logic gate are different from those of the next external input pin 53, it is possible to prevent it from being impossible to judge the suitability of the measurement of the input characteristic.

When the reproduction of the signal is completed, the detecting section 3 moves to S4 and pays attention to the next external input pin 53 and sets the external input pin 53 as the target pin. Then, the time determination process is performed on the target pin.

At the test time T ₀ , when all the external input pins 53 are set as the target pins and the time determination process is completed, the remaining external input pins 53 are exhausted in S6, and the detection unit 3 moves to S8.

S8 is a final time determination means, which compares the test time T _{0 at} that time with the final time T _E of the test signal stored in the signal data 8. Now the test time T ₀
However, since it does not match the final time T _E , the detection unit 3
Moves to S9.

S9 is an unmeasured pin determination means, and the detection unit 3 determines whether or not there is an external input pin 53 in the unmeasured pin group. At this time, if there is an external input pin 53 whose measurement time has not been determined, the process proceeds to S10.

Then, S10 is a signal reproducing means,
The detector 3 reproduces the signal for the same reason as in S7. When the reproduction of the signal is completed, the detection unit 3 moves to S2, inputs the levels of the test signals L1 to L3 at the next test time T ₁ to the external input pins 53, and the logic simulator unit 4 performs the simulation.

When the measurement time is determined for all the external input pins 53 before the test time T reaches the end time T _E , the external input pin 5 is added to the unmeasured pin group in S9.
Since 3 does not remain, the detection unit 3 moves from S9 to S11. S11 is an output means, and the detection unit 3 outputs the measurement time determined for the external input pin 53 and the input equivalent base number at the measurement time to a display device or a printing device (not shown) to perform all processing. finish.

On the other hand, when the test time T reaches the end time T _E in S8, the detecting section 3 moves from S8 to S11. Then, in S11, the detection unit 3 outputs the determined measurement time and the input equivalent base number at the measurement time to the external input pin 53 whose measurement time is determined.
Further, the detection unit 3 outputs the test time T and the input equivalent base number when the input equivalent base number becomes maximum for the external input pin 53 remaining in the unmeasured pin group.

For the external input pin 53 whose measurement time is set in advance, when the set time is judged to be suitable for measuring the input characteristic by the time judgment processing,
The detection unit 3 outputs the set time and the input equivalent base number at that time. On the other hand, when it is determined in the time determination process that the set time is not suitable for measuring the input characteristic, the detection unit 3 outputs the set time as an error. Then, when the output ends, the detection unit 3 ends all the processes.

The measurement time detected as described above is used by the test device of the semiconductor device 50 together with the signal data 8 to measure the input characteristic of the semiconductor device 50. As described above, in this embodiment, the logic simulator unit 4 inputs the circuit data 6, the logic library data 7 and the signal data 8 and inputs them to the input terminal of each logic gate based on the test signal stored in the signal data 8. Vary the level of the signal being applied. Then, the input characteristic measurement time detection unit 3 inputs the simulation result of the logic simulator unit 4, and if the measurement time is not set in advance, the input signal of the external input pin 53 focused on at the time when the level of the test signal changes. Is performed, and the input equivalent base number of the logic gate connected to the external input pin 53 is calculated for the external input pin 53.

Then, the level of the other input terminal of the logic gate is compared with the other input logic preset in the logic library data 7. When the levels of the other input terminals match the other input logic, the input characteristic measurement time detection unit 3 stores the test time at that time in the detection result storage unit 5 as the measurement time.

On the other hand, when the levels of the other input terminals do not match the other input logic, the input characteristic measurement time detection unit 3 compares the calculated input equivalent base number with the previously stored input equivalent base number. When the calculated number of input equivalent bases is larger than the previously stored input equivalent bases, the test time at that time is updated as the measurement time.

When the measurement time is set in advance, the input characteristic measurement time detection unit 3 inputs the simulation result of the logic simulator unit 4, and when the measurement time is not set in advance, the level of the test signal changes. X propagation that changes the input signal of the external input pin 53, which is sometimes noticed, is performed. Then, the level of the other input terminal of the logic gate is compared with the other input logic preset in the logic library data 7. When the level of the other input terminal and the other input logic match, the input characteristic measurement time detection unit 3 calculates the input equivalent base number of the logic gate connected to the external input pin 53 with respect to the external input pin 53. . Further, when the input equivalent base number matches the expected value, the input characteristic measurement time detection unit 3 determines that the preset measurement time is correct and stores the evaluation in the detection result storage unit 5.

On the other hand, when the level of the other input terminal does not match the other input logic, the input characteristic measurement time detection unit 3 stores the evaluation in the detection result storage unit 5 as an error at the preset measurement time. Even when the input equivalent base number does not match the expected value, the input characteristic measurement time detection unit 3
The evaluation is stored in the detection result storage unit 5 because the preset measurement time is an error.

As a result, the time suitable for measuring the input characteristic of the external input pin 53 can be automatically detected. Further, when the measurement time is set in advance, it is possible to judge whether or not the set measurement time is correct.

Furthermore, since the input characteristic of the semiconductor device can be measured by using the detected measurement time, a correct measurement result can be obtained and the test time before product shipment can be shortened.

The present invention may be carried out in the following modes other than the above embodiment. (1) In this embodiment, the logic simulator unit 4 is provided in the detection apparatus 1. However, when X propagation is not required, a simulated result is prepared in advance, and another input check is performed based on the data. You may do it. With this configuration, the time for performing X propagation is eliminated, and the time at which the input characteristic is measured can be detected faster.

(2) In the present embodiment, the flow chart of the process may be appropriately changed and implemented. For example, S22
Immediately after the X propagation is performed in step S24, another input check may be performed in step S24. Further, the reproduction of the signals of S7 and S10 may be performed after the input characteristic measurement time determination processing of S5.

(3) In this embodiment, the external input pin 5
Although the ammeter 57 and the variable power source 58 are connected to 3 to detect the time when the input characteristic is measured, the time when the other characteristic is measured may be detected.

[0072]

As described in detail above, according to the present invention,
There is an excellent effect that the measurement time suitable for measuring the input characteristic can be automatically obtained.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing the configuration of an input characteristic measurement time detection device according to an embodiment of the present invention.

FIG. 2 is a flowchart showing processing of an input characteristic measurement time detection device according to an embodiment.

FIG. 3 is a processing flow of input characteristic measurement time determination processing.

FIG. 4 is a waveform diagram showing an example of signal data.

5 (a) and 5 (b) are main circuit diagrams for explaining another input check.

6A is a diagram showing a truth value of an AND circuit including a signal X, and FIG. 6B is a diagram showing a truth value of an OR circuit.

FIG. 7 is a main part circuit diagram for explaining X propagation.

8A and 8B are circuit diagrams of main parts for explaining calculation of the number of input equivalent bases.

FIG. 9 is a schematic diagram illustrating an input characteristic measurement test.

[Explanation of symbols]

 3 Input characteristic measurement time detection unit 4 Logic simulator unit 5 Detection result storage unit 6 Circuit data 7 Logic library data 8 Signal data

Claims (4)

[Claims] 1. Circuit data (6) storing externally designed external input pins, logic gates, and connection information thereof.
And another input logic in which the level of the other input terminal is preset with respect to each input terminal of the logic gate of the circuit data (6) and each logic gate is equivalently expressed by a plurality of transistors Logic library data (7) in which the number of input equivalent bases set corresponding to the current flowing in is stored, and a test signal input to the external input pin to check the logic of the circuit data (6), Measurement time setting in which the time for measuring the input characteristic of the external input pin is preset, and the input of the logic gate connected to the external input pin when measuring the input characteristic of the external input pin with respect to the external input pin Signal data (8) storing an expected value in which the equivalent base number is set in advance is prepared, and the circuit data (6) is generated based on a test signal of the signal data (8). The level of the signal input to the input terminal of each logic gate is changed, and the level of the input terminal of the logic gate when the level of the signal changes is compared with the other input logic stored in the logic library data (7). It is determined whether they match, and if they match, the time of the test signal input to the external input pin at that time is used as the time to measure the input characteristics, and the number of input equivalent bases for the external input pin at that time is set. A method for detecting the input characteristic measurement time of a semiconductor integrated circuit device which is stored. 2. Circuit data (6) in which external input pins, logic gates, and their connection information, which are logically designed in advance, are stored.
And another input logic in which the level of the other input terminal is preset with respect to each input terminal of the logic gate of the circuit data (6), and each logic gate is equivalently expressed by a plurality of transistors, and the base of the transistor is expressed. Logic library data (7) in which the number of input equivalent bases set corresponding to the current flowing in is stored, and a test signal input to the external input pin to check the logic of the circuit data (6), Measurement time setting in which the time for measuring the input characteristic of the external input pin is preset, and the input of the logic gate connected to the external input pin when measuring the input characteristic of the external input pin with respect to the external input pin The signal data (8) in which the expected value in which the equivalent base number is set in advance and the data (6 to 8) are input, and each logic gate is input based on the test signal. A logic simulator unit (4) for changing the level of a signal input to an input terminal, and the level of the input terminal of the logic gate when the level of the test signal changes when the data (6 to 8) are input. It is determined whether or not it matches another input logic stored in the logic library data (7), and if they match, the time of the test signal input to the external input pin at that time is set as the time at which the input characteristic is measured. And an input characteristic measurement time detection unit (3) which stores the input equivalent base number for the external input pin at that time, and an input characteristic measurement time detection apparatus for a semiconductor integrated circuit device. 3. The input characteristic measurement time detection device for a semiconductor integrated circuit device according to claim 2, wherein the input characteristic measurement time detection section (3) is input to its input terminal by a logic simulator section (4). Change the signal input to the external input pin to a predetermined level, and determine whether the level of the other input terminal of the logic gate connected to the external input pin changes, If it does not change, it is judged whether the level of the input terminal of the logic gate when the level of the test signal changes matches the other input logic stored in the logic library data (7), and if they match. In addition to setting the time of the test signal input to the external input pin at that time as the time to measure the input characteristics, store the input equivalent base number for the external input pin at that time. Input characteristic measuring time detecting apparatus for a semiconductor integrated circuit device has. 4. The input characteristic measurement time detection device for a semiconductor integrated circuit device according to claim 2, wherein the input characteristic measurement time detection section (3) stores the measurement time in advance in the signal data (8). In this case, after the signal input to the input terminal of the logic simulator section (4) changes at the measurement time, the signal input to the external input pin is changed to a predetermined level. It is determined whether the level of the other input terminal of the logic gate connected to the input pin changes, and if it does not change, the level of the input terminal of the logic gate when the level of the test signal changes is the logic level. It is determined whether or not it matches the other input logic stored in the library data (7), and if they match, the input equivalent base number for the external input pin at that time is stored. Input characteristic measuring time detecting apparatus for a semiconductor integrated circuit device.