JPH07254709A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit equipped with a protection circuit that sufficiently protects an inner circuit with sure at any position on a circuit board. CONSTITUTION:A protection circuits 8b that protect an inner circuit by drawing out voltage to either of VDD bonding electrode 3 and GND bonding electrode 2 are provided at the board areas near the VDD banding electrode 3 and the GND bonding electrode 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a protection circuit for semiconductor integrated circuits.

[0002]

2. Description of the Related Art In a general MIS type semiconductor circuit,
Since the input gate of the MIS transistor is very weak against electrostatic breakdown, a protection circuit for preventing electrostatic breakdown is provided between the external connection terminal and the internal circuit to protect the internal circuit. FIG. 6 shows a circuit diagram including a conventional protection circuit. In the figure, (1) is the input bonding electrode,
(2) is a GND bonding electrode, (3) is a V _DD bonding electrode, (4) is a protective resistance, (5a) is a parasitic resistance due to wiring, and (7a) is a field transistor (hereinafter referred to as an NPN bipolar transistor). ), (8a) is a protection circuit, (9)
Is an internal circuit, and has a CMIS inverter (10) composed of a PMIS transistor (10a) and an nMIS transistor (10b) as an example. The protection circuit (8a) is connected to the internal circuit (9) through the resistor (6). FIG. 7 shows a protection circuit
The pattern diagram of (8a) is shown. (11) is input wiring, (12) is GN
D wiring, (13) contacts, (14a) and (14b) n ⁺ type active regions, (15) P ⁺ type active layer, and (16) field insulating film. The input wiring (11) has a protective resistance (4) connected to the input bonding electrode (1), an n ⁺ type active layer (14a), a resistance (6) connected to an internal circuit, and a contact (13), respectively.
Connected through. The GND wiring (12) is also connected to the n ⁺ type active layer (14b) and the P ⁺ type active layer (15) through the contact (13).

FIG. 8 is a sectional view taken along line AB of FIG. However, the wiring is schematic. (17) is a P-type region. (14a), (14b), (15) and (17) form an NPN bipolar transistor, and (14a) is the collector and (14
b) is the emitter, and (15) and (17) are the bases.

Next, the operation of the protection circuit (8a) will be described. The protective resistor (4) functions to flow a current and cause a large voltage drop. The resistor (6) serves to delay the high voltage applied to the internal circuit (10). The operation of the NPN bipolar transistor (7a) will be described with reference to FIGS. In FIG. 4, (7) is an NPN bipolar transistor, (18) is an ammeter, and (19) is a DC variable power supply.

FIG. 5 shows the voltage (V) -current (I) characteristics of the NPN bipolar transistor (7) in the circuit of FIG. When the voltage (V) is increased from 0V, the current (I) does not flow until 12V, but when it exceeds 12V, the current suddenly flows. This is because of breakdown or punch through. When the voltage is lowered, the current suddenly stops flowing at 10V. This is because of the forward current or the like. Further down from 0V, -0.8
Current flows below V. Although the voltage value varies depending on each NPN bipolar transistor, the same characteristics are exhibited. As described above, the NPN bipolar transistor (7a) does not flow a current at a low positive applied voltage, but works to flow a large current at an applied voltage of a certain value or more, and a large current even at a low voltage at a negative voltage. Works to flush. Therefore, when a positive high voltage is input to the input bonding electrode (1), the input bonding electrode (1), the protection resistor (4), the NPN bipolar transistor (7a), and the parasitic resistance shown in FIG.
A current flows through the electrode (2) for GND bonding through (5a). In addition, when a negative high voltage is input to the input bonding electrode (1), a current flows in the opposite direction to the case of the positive high voltage. As described above, the voltage flowing to the internal circuit (9) can be lowered by the flow of the current, which protects from electrostatic breakdown.

[0006]

In the conventional protection circuit,
As shown in Fig. 9, the parasitic resistance (5a1) of the protection circuit (8a1) located near the GND bonding electrode (2) on the semiconductor integrated circuit is as small as several tens of mΩ, while it is located far away. In the case of the protection circuit (8a) to be activated, the parasitic resistance (5a2) becomes several tens Ω, which is about 1000 times larger.
There is a problem in that the protection circuit (8a2) has insufficient ability to extract high voltage and the electrostatic breakdown voltage of the internal circuit (9) is reduced.

An object of the present invention is to obtain a semiconductor integrated circuit having a protection circuit capable of reliably and sufficiently protecting an internal circuit at any position on a circuit board.

[0008]

A semiconductor integrated circuit according to the present invention is formed on a semiconductor substrate and has a ground potential bonding electrode which is at a ground potential. The semiconductor integrated circuit is formed on the semiconductor substrate separately from the ground potential bonding electrode. A power source potential bonding electrode to which a power source potential is applied; and an input node and the ground potential bonding electrode, which are formed in a region where a distance from the semiconductor substrate to the ground potential bonding electrode is smaller than a distance from the power source potential bonding electrode. A first input protection transistor connected between the first input protection transistor and the power supply electrode, and a second input protection transistor connected between the input node and the power supply potential bonding electrode. A first input protection circuit for protecting the internal circuit,
A third input is formed in a region of the semiconductor substrate that is farther from the ground potential bonding electrode than the power source potential bonding electrode, and is connected between an input node and the ground potential bonding electrode. A second input protection circuit having a protection transistor and a fourth input protection transistor connected between the input node and the power supply potential bonding electrode and protecting the second internal circuit; It is characterized by having.

[0009]

In the present invention, because of the above-described structure, among the protection circuits formed on the semiconductor substrate, those formed in the substrate region closer to the ground potential bonding electrode than the power supply potential bonding electrode are: Even if there is a large parasitic resistance due to the wiring that connects this and the power supply potential bonding electrode, the constituent element of this, that is, the input protection transistor connected between the input node and the ground potential bonding electrode If a high voltage is drawn and the substrate area closer to the power supply potential bonding electrode than the ground potential bonding electrode is formed, even if the parasitic resistance due to the wiring connecting this and the ground potential bonding electrode is large, Is a component,
A high voltage is extracted to the power supply potential bonding electrode by the input protection transistor connected between the input node and the power supply potential bonding electrode.

[0010]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a circuit diagram including a protection circuit. In the figure, the same reference numerals as those in FIG. 6 indicate the same or corresponding portions, (5b) is a parasitic resistance due to wiring, (7b) is a field transistor (hereinafter referred to as NPN bipolar transistor), and (8b) is a protection circuit. is there. Where the protection circuit (8b)
Is connected to the internal circuit (9) through the resistor (6).
The difference from the conventional example is that the input bonding electrode (1) and V _DD
The point is that there is an NPN bipolar transistor (7b) between the bonding electrodes (3). The pattern diagram of the protection circuit (8b) is shown in FIG. (11) is input wiring, (12) is GND wiring,
(13) is a contact, (14a), (14c), (14d) are n ⁺ type active regions, (15) is a P ⁺ type active region, and (16) is a field insulating film. (20) is the V _DD wiring. The difference from the conventional example is that the n ⁺ type active layer (14b) is connected to the GND wiring (12) in the past, but in the present invention, the n ⁺ type active layer (14b) is (1
It is divided into 4c) and (14d), and (14c) is GND wiring (1
2), and (14d) is a point connected to the V _DD wiring (20). FIG. 3 shows a sectional view taken along the line CD of FIG. However, the wiring is schematic. (17) is a P-type region. (14a), (14c), (15), (17) and (14a), (14d), (1
Each of 5) and (17) constitutes an NPN bipolar transistor.

Next, the operation will be described. When a positive or negative high voltage is input to the input bonding electrode (1), the high voltage is discharged to the GND bonding electrode (2) by the same operation as the conventional one. Also V _DD bonding electrode
To (3), due to breakdown or punch through of NPN bipolar transistor (7b) in Fig. 1, positive high voltage is applied to input bonding electrode (1), protection resistor (4), NPN.
V through bipolar transistor (7b) and parasitic resistance (5b)
_A current flows through the _DD bonding electrode (3). In the case of a negative high voltage, the current flows exactly in the opposite way. By flowing the current as described above, the voltage applied to the internal circuit (9) can be lowered, and it is protected from electrostatic breakdown. By the way, as shown in FIG. 9, in the case of the protection circuit (8a2) located far from the GND bonding electrode (2) on the semiconductor integrated circuit, the parasitic resistance (5a2) increases and the protection circuit (8a2) There was a problem that the ability to pull out the high voltage was insufficient. In the present invention, since the V _DD bonding electrode (3) is generally separated from the GND bonding electrode (2) on the semiconductor integrated circuit as shown in FIG. 10, the V _DD bonding electrode (3) is located far from the GND bonding electrode (2). In the protection circuit (8b) located, that is, the protection circuit (8b) in which the parasitic resistance (5a) has a large value,
On the contrary, since it is close to the V _DD bonding electrode (3), the parasitic resistance (5b) is smaller than that of (5a), the ability to extract a high voltage is increased, and the electrostatic breakdown voltage of the internal circuit (9) is increased.
That is, in the semiconductor integrated circuit of the present embodiment, the GND is better than the V _DD bonding electrode (3) in the protection circuit.
What is formed in the substrate region close to the bonding electrode (2) is a component of this, even if the parasitic resistance due to the wiring connecting between this and the V _DD bonding electrode (3) is large. A high voltage is extracted to the GND bonding electrode by the NPN bipolar transistor (7b) connected between the electrode (1) and the GND bonding electrode (2), and the _VDD bonding electrode ( What is formed in the substrate region close to 3) is the same as the input bonding electrode (1), which is the constituent element of this, even if the parasitic resistance due to the wiring connecting between this and the GND bonding electrode (2) is large. withdrawing the high voltage V _DD bonding electrode (3) by V _DD bonding electrode (3) connected NPN bipolar transistor between (7a).

[0012]

As described above, according to the semiconductor integrated circuit of the present invention, in the protection circuit formed on the semiconductor substrate, in the substrate region closer to the ground potential bonding electrode than the power potential bonding electrode. What is formed is a constituent element of this, even if there is a large parasitic resistance due to the wiring that connects it and the power supply potential bonding electrode.
A high voltage is drawn to the ground potential bonding electrode by the input protection transistor connected between the input node and the ground potential bonding electrode, and is formed in the substrate region closer to the power supply potential bonding electrode than the ground potential bonding electrode. Even if the parasitic resistance due to the wiring connecting between this and the ground potential bonding electrode is large, the power supply potential bonding is performed by the input protection transistor connected between the input node and the power supply potential bonding electrode, which is a constituent element of this structure. Since a high voltage is extracted to the electrodes for use, regardless of the formation area of the internal circuit on the board, the internal circuit can be reliably and sufficiently protected regardless of the area formed on the board. There is an effect that the internal circuit can be protected by high electrostatic breakdown voltage.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a protection circuit for a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a pattern of the protection circuit shown in FIG.

FIG. 3 is a cross-sectional view taken along the line CD of FIG.

FIG. 4 is a circuit diagram for examining current-voltage characteristics of an NPN bipolar transistor.

FIG. 5 is a current-voltage characteristic diagram of an NPN bipolar transistor.

FIG. 6 is a diagram showing a configuration of a conventional protection circuit for a semiconductor integrated circuit.

7 is a diagram showing a pattern of the protection circuit shown in FIG.

8 is a cross-sectional view taken along the line C-D in FIG.

FIG. 9 is a layout diagram of a protection circuit.

FIG. 10 is a layout diagram of a protection circuit.

[Explanation of symbols]

1 input bonding electrode, 2 GND bonding electrode, 3 V _DD bonding electrode, 4 protection resistor,
5a, 5a1, 5a2, 5b Parasitic resistance, 6 resistance, 7,
7a, 7b NPN bipolar transistor, 8a, 8
a1, 8a2, 8b protection circuit, 9 internal circuit, 10
CMIS inverter, 10a PMIS transistor,
10b NMIS transistor, 11 input wiring, 12
GND wiring, 13 contacts, 14a, 14b, 1
4c, 14d n ⁺ type active layer, 15 P ⁺ type active layer, 1
6 field insulating film, 17 P type region, 18 ammeter, 19 DC power supply, 20 V _DD wiring.

Continuation of the front page (51) Int.Cl. ⁶ Identification code Reference number within the agency FI Technical indication location H01L 27/06 23/522 23/556 23/60 23/62 21/331 29/73 H01L 27/04 A 27 / 06 101 P 311 C 29/72

Claims (1)

[Claims] 1. A ground potential bonding electrode formed on a semiconductor substrate and having a ground potential, a power potential bonding electrode formed on the semiconductor substrate away from the ground potential bonding electrode, and having a power potential applied thereto. A first input that is formed in a region of the semiconductor substrate that is smaller than a distance from the power supply potential bonding electrode from the ground potential bonding electrode and that is connected between an input node and the ground potential bonding electrode. A first input protection circuit having a protection transistor and a second input protection transistor connected between the input node and the power supply potential bonding electrode, and protecting the first internal circuit; In a region where the distance from the ground potential bonding electrode of the semiconductor substrate is greater than the distance from the power potential bonding electrode. A third input protection transistor formed and connected between the input node and the ground potential bonding electrode, and a fourth input protection transistor connected between the input node and the power supply potential bonding electrode. And a second input protection circuit for protecting the second internal circuit.