JPH07254283A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To shorten the time until read operation after write operation. CONSTITUTION:A column selecting signal WCD for write is input to a column address selecting switch 1 for write in a semiconductor storage device, bit lines BL, BL-bar and data bus lines WDB, WDB-bar for write are connected at the time of write operation, and the bit lines BL, BL-bar and the data bus lines WDB, WDB-bar for write are separated at the time of read operation. A column selecting signal RCD-bar for read is input to a column address selecting switch 2 for read, the bit lines BL, BL-bar and data bus lines RDB, RDB-bar for read are separated at the time of write operation, and the bit lines BL, BL-bar and the data bus lines RDB, RDB-bar for read are connected at the time of read operation. A delay circuit 3 delays the column selecting signal RCD-bar for read to the column selecting signal WCD for write after the completion of write operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
Specifically, it relates to a random access memory (RAM).

In recent years, RAMs have been highly integrated and speeded up. Therefore, it is required to shorten the time even in the read operation of the RAM.

[0003]

2. Description of the Related Art FIG. 10 is a block circuit diagram showing a structure of a general static random access memory (SRAM).

The SRAM includes a memory cell array (memory cell matrix) 101, an address input circuit 102, a row decoder 103, a column decoder 104, a write column address selection switch (hereinafter referred to as a W column switch) 105, and a read column address selection switch. (Hereinafter referred to as R column switch) 106, an input circuit 107, a write amplifier 108, a sense amplifier 109, and an output circuit 110.

The memory cell array 101 is composed of memory cells arranged two-dimensionally, and each memory cell stores 1-bit data. Address signal A from the outside
IN is sent to the row and column decoders 103 and 104 via the address input circuit 102. Then, the row decoder 103 selects one word line WL. The column decoder 104 outputs read / write column selection signals RCD, WCD to both column switches 105, 106 according to read / write operations, and selects a pair of bit lines BL and inverted bit line bars BL. Then, a memory cell at the intersection of the selected word line WL and bit line pair BL, bar BL is determined, and the determined memory cell is the target of the read and write operations.

Input data Din from the external device is input circuit 10 when the write enable signal bar WE is at L level.
7 is sent to the write amplifier 108. Further, the column decoder 104 outputs the write column selection signal WCD to the W column switch 105 to select the bit line pair BL, bar BL. Then, the input data Din is the write amplifier 1
08 is sent to the selected bit line pair BL, bar BL via the W column switch 105. At this time, the selected word line WL is being driven by the row decoder 103. Therefore, the input data Din sent to the bit line pair BL and bar BL is the same as the selected word line WL and bit line pair B.
Data is written to the memory cell at the intersection of L and bar BL.

On the other hand, when data is read from the memory cell array 101, that is, the write enable signal bar WE is H level.
At the level, the column decoder 104 outputs the read column selection signal RCD to the R column switch 106 to select the bit line pair BL and bar BL. At this time, the selected word line WL is being driven by the row decoder 103. The data read from the memory cell at the intersection of the selected word line WL and the bit line pair BL, bar BL is sent from the bit line pair BL, bar BL to the sense amplifier 109 via the R column switch 106. The sense amplifier 109 is
Controlled by the activation signal SAP from the input circuit 107, no data is transmitted in the inactive state, and data is transmitted to the output circuit 110 in the activated state. The output circuit 110 is controlled by the control signal from the input circuit and outputs the data read from the memory cell to the output data D.
Output to an external device as out.

By the way, it may take time until the level of the selected bit line pair BL, BL is changed for the next read or write operation after the writing of the input data Din is completed. In order to shorten the changing time, each bit line pair BL and bar BL is provided with a reset circuit and precharged to a predetermined level (for example, H level). This memory cell array is shown in FIG.

FIG. 7 is a partial circuit diagram showing a conventional memory cell array. In FIG. 7, the memory cell array 1
3 shows three columns of a plurality of 01 bit line pairs. The word line WL is omitted.

Each bit line pair BL and bar BL is connected to a write data bus line WDB and bar WDB via W column switches Wa and Wb formed of N channel MOS transistors (hereinafter referred to as NMOS transistors), respectively.
Further, each bit line pair BL, bar BL is a P channel M
The read data bus lines RDB and RDB are connected via R column switches Ra and Rb formed of OS transistors (hereinafter referred to as PMOS transistors).

A load circuit E1 and a reset circuit E2 are connected to each bit line pair BL and bar BL. The load circuit E1 is composed of a PMOS transistor whose gate is connected to the low-potential-side power source Vss.
It is always connected to the high potential side power source Vcc via a MOS transistor. The reset circuit E2 is composed of a PMOS transistor, and its gate has a recovery signal bar WR.
Is entered. The recovery signal bar WR becomes L level for a predetermined time when the write enable signal bar WE becomes H level as shown in FIG. 8, and each bit line pair BL, bar BL is set to the high potential side power supply Vcc by each reset circuit E2. Connecting.

A write amplifier 108 is connected to the W data bus line pair WDB and the bar WDB, and the R data bus line pair RD is connected.
A sense amplifier 109 is connected to B and bar RDB. Write operation, that is, write enable signal bar WE
Is at the L level, the write amplifier 108 receives the input circuit 1
W data bus line pair based on input data Din from 07
Change the level of WDB and bar WDB. On the other hand, in the read operation, the sense amplifier 109 detects the R data bus line pair.
Output data Dout corresponding to the levels of RDB and RDB is output via the output circuit 110.

The W column switches Wa and Wb are NMOS transistors, the gates of which are connected to the column decoder 104 and receive the W column selection signals WCDn-1 to WCDn + 1, respectively. On the other hand, the R column switches Ra and Rb are PMOS transistors, and their gates are connected to the column decoder 104 and the R column selection signal bars RCDn-1.
Each bar RCDn + 1 is input.

The column decoder 104 inputs the address signal AIN via the address input circuit 102. Further, the column decoder 104 inputs the write enable signal bar WE via the input circuit 107. Then, as shown in FIG. 8, the column decoder 104 receives the input address signal A
Based on IN and the write enable signal bar WE, W column selection signals WCDn-1 to WCDn + 1 and R column selection signal bar RCDn
-1 to generate RCDn + 1.

Incidentally, FIG. 8 shows an R column selection signal RCDn obtained by inverting the R column selection signal bar RCDn in order to make the read or write operation easy to understand. That is, R
When the column selection signal RCDn is at H level, the read operation is performed.

That is, the write enable signal bar WE is L
At the time of the level, the W column selection signal WCDn becomes the H level based on the address signal AIN, and the other W column selection signals WCDn-1 and WCDn + 1 become the L level. Then, the W column switches Wa and Wb inputting the W column selection signal WCDn to their gates are turned on, and the W column switches Wa and Wa
The bit line pair BL and bar BL connected to Wb are connected to the W data bus line pair WDB and bar WDB. Then, the memory cell C at the intersection with the selected word line WL is determined by the row decoder 103, and the input data Din is written in the memory cell C.

At this time, the R column selection signal bar RCDn-1 ...
The bar RCDn + 1 is at H level, and each bit line pair BL, bar
BL and R data bus line pair RDB and bar RDB are not connected. Write operation is completed and write enable signal bar WE
Becomes H level, the column decoder 104 sets the W column selection signal WCD _n to L level and the W column switch Wa,
Wb is turned off, bit line pair BL, bar BL and W data bus line pair
Separate WDB and bar WDB. When the write enable signal bar WE goes high and the recovery signal bar WR goes low for a predetermined time, the load circuit E1
The bit line pair BL and bar BL are connected to the high potential side power source Vcc by the reset circuit E2. As a result, each bit line pair BL, BL is precharged to H level.

By the way, the R column selection signal bar RCDn-1 ...
The bar RCDn + 1 is determined based on the address signal AIN after the write enable signal bar WE is at the H level. That is,
After the write operation is completed, the W column selection signal WCDn in which the write operation is performed becomes L level and the bit line pair BL, bar BL and W
The data bus line pair WDB and bar WDB are disconnected. At this time, since the address signal AIN has not changed, the R column selection signal bar RCDn corresponding to the bit line pair BL and bar BL for which the write operation has been performed becomes L level, and the bit line pair BL for which the write operation has been performed. , Bar BL and R Data bus line pair RD
B and bar RDB are connected.

Then, the data written from the write amplifier 108 may be directly read by the sense amplifier 109 and output as the output data Dout. Therefore, W and R column selection signals WCDn-1 to WCDn +
1. The activation signal SAP is controlled so that the sense amplifier 109 is deactivated when the levels of the bar RCDn-1 to the bar RCDn + 1 change. As a result, since the data written from the write amplifier 108 is not output from the sense amplifier 109, it is prevented from being output as the output data Dout.

[0020]

By the way, the output data Dout requires some time from when the sense amplifier 109 is activated by the activation signal SAP to when its level actually changes. Therefore, as shown in FIG.
R column selection signal RC after the address signal AIN changes
The read operation from when the write enable signal bar WE becomes H level to when the output data Dout is read may be delayed as compared with the time until D changes. Ideally, the sense amplifier 109 is activated when the write recovery signal WR becomes H level, or the sense amplifier 109 is always activated.
In this state, the read operation time from when the write enable signal bar WE becomes H level to when the output data Dout is read can be shortened.

However, as described above, the W column selection signals WCDn-1 to WCDn + 1 and the R column selection signal bar RCDn-1 are used.
~ When the bar RCDn + 1 is switched, the sense amplifier 10
When 9 is in the activated state, the data to be written in the memory cell C is read as it is, and a malfunction occurs.

The activation signal SAP is the address signal A.
It is generated by combining IN and write enable signal bar WE. Therefore, W and R column selection signals WCDn-1 to WC
The generation of Dn + 1, RCDn-1 to RCDn + 1 is delayed. Then, the activation of the sense amplifier 109 is delayed, and the time until the output data Dout is read is delayed. As a result, the time for reading the output data Dout becomes long, and the operation of the entire semiconductor memory device cannot be speeded up.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor integrated circuit device capable of shortening the read operation time.

[0024]

FIG. 1 is a diagram for explaining the principle of the present invention. The semiconductor memory device includes a write column address selection switch 1, a read column address selection switch 2, and a delay circuit 3.

Write column address selection switch 1
Inputs the write column selection signal WCD, connects the bit lines BL and bar BL to the write data bus lines WDB and bar WDB in the write operation, and connects the bit line BL and bar in the read operation. BL and write data bus line WDB
， Separate from WDB bar.

Read column address selection switch 2
Inputs the read column selection signal bar RCD, disconnects the bit lines BL and bar BL from the read data bus lines RDB and bar RDB in the write operation, and disconnects the bit line BL and bar in the read operation. BL and data bus line for reading
Connect RDB and bar RDB.

After the write operation is completed, the delay circuit 3 delays the read column selection signal bar RCD with respect to the write column selection signal WCD.

[0028]

Therefore, according to the present invention, after the write operation for writing data into the memory cell C is completed, the read column selection signal bar RCD is set to the write column selection signal WC.
The delay circuit 3 delays D.

As a result, in the read column address selection switch 2, the write column address selection switch 1 outputs the bit line based on the write column selection signal WCD.
After disconnecting BL and bar BL from write data bus line WDB and bar WDB, bit line BL and bar BL and read data bus line based on read column selection signal bar RCD
Connect RDB and bar RDB.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment embodying the present invention will now be described with reference to FIGS.
It will be described with reference to FIG. For convenience of explanation, the same components as those shown in FIG. 10 are designated by the same reference numerals and the description thereof is partially omitted.

FIG. 2 is a partial circuit diagram of the memory cell array of one embodiment. W column switches Wa and Wb are provided between the plurality of bit line pairs BLn-1, BLn-1 to BLn + 1 and BLn + 1 connected to the memory cell C and the W data bus line pair WDB and WDB. Are connected respectively. W column switch
Wa and Wb are NMOS transistors, and W column selection signals WCDn-1 to WCDn + 1 are input to their gates, respectively. Then, the W column switches Wa and Wb are turned on when the H level W column selection signals WCDn-1 to WCDn + 1 are input to their gates, and the bit line pairs BLn-1 and BLn-1 to BLn-1 to BLn.
n + 1, bar BLn + 1 is connected to W data bus line pair WDB, bar WDB.

Each bit line pair BLn-1, bars BLn-1 to BLn + 1
, BLn + 1 are connected to the first reset circuit 11 respectively. The first reset circuit 11 is a PMOS
Bit line pair BLn-1, composed of transistors, and bar
Bit line pair BLn-1, BLn-1 to BLn + 1, and bar are connected between BLn-1 to BLn + 1 and bar BLn + 1, respectively.
They are respectively connected between BLn + 1 and the high potential side power source Vcc. The W column selection signals WCDn-1 to WCDn + 1 are input to the gates of the PMOS transistors that form the first reset circuit 11, similarly to the W column switches Wa and Wb. Then, the first reset circuit 11 is turned on when an L level W column selection signal WCDn-1 to WCDn + 1 is input to its gate, and the bit line pair BLn-1 and bars BLn-1 to BLn +.
1 and bar BLn + 1 are connected to each other and bit line pair
BLn-1, bar BLn-1 to BLn + 1, and bar BLn + 1 are connected to the high potential side power supply Vcc.

That is, when the W column selection signals WCDn-1 to WCDn + 1 are at the H level, the bit line pair BLn-1 and the bars BLn-1 to BLn + 1.
, Bar BLn + 1 is connected to the W data bus line pair WDB, bar WDB by W column switches Wa, Wb. On the other hand, when the W column selection signal WCDn-1 to WCDn + 1 is at L level, the bit line pair BLn-1, bar BLn-1 to BLn + 1, bar BLn + 1 are connected to each other by the first reset circuit 11. It is also connected to the high potential side power source Vcc.

Further, the bit line pair BLn-1 and the bars BLn-1 to BLn.
R column switches Ra and Rb are respectively connected between n + 1 and bar BLn + 1 and the R data bus line pair RDB and bar RDB. The R column switches Ra and Rb are PMOS transistors and have R column selection signal bar RCDn-1 at their gates.
~ Bar RCDn + 1 is input respectively. The R column switches Ra and Rb are turned on when the L column R column selection signals bar RCDn-1 to RCDn + 1 are input to their gates, and the bit line pair BLn-1 and bar BLn-1 to BLn + 1 are turned on. ， Bar BLn
+1 and R data bus line pair RDB and bar RDB are connected.

Each bit line pair BLn-1, bars BLn-1 to BLn + 1
, BLn + 1 are connected to the second reset circuit 12, respectively. The second reset circuit 12 is an NMOS
Bit line pair BLn-1, composed of transistors, and bar
Connected between BLn-1 ~ BLn + 1 and BLn + 1,
It is connected between the bit line pair BLn-1, bars BLn-1 to BLn + 1, bar BLn + 1 and the high potential side power supply Vcc. Similarly to the R column switches Ra and Rb, R column selection signals bar RCDn-1 to bar RCDn + 1 are input to the gates of the PMOS transistors forming the second reset circuit 12. Then, the second reset circuit 12 is turned on when the H-level R column selection signal bar RCDn-1 to RCDn + 1 is input to its gate, and turns on, and the bit line pair BLn-1 and bar BLn-1 to BLn +.
1 and bar BLn + 1 are connected to each other and bit line pair
BLn-1, bar BLn-1 to BLn + 1, and bar BLn + 1 are connected to the high potential side power supply Vcc.

That is, R column selection signal bar RCDn-1 to bar
When RCDn + 1 is at L level, bit line pair BLn-1 and bar BLn-
1 to BLn + 1 and bar BLn + 1 are connected to the R data bus line pair RDB and bar RDB by R column switches Ra and Rb. On the other hand, when the R column selection signal bar RCDn-1 to bar RCDn + 1 is at the H level, the bit line pair BLn-1, bar BLn-1 to BLn + 1, bar BLn + 1 are mutually set by the second reset circuit 12. In addition to being connected, it is connected to the high potential side power source Vcc.

The W column selection signals WCDn-1 to WCDn + 1 and the R column selection signals RCDn-1 to RCDn + 1 are applied to the column decoder 10.
Input from 4. FIG. 3 is a partial circuit diagram of the address input circuit 102. The address input circuit 102 is provided with an external input terminal 21 for inputting the address signal AINn. The input terminal of the inverter circuit 22 is connected to the external input terminal 21. The output terminals of the inverter circuit 22 are connected to odd-numbered stages (three stages in this embodiment) of serially connected inverter circuits 23 to 25, and even-numbered (two stages in this embodiment) inverter circuits 26 and 27. Are connected.

When the address signal AINn is input from the external input terminal 21, the address input circuit 102 generates the internal address signal An via the inverter circuit 22 and the odd-numbered inverter circuits 23 to 25. Further, the internal address signal bar An is generated via the inverter circuit 22 and the even-numbered inverter circuits 26 and 27. Then, the generated internal address signals An and Bar An are output to the row or column decoders 103 and 104.

The address signal is the storage capacity of SRAM,
That is, the memory cells C arranged in the memory cell array 101
The number of rows and columns is set. The address input circuit 102 of FIG. 3 is also provided with a number of circuits corresponding to the number of address signals. And
The internal address signal generated by each circuit corresponding to the address signal is output to the row or column decoder 103, 104.

FIG. 4 is a partial circuit diagram of the input circuit 107, which shows the write enable signal bar WE to the first write enable signal WE1 and the second write enable signal bar WE.
2 is an internal enable signal generation circuit 107a for generating 2. The internal enable signal generation circuit 107a is provided with an external input terminal 31 for inputting the write enable signal bar WE. To the external input terminal 31, even-numbered stages (two stages in this embodiment) of serially connected inverter circuits 32 and 33 are connected. To the output terminal of the inverter circuit 33, odd-numbered stages (three stages in this embodiment) of serially connected inverter circuits 34 to 36 are connected. Each inverter circuit 3
Reference numerals 2-36 generate the first write enable signal WE1 by inverting the input write enable signal WE.

The NAND circuit 37 is directly connected to the output terminal of the inverter circuit 33, and the delay circuit 3 is provided.
8 to the NAND circuit 37. The delay circuit 38 is composed of even-numbered stages (two stages in this embodiment) of serially connected inverter circuits 39 and 40, and delays the input signal by a delay time t determined by the inverter circuits 39 and 40. There is. This delay time t
Is set shorter than the time when the R column selection signal RCD changes based on the change of the address signal AIN shown in FIG. The inverter circuit 4 is connected to the output terminal of the NAND circuit 37.
1 input terminal is connected.

The write enable signal bar WE is directly input from the inverter circuit 33 to the NAND circuit 37, and is also input to the NAND circuit 37 via the delay circuit 38. Then, the NAND circuit 37 logically synthesizes the signal input directly from the inverter circuit 33 and the signal input via the delay circuit 38, and the synthesized signal is output to the inverter circuit 4
It is output as the second write enable signal bar WE2 via 1.

When the write enable signal bar WE rises from the L level to the H level, the signal is input to the NAND circuit 37 via the inverter circuits 32 and 33 and further input to the NAND circuit 37 via the delay circuit 38. To be done. That is, the NAND circuit 37 logically synthesizes a signal which rises based on the rising edge of the write enable signal bar WE and a signal which rises after a delay time t from the write enable signal bar WE. On the other hand, the first write enable signal WE1 falls on the rising edge of the write enable signal bar WE. As a result, the second write enable signal bar WE2 changes to the first write enable signal WE1.
Will fall with a delay time t from the fall of.

On the other hand, when the write enable signal bar WE falls from the L level to the H level, the signal is input to the NAND circuit 37 via the inverter circuits 32 and 33, and further, to the NAND circuit via the delay circuit 38. 37 is input. That is, the NAND circuit 37 has a signal that falls based on the rise of the write enable signal bar WE,
The write enable signal bar WE is logically synthesized with a signal falling with a delay time t. On the other hand, the first write enable signal WE1 rises based on the fall of the write enable signal bar WE. As a result, the second write enable signal bar WE2 rises with the rising of the first write enable signal WE1.

The second and second write enable signals
WE1 and WE2 are output to the column decoder 104.
FIG. 5 is a partial circuit diagram of the column decoder 104.
A column selection signal generation circuit 104a that generates a W column selection signal WCDn and an R column selection signal RCDn. A plurality of column selection signal generation circuits 104a (two in this embodiment)
NAND circuits 51 and 52 are provided. The internal address signals An and An + 1 are input to the NAND circuit 51, and the internal address signals An + 1 and An + 2 are input to the NAND circuit 52.

The output terminals of the NAND circuits 51 and 52 are connected to the input terminals of the NAND circuit 55 via the inverter circuits 53 and 54, respectively. An inverter circuit 56 is connected to the output terminal of the NAND circuit 55. Then, the column selection signal Bn is generated based on the input address signals An to An + 2. The column selection signal Bn is input to the NAND circuits 57 and 58, respectively.

The NAND circuit 57 is a two-input element, one of which receives the column selection signal Bn and the other of which receives the first write enable signal WE1 from the internal write enable signal generating circuit 107a. To be done. An inverter circuit 59 is connected to the output terminal of the NAND circuit 57. The NAND circuit 57 and the inverter circuit 59 use the column selection signal Bn and the first write enable signal WE1.
The W column selection signal WCDn is generated by The W column selection signal WCDn is the first reset circuit 11 and the W column switch connected to the bit line pair BLn, BLn in FIG.
Input to the Wa and Wb gates respectively.

The NAND circuit 58 is a 2-input element, and the column selection signal Bn is input to one of the two input elements, as in the NAND circuit 57, and the other is a second input from the internal write enable signal generating circuit 107a. The write enable signal bar WE2 is input. Inverter circuits 60 and 61 connected in series are connected to the output terminal of the NAND circuit 58. Then, the NAND circuit 58 and the inverter circuit 60 generate the R column selection signal bar RCDn from the column selection signal Bn and the second write enable signal bar WE2. The R column selection signal RCDn shown in FIG. 6 is output via the inverter circuit 61.

At this time, the second write enable signal bar WE2 falls after a delay time t from the fall of the first write enable signal WE1. Therefore, the rising of the R column selection signal bar RCDn is delayed from the W column selection signal WCDn by the delay time t as shown in FIG. The R column selection signal bar RCDn is input to the gates of the second reset circuit 12 and the R column switches Ra and Rb connected to the bit line pair BLn and bar BLn of FIG. 2, respectively.

The column selection signal generation circuit 104 shown in FIG.
a is a partial circuit diagram of the column decoder 104, which includes a plurality of bit line pairs BLn-1 and BL of the memory cell array 101.
Actually, the number of column selection signal generation circuits 104a corresponding to n-1 to BLn + 1 and bar BLn + 1 is actually provided. Therefore, in FIG. 2, the bit line pair BLn-1 and the bars BLn-1 to BLn +.
1, W column switches Wa and Wb connected to the bar BLn + 1 and W column selection signals WCDn-1 and WCDn + 1 respectively inputted to the gates of the first reset circuit 11 are similarly generated to generate other column selection signals. It is generated by the circuit 104a. Further, R column selection signals input to the R column switches Ra and Rb connected to the bit line pair BLn-1, BLn-1 to BLn + 1, BLn + 1 and the gate of the second reset circuit 12, respectively. The bar RCDn-1 and bar RCDn + 1 are also other column signal generation circuits 10.
4a.

That is, the R column selection signal bar RCDn-1 is R
As with the column selection signal bar RCDn, its rising edge is delayed from the W column selection signal WCDn-1 by a delay time t. Further, the rising of the R column selection signal bar RCDn + 1 is delayed from the W column selection signal WCDn + 1 by a delay time t, similarly to the R column selection signal bar RCDn.

Next, the operation of the semiconductor memory device configured as described above will be described. During a write operation, that is, when the write enable signal bar WE is at the L level, one set of W column switches Wa and Wb is selected by the W column selection signal WCD, for example, the W column selection signal WCDn, based on the address signal AIN, and turned on. Become. At this time, R column selection signal bar RC
Since Dn is at the H level, the R column switches Ra and Rb are turned off. As a result, the bit line pair BLn and bar BLn are connected to the W data line pair WDB and bar WDB. Then, the input data Din is input to the write amplifier 108, and the levels of the W data line pair WDB and WDB are changed based on the input data Din.

Then, through the W column switches Wa and Wb selected by the W column selection signal WCDn, the bit line pair BLn
, The level of the W data bus line pair WDB, bar WDB is transmitted to the bar BLn. Then, data is written to the memory cell C connected to the intersection of one word line (not shown) selected by the row decoder 103 based on the address signal AIN and the bit line pair BLn, BLn.

When the write enable signal bar WE becomes H level, that is, the read operation is completed after the write operation is completed, the W column selection signal WCDn falls to L level based on the rise of the write enable signal bar WE. Then, the W column switches Wa and Wb for inputting the W column selection signal WCDn to the gate are turned off, and the bit line pair BLn and bar BLn are disconnected from the W data bus line pair WDB and bar WDB. On the other hand, the first reset circuit 11 connected to the pair of bit lines BLn and BLn has the W column selection signal at its gate.
Since WCDn is input, it is turned on and bit line pair BLn,
The bar BLn is connected to the high potential side power source Vcc.

At this time, the R column selection signal bar RCDn is at H level.
It is a level. Since the second reset circuit 12 inputs the R column selection signal bar RCDn to the gate, it is on and connects the bit line pair BLn, bar BLn to the high potential side power source Vcc. As a result, the bit line pair BLn,
The bar BLn is precharged to H level by the first and second reset circuits 11 and 12.

That is, since the bit line pair BLn and bar BLn are precharged by the W column selection signal WCDn and the R column selection signal RCDn, the conventional recovery signal bar
Does not require WR. As a result, conventional recovery signal bars
A circuit for generating the WR and a signal line for transmitting the recovery signal bar WR are unnecessary, and the degree of integration of the SRAM can be further increased. In addition, since it is not necessary to adjust the timing for generating the recovery signal bar WR, SRA
The design of M becomes easy.

When the time corresponding to the delay time t has elapsed, the R column selection signal bar RCDn falls to the L level. Then, the R column switches Ra and Rb inputting the R column selection signal bar RCDn to their gates are selected and turned on. On the other hand, the second reset circuit 12 inputting the R column selection signal bar RCDn to its gate is turned off.
As a result, the bit line pair BLn, BLn is selected and connected to the R data bus line pair RDB, RDB. At this time,
The bit line pair BLn and bar BLn are precharged by the first and second reset circuits 11 and 12 after the W column switches Wa and Wb are turned off and separated from the W data bus line pair WDB and bar WDB. Therefore, since the data written in the memory cell C does not remain in the bit line pair BLn and bar BLn, the written data is written even if the R column switches Ra and Rb are turned on and the R data bus line pair RDB and bar RDB are connected. Is not output. That is, since the data written from the write amplifier 108 is not output from the sense amplifier 109, it is not output as the output data Dout. As a result, the sense amplifier 109 can be kept in the active state at all times, and the activation signal SAP is not required, so that the output data D can be output after the write enable signal bar WE is switched.
The time until out is output becomes shorter. Therefore, the read operation time of the semiconductor memory device can be shortened.

When the data read is completed and the write enable signal bar WE becomes L level again, the second and second write enable signals WE1 and WE2 simultaneously rise based on the fall of the write enable signal bar WE. . As a result, the W column selection signal WCDn and the R column selection signal bar RCDn fall at the same time. Then, the R column switches Ra and Rb inputting the R column selection signal bar RCDn to their gates are turned off. Also, the W column switch W that inputs the W column selection signal WCDn to its gate
a and Wb are turned on. As a result, bit line pair BLn, bar B
Ln is separated from the R data bus line pair RDB and bar RDB and connected to the W data bus line pair WDB and bar WDB. Then, similarly to the above, the input data Din is written into the memory cell C via the write amplifier 108. Therefore, the writing operation of the semiconductor memory device is not delayed.

As described above, in this embodiment, the delay circuit 38 is provided in the internal write enable signal generation circuit 107a,
The fall of the second write enable signal bar WE2 is delayed from the first write enable signal WE1 by a delay time t. Then, the column selection signal generation circuit 104a generates the W column selection signal WCDn based on the first write enable signal WE1 and outputs the second write enable signal bar WE.
The R column selection signal bar RCDn is generated based on 2. Therefore, the fall of the R column selection signal bar RCDn is delayed by the delay time t from the fall of the W column selection signal WCDn. Then, the W column selection signals WCDn control the W column switches Wa and Wb and the first reset circuit 11. Further, the R column switches Ra and Rb and the second reset circuit 12 are controlled by the R column selection signal bar RCDn.

First, the bit line pair BLn and the bar BLn
Is a W data bus line pair WDB by W column switch Wa, Wb
， Bar WDB disconnected from the first reset circuit 11
As a result, the bit line pair BLn, BLn is connected to the high potential side power source Vcc. Then, the first and second reset circuits 1
1 and 12 sets the level of the bit line pair BLn, BLn to H
Precharge to level is done. Next, the bit line pair BLn and bar BLn are connected to the R data bus line pair RDB and bar RDB by the R column switches Ra and Rb.
Therefore, since the data written by the write amplifier 108 is precharged, it is not read by the R data bus line pair RDB, RDB.

As a result, the sense amplifier 109 can always be activated, and the conventional activation signal SAP is not required. Therefore, the time for preparing the output data Dout from the rising of the write enable signal WE is shortened. To be done.
Therefore, the read operation time of the semiconductor memory device can be shortened.

The present invention may be carried out in the following modes other than the above embodiment. (1) In the above embodiment, the first reset circuit 11 is composed of NMOS transistors. Further, the W column switches Wa and Wb are each composed of a PMOS transistor. W column selection signals WCDn-1 to WCDn + 1 are input to the gates via inverter circuits. With this configuration, the same effect as that of the above embodiment can be obtained.

In addition, the second reset circuit 12 is PMOS
Composed of transistors. In addition, R column switch Ra,
Each Rb is composed of an NMOS transistor. Then, R column selection signals bar RCDn-1 to bar RCDn + 1 are input to the gates of the PMOS transistors via inverter circuits, respectively. With this configuration, the same effect as that of the above embodiment can be obtained.

(2) In the above embodiment, the W column switch
Wa, Wb and R column switch Ra, Rb for each bit line pair BLn-
1, bar BLn-1 to BLn + 1, bar BLn + 1 provided at both ends of each bit line pair BLn-1, bar BLn-1 to BLn + 1, bar BLn + 1 and W data bus line pair WDB, bar WDB and R data bus line pair
RDB and bar RDB were connected, but each bit line pair
W column switches Wa, Wb and R column switches Ra, Rb are connected to one end of BLn-1, bar BLn-1 to BLn + 1, bar BLn + 1, and W data bus line pair WDB, bar WDB and R data bus. It may be connected to a wire pair RDB or bar RDB.

(3) The present invention may be applied to a dynamic random access memory (DRAM).

[0066]

As described in detail above, according to the present invention,
There is an excellent effect that the time for the read operation can be shortened.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a partial circuit diagram illustrating a memory cell array according to an embodiment.

FIG. 3 is a partial circuit diagram illustrating an address input circuit.

FIG. 4 is a partial circuit diagram of an input circuit that generates first and second write enable signals.

FIG. 5 is a partial circuit diagram of a column decoder that generates a read / write column selection signal.

FIG. 6 is a waveform diagram illustrating the operation of the SRAM.

FIG. 7 is a partial circuit diagram illustrating a conventional memory cell array.

FIG. 8 is a waveform diagram illustrating an operation of a conventional SRAM.

FIG. 9 is a waveform diagram showing an address signal and a read column selection signal in an address change.

FIG. 10 is a block circuit diagram showing a configuration of a general SRAM.

[Explanation of symbols]

 1 write column address select switch 2 read column address select switch 3 delay circuit BL, bar BL bit line WL word line C memory cell WDB, bar WDB write data bus line RDB, bar RDB read data bus line WCD write Column selection signal Bar RCD read column selection signal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location G11C 11/34 354 D

Claims (5)

[Claims] 1. A data bus line (WDB) for writing to a memory cell (C) connected to a bit line (BL, BL).
, Bar WDB) and a read operation for reading data stored in the memory cell (C) through the read data bus line (RDB, bar RDB). It is connected between the bit line (BL, bar BL) and the write data bus line (WDB, bar WDB) and receives the write column selection signal (WCD) and is based on the write column selection signal (WCD). In the write operation, the bit line (BL, bar BL) and the write data bus line (WDB, bar WDB) are connected, and in the read operation, the bit line (BL, bar BL) and the write data are connected. Bus line (WDB, bar
WDB) is connected to the write column address select switch (1) for disconnecting the read column select signal (1) from the bit line (BL, bar BL) and the read data bus line (RDB, bar RDB). Bar RCD) is input, and in the case of a write operation based on the read column selection signal (bar RCD), the bit line (BL, bar BL) and the read data bus line (RDB, bar RDB) are disconnected. In the case of read operation, read column address selection switch (2) that connects the bit line (BL, bar BL) and read data bus line (RDB, bar RDB), and write column selection after the write operation is completed Signal (WCD
), A delay circuit (3) for delaying the read column selection signal (bar RCD). 2. The semiconductor memory device according to claim 1, comprising the delay circuit (38), receiving the write enable signal (bar WE), and inputting the write enable signal (bar WE).
First write enable signal (WE1) based on WE)
And an internal circuit for delaying the rising of the write enable signal (bar WE) by a delay circuit (38) and generating a second write enable signal (bar WE2) based on the delayed write enable signal (bar WE2). A write enable signal generating circuit (107a) and a first write enable signal (WE1, bar WE2) based on the first and second write enable signals (WE1, bar WE2) generated by the internal write enable signal generating circuit (107a). WE1) to write column select signal (WCD)
And a column selection signal generation circuit (104a) for generating a read column selection signal (bar RCD) from the second write enable signal (bar WE2). 3. The semiconductor memory device according to claim 1, wherein the bit line (BL, bar BL) is provided to the bit line (BL, bar BL) based on the write column select signal (WCD). A first reset circuit (11) for connecting the bit lines (BL, bar BL) to a high potential side power source (Vcc) and a bit line based on the read column selection signal (bar RCD). A second reset circuit (12) for connecting (BL, bar BL) to each other and for connecting the bit line (BL, bar BL) to a high potential side power supply (Vcc), and a first reset circuit (11) ), The bit line (BL, bar BL) and the write data bus line (WDB, bar WDB) are separated by the write column address selection switch (1) based on the write column selection signal (WCD). Sometimes bit line (BL , Bar BL) are connected to each other and also connected to the high-potential side power supply (Vcc), and the second reset circuit (12) uses the read column address selection switch (2) based on the read column selection signal (bar RCD). ) Disconnects the bit line (BL, bar BL) from the read data bus line (RDB, bar RDB), the bit line (BL, bar BL) is connected to each other and the high potential side power supply (Vcc) A semiconductor memory device characterized by being connected to a. 4. The semiconductor memory device according to claim 1, wherein the write column address selection switch (1) comprises:
An N-channel MOS transistor (Wa, Wb), the gate of which receives the write column select signal (WCD), and the read column address select switch (2)
A P-channel MOS transistor (Ra, Rb), the gate of which is the read column select signal (bar RCD).
) Is input, the semiconductor memory device characterized by inputting. 5. The semiconductor memory device according to claim 3, wherein the first reset circuit (11) is a P channel MOS.
The write reset column select signal (WCD) is input to the gate of the transistor, and the second reset circuit (12) is an N channel MOS transistor.
A semiconductor memory device comprising a transistor, the gate of which receives a read column selection signal (bar RCD).