JPH07253796A - Digital signal recording device and digital signal reproducing device - Google Patents

Abstract

PURPOSE:To efficiently increase a recording time while maintaining the recording quality of digital signal to be recorded in a solid-state memory in quality as high as possible. CONSTITUTION:A hierarchial encoder is constituted of a band divider 12. quantizers 13 to 16, a hierarchy divider 17 and an input signal is divided into M pieces of bands by the band divider 12 and bands are respectively quantized into previously given number of bits by quantizers 13 to 16 and then quantized codes having quantized Q bits in total are inputted to the hierarchy divider 17 to be divided into a first to Nth hierarchies by a predetermined method. A write-in controller 19 writes respective hierarchial data in data storage areas of a solid-state memory 18 in a predetermined address order. At this time, in the case high-order hierarchial data are aleady written in an address in which the data are to be written, the controller 19 stops the writing. Then, auxiliary information expressing attributions of data such as the address in which hierarchial data are to be stored, etc., are stored in the atociliary information storage area of the solid-state memory 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal recording device and a digital signal reproducing device for encoding and recording a digital signal in a solid-state memory.

[0002]

2. Description of the Related Art In recent years, with the increase in capacity and cost of semiconductor memories (solid-state memories), digital signal recording / reproducing devices using solid-state memories as recording media are expected as next-generation recording / reproducing devices. However, at present, the solid-state memory is very expensive as compared with other recording media such as a magnetic tape, a magnetic disk, and an optical disc, which prevents the practical application of a digital signal recording / reproducing device using the solid-state memory. The signal compression technique is an effective means for effectively utilizing the solid-state memory and putting the digital signal recording / reproducing device into practical use.
On the other hand, when the compression rate is increased, the recording quality is deteriorated.

A conventional example closest to the present invention will be described below by taking Japanese Patent Laid-Open No. 305053/1990 as an example. The invention described in this publication makes it possible to vary the bit rate when encoding a digital signal. When the memory capacity is sufficient, the digital signal is encoded at a high bit rate and recorded in the solid-state memory. Next, when the remaining capacity of the solid-state memory becomes low, the data recorded at the high bit rate is read from the solid-state memory, and the bit rate is reduced and re-encoded by a compression algorithm different from the original one. To record. By doing so, an empty area is secured in the solid-state memory. By repeating this series of processes, the contradictory problems of recording quality and longer recording time are addressed.

Further, the applicant of the present invention filed Japanese Patent Application No. 5-27181.
No. 8 (hereinafter, abbreviated as prior application) proposes a digital signal recording / reproducing apparatus based on a hierarchical encoding method, which is the basis of the present application.

[0005]

However, in the above-mentioned conventional example, in order to secure an empty area in the solid-state memory, the data recorded at a high bit rate is read from the solid-state memory, and the bit is compressed by a compression algorithm different from the original one. Since the rate must be reduced and re-encoded, the load on the hardware is large and the efficiency is low. Further, there is a problem that an unused area is generated in the solid-state memory depending on the amount of data, and the solid-state memory cannot be effectively used.

Further, in the above-mentioned prior application by the present applicant, there is no particular limitation on the specific structure of the hierarchical encoder and the method of storing hierarchical data in the solid-state memory.

In view of the above problems, the present invention provides a digital signal recording / reproducing apparatus capable of effectively extending the recording time while maintaining the recording quality as much as possible and effectively utilizing the solid-state memory. With the goal. Further, by adding a new configuration regarding the specific configuration of the hierarchical encoder and the method of storing hierarchical data in the solid-state memory, which are not limited in the above-mentioned prior application, the above-mentioned object can be realized by a simple process. It is a thing.

[0008]

In order to achieve the above object, a digital signal recording apparatus according to a first aspect of the present invention is a hierarchical coding for coding a digital signal from first hierarchical data to maximum Nth hierarchical data. And a solid-state memory having a data storage area for storing data hierarchically encoded by the hierarchical encoder and an auxiliary information storage area for storing auxiliary information indicating an attribute of the stored data, and writing of the solid-state memory When the available area is insufficient, at least the first hierarchical data among the hierarchical data stored in the solid-state memory is retained, but at least a part of the hierarchical data of any other hierarchical data is released to release the memory. Device and a storage area corresponding to the data area released by the memory releaser, the hierarchical data of the arbitrary number of N or less, including at least the first hierarchical data, is deselected. And a write controller for storing auxiliary information representing an attribute of the stored data in the auxiliary information storage area, wherein the hierarchical encoder has M input signals (M ≧ 1). A band divider for dividing into bands,
Receiving the M band signals divided by the band divider,
Receiving M quantizers for quantizing with a predetermined number of bits and a total of Q-bit quantizers quantized by the M quantizers, the quantizers are predetermined. It is configured by a hierarchy divider that divides the hierarchy into N (N> 1) layers by the above method.

Further, the digital signal recording apparatus of the second invention relates to the control method of the write controller, wherein the write controller sequentially stores each hierarchical data in the storage device in a predetermined address order for each hierarchical data. When writing each layer data in the address order, it is a write controller for writing, and in the area in which the layer data is to be written, if layer data having a layer order higher than the layer order of the layer data is already written, It has a rule to stop the writing process of the hierarchical data.

The digital signal recording apparatus of the third invention also relates to the control method of the write controller, wherein the write controller sets an address for stopping the write processing of each hierarchical data to a bit rate of each hierarchical data. And the capacity of the data storage area, and the writing process of each hierarchical data is stopped when the write address reaches the address.

A digital signal reproducing apparatus according to the present invention has a data storage area for storing hierarchically encoded hierarchical data and an auxiliary information storage area for storing auxiliary information representing an attribute of the stored data. The solid-state memory in which the hierarchical data and the auxiliary information representing the attribute of the hierarchical data are recorded by the digital signal recording device of the present invention, the hierarchical data stored in the solid-state memory, and the stored hierarchical data. The auxiliary information representing the attribute is read, and a hierarchical decoder that decodes the original digital signal according to the hierarchy of the hierarchical data is provided, and inside the hierarchical decoder, in the auxiliary information storage area in the solid-state memory. A reading controller for reading the stored auxiliary information and sequentially reading the hierarchical data stored in the data storage area in the solid-state memory based on the auxiliary information A.

[0012]

According to the first aspect of the present invention, the digital signal is first input to the hierarchical encoder and encoded into the first to Nth hierarchical data by the above configuration. The hierarchical encoder includes a band divider, a quantizer, and a layer divider, and an input signal is first divided into M bands by the band divider. Next, these M band signals are quantized by a quantizer to a predetermined number of bits. The quantized total Q-bit quantized code is input to the layer divider and divided into the first to Nth layers by a predetermined method. Next, these hierarchical data are stored in the data storage area of the solid-state memory. In addition, auxiliary information representing data attributes, such as the address where the hierarchical data is stored, is stored in the auxiliary information storage area of the solid-state memory. How the hierarchical data is stored in the solid state memory is controlled by the write controller. When the memory is full, the write controller releases a data storage area in which a part of hierarchical data (preferably lower important hierarchical data) is stored and secures a free area. Then, new hierarchical data and auxiliary information are stored in the vacant area. While maintaining the recording quality as much as possible by repeating the above series of processing, the recording time can be efficiently extended, and since the data is effectively stored in the solid-state memory,
It is possible to effectively use the solid-state memory.

Further, in the second invention, the write controller writes each hierarchical data in the data storage area of the solid-state memory in a predetermined address order. Then, if the hierarchical data higher than itself has already been written at the address to be written next, a rule is set to stop the writing process at that time. When the memory becomes full by this, writing is automatically stopped from the lower hierarchy, and the recording time can be efficiently extended by an extremely simple process.

Further, in the third invention, like the second invention, the write controller writes each hierarchical data in the data storage area of the solid-state memory in a predetermined address order. The address at which the writing of each hierarchical data is stopped is determined in advance according to the bit rate of each hierarchical data and the size of the data storage area. The second invention has an advantage that writing is automatically stopped from a lower hierarchy by a simple rule, but when the number of hierarchies is 6 or more, it becomes difficult to allocate a data area for each hierarchy. On the other hand, in the third invention, the write processing can be stopped in any order regardless of the number of layers.

Further, according to the digital signal reproducing apparatus of the present invention, it becomes possible to efficiently read and decode the data recorded by the digital signal recording apparatus of the present invention.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital signal recording device and a digital signal reproducing device according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the arrangement of a digital signal recording apparatus according to the first embodiment of the present invention. Figure 1
11 is an analog audio input signal, for example, 1
A / D converter for converting to 6-bit digital signal, 1
Reference numeral 2 is a band divider for dividing the 16-bit digital signal from the A / D converter 11 into four bands from a first band signal to a fourth band signal, and 13 is a band divider for dividing the first band signal into 6 bands. First quantizing with bits and outputting first coded data
, A second quantizer 14 quantizes the second band signal with 4 bits and outputs second code data, and a 15 quantizes the third band signal with 3 bits. A third quantizer for digitizing and outputting third code data, 16
Is a fourth quantizer that quantizes the fourth band signal with 3 bits and outputs fourth code data, and 17 is a total of 16 bits of code data of the first to fourth code data. A layer divider that receives and outputs four-layer hierarchical data from the first hierarchical data to the fourth hierarchical data of 4 bits, and 18 is a data storage that stores the data hierarchically encoded by the hierarchical divider 17. A solid-state memory having an area and an auxiliary information storage area for storing auxiliary information indicating the attribute of the stored data. Reference numeral 19 denotes hierarchical data stored in the solid-state memory 18 when the writable area of the solid-state memory 18 is insufficient. Among these, at least the first layer data is held, at least a part of the data area of the layer data of any other layer is released, and the data corresponding to the released data area is released. In the region, including at least the first layer data, a write controller for storing hierarchical data in the number of 4 or less arbitrary hierarchy.

Here, the meaning of releasing the data area means that even if there is already written data in the data area, it is permitted to write new data in the area. Is.

FIG. 2 is a block diagram showing an example of the configuration of the band divider 12 shown in FIG. As shown in FIG. 2, the band divider 12 includes a QMF (quadrature mirror filter) 2
A QMF filter bank composed of stages, which is a band divider that has been widely used in the past (eg, Digital Signal Processing Handbook, edited by Institute of Electronics, Information and Communication Engineers, pp.135-
137 1993 ''). In the present embodiment, the QMF filter bank as described above is used as an example of the band divider, but in addition to this, a polyphase filter bank or a hybrid poly filter filter used in the MPEG audio encoding algorithm or the like is used. It is also possible to use a phase / MDCT filter bank (ISO / IEC 11172-3: 199
See 3).

In the present embodiment, the numbers of bits quantized by the first to fourth quantizers are 6 bits, 4 bits, 3 bits and 3 bits respectively, but it is not always necessary to do so, and for example, 6 bits, 5 bits, 3 bits,
It may be 2 bits or the like. In addition, in the present embodiment, the first to fourth quantizers are quantizers that perform linear quantization with the predetermined number of bits as described above, respectively.
It may be a non-linear quantizer that performs non-linear conversion with a logarithmic function or a hyperbolic function (see "Digital Signal Processing Handbook, ed. The Institute of Electronics, Information and Communication Engineers, pp. 16-17 1993"). Further, a quantizer which performs quantization while normalizing the amplitude according to the amplitude value of the input signal as in the case of the MPEG audio encoding algorithm or the like (ISO
/ See IEC 11172-3: 1993).

In FIG. 3, when the number of bits allocated to each band is 6 bits, 4 bits, 3 bits and 3 bits, respectively, the hierarchy divider 17 causes the code of 16 bits in total of the first to fourth code data. It shows an example of which bit in the data is applied to which hierarchy. The number in each frame in FIG. 3 is a number indicating which layer. Bands 1 to 4 shown in FIG. 3 are the lowest frequency bands in band 1, and become higher frequency bands in the order of band 4. In FIG. 3, the first
Layer data is 4-bit data of 4 bits on the MSB side of the first code data, and the second layer data is the second LBS 1 bit of the first code data and the MSB of the second code data.
3 bits on the side, a total of 4 bits, the third layer data is
The MSB side 2 bits of the third code data and the MSB side 2 bits of the fourth code data, a total of 4 bits data, and the fourth hierarchical data is the first LSB 1 bit of the first code data and the second code data. First LSB 1 bit, first LSB 1 bit of third code data, and first LS of fourth code data
The hierarchical structure is such that B1 bit is a total of 4 bit data. The hierarchical division as described above is
It is based on the idea that the information in the lower frequency band and the information on the MSB side in each band are more important. In other words, since the hierarchical division may be performed in the order of importance of code data, the hierarchical division as described above is not always necessary.

In FIG. 4, when the number of bits assigned to each band is 6 bits, 5 bits, 3 bits, and 2 bits, respectively, the hierarchy divider 17 causes the code of the above-mentioned first to fourth code data to be 16 bits in total. It shows an example of which bit in the data is applied to which hierarchy. The number in each frame in FIG. 4 is a number indicating which layer. In FIG. 4, the first hierarchical data is 4-bit data of 4 bits on the MSB side of the first coded data, and the second hierarchical data is the MSB of the second LBS 1 bit and the second coded data of the first coded data. 3 bits on the side, a total of 4 bits, and the third hierarchical data is the MSB of the third code data.
2 bits on the side and 2 bits on the MSB side of the fourth code data, a total of 4 bits, and the fourth hierarchical data is the first LSB 1 bit of the first code data, the 2 bits on the LSB side of the second code data, and the 3rd bit. That is, the hierarchical structure is such that the first LSB is 1 bit of the code data of 4 bits in total. The hierarchical division as described above is also based on the idea that, as in the above-described example, the lower frequency band information and the MSB side information in each band are more important. In other words, since the hierarchical division may be performed in the order of importance of code data, the hierarchical division as described above is not always necessary.

FIG. 5 is a flow chart showing the operation of the write controller 19. FIG. 6 is a diagram showing a state of the data storage area when the memory storage area is in the memory full state for the first time during data recording. In addition, FIG.
It is a figure which shows the content of the auxiliary information at the time of the said data storage area becoming a memory full state for the first time during data recording.

FIG. 8 is a diagram showing the state of the data storage area when the data storage area becomes the memory full state for the second time during data recording. Further, FIG. 9 is a diagram showing the contents of the auxiliary information when the data storage area becomes the memory full state for the second time during data recording.

FIG. 10 is a diagram showing the state of the data storage area at the end of data recording, and FIG. 11 is a diagram showing the contents of auxiliary information at the end of data recording.

The operation of the digital signal recording apparatus of this embodiment constructed as described above will be described below with reference to FIGS. 1 to 11.

In FIG. 1, first, an analog voice input signal is converted by an A / D converter 11 into a 16-bit digital signal. The digital signal is a band divider 12
Is band-divided into four bands from the first band signal to the fourth band signal. At this time, the band division is performed by the QMF filter bank as shown in FIG.

The first quantizer 13 quantizes the first band signal with 6 bits and outputs first code data. The second quantizer 14 quantizes the second band signal with 4 bits and outputs second code data. The third quantizer 15 quantizes the third band signal with 3 bits and outputs third code data. Fourth quantizer 1
6 quantizes the fourth band signal with 3 bits,
The code data of is output.

The hierarchy divider 17 receives the code data of a total of 16 bits of the first to fourth code data, and receives the code data of FIG.
As shown in (4), 4-layer hierarchical data from the first hierarchical data to the fourth hierarchical data of 4 bits each is output.

As shown in FIG. 5, the write controller 19 releases the entire data storage area at the start of recording and writes the hierarchical data generated by the hierarchical divider 17 in the area. In this embodiment, all layers from the first layer data to the fourth layer data are selected and written. The write controller 19 also adds auxiliary information indicating in which area the data of the selected hierarchy is to be written,
Write to the auxiliary information storage area.

FIG. 6 shows a state of the data storage area in which the hierarchical data from the first hierarchical layer to the fourth hierarchical layer is stored and the memory is full as described above. In this embodiment, address 0000 to address 0F
The first layer data is stored up to FF, and the address 10
The second hierarchical data is stored from 00 to the address 1FFF, the third hierarchical data is stored from the address 2000 to the address 2FFF, and the fourth hierarchical data is stored from the address 3000 to the address 3FFF.

FIG. 7 shows the contents of the auxiliary information when the hierarchical data from the first hierarchical layer to the fourth hierarchical layer is stored as described above and the data storage area is in a memory full state. ing. This is because the first hierarchical data is stored from address 0000 to address 0FFF, the second hierarchical data is stored from address 1000 to address 1FFF, and the second hierarchical data is stored from address 2000 to address 2F.
The third layer data is stored up to FF, and the address 30
The contents indicate that the fourth hierarchical data is stored from 00 to address 3FFF.

When the memory is full, the write controller 19 confirms the auxiliary information, selects a specific area of the data storage area, and releases the area, as shown in FIG. The hierarchical data generated by the hierarchical divider 17 is written in the open area. In this embodiment,
The area from the address 2000 to the address 3FFF, which is the area where the third hierarchical data and the fourth hierarchical data are stored, is released, and the hierarchical data generated by the hierarchical divider 17 is written in the opened area. In this embodiment,
Hierarchical data from the first hierarchy to the second hierarchy is selected and written. Further, the write controller 19 writes information indicating in which area the selected hierarchical data is to be written, in the auxiliary information storage area.

FIG. 8 shows a state of the data storage area in which the data of the first to second layers is newly stored and the memory is full as described above. . In this embodiment, the first layer data is stored from address 0000 to address 0FFF, the second layer data is stored from address 1000 to address 1FFF, and the address 2000 to address 2FF.
The first layer data is stored up to F, and the address 300
The second hierarchical data is stored from 0 to address 3FFF.

FIG. 9 shows the auxiliary information when the data of the layers from the first layer to the second layer is newly stored as described above and the data storage area is in the memory full state. It represents the content. This indicates that the first hierarchical data is newly stored from the address 2000 to the address 2FFF and the second hierarchical data is newly stored from the address 3000 to the address 3FFF.

When the memory full state is reached, the write controller 19 confirms the auxiliary information, selects a specific area of the data storage area, releases the area, as shown in FIG. The hierarchical data generated by the hierarchical divider 17 is written in the open area. In this embodiment,
The area from the address 3000 to the address 3FFF is released, and the hierarchical data generated by the hierarchical divider 17 is written in the opened area. In this embodiment, the layer data of the first layer is selected and written. Further, the write controller 19 writes information indicating in which area the selected hierarchical data is to be written, in the auxiliary information storage area.

FIG. 10 shows a state of the data storage area when the first layer data is newly stored as described above and the recording state is completed. Here, the first hierarchical data is stored from address 0000 to address 0FFF, and the address 1000 to address 1FFF is stored.
The second layer data is stored up to the address 2000
To the address 2FFF, the first hierarchical data is stored, and the first data from the address 3000 to the address 3FFF is stored.
The hierarchical data of is stored.

FIG. 11 shows the contents of the auxiliary information when the first hierarchical data is newly stored as described above and the recording state is completed. This has a content indicating that the first hierarchical data is newly stored from address 3000 to address 3FFF.

What is important in the above processing is that the write controller 19 does not write the data of the new time to the area where the first layer data having the highest importance is stored. It means that the first hierarchical data is always written at the time.

As described above, according to this embodiment, an A / D converter for converting an analog voice input signal into a 16-bit digital signal, and M digital signals (M ≧ 1).
, A M band quantizer that receives M band signals divided by the band divider, and quantizes the M band signals by a predetermined number of bits; Upon receiving the total Q-bit quantized code quantized by the quantizer, the number of the quantized codes is N (N> N) by a predetermined method.
1) A hierarchical divider for hierarchically dividing the hierarchy, a data storage area for storing the data hierarchically divided by the hierarchical divider, and an auxiliary information storage area for storing auxiliary information indicating the attribute of the stored data. And a writable area of the solid-state memory are insufficient, among the hierarchical data stored in the solid-state memory, at least the first hierarchical data is held, and a hierarchy of any other hierarchy Free at least part of the data area of the data,
In the storage area corresponding to the released data area, the number of hierarchical data of any number of N or less including at least the first hierarchical data is stored in the data storage area,
A write controller that stores auxiliary information representing the attribute of the stored data in the auxiliary information storage area, and at least every time the data storage area becomes a memory full state, at least the hierarchical data already stored While retaining the first hierarchical data, at least a part of the data area of the hierarchical data of any other hierarchical layer is released, and the released area newly includes at least the first hierarchical data, By storing the hierarchical data of an arbitrary number of layers of N or less, the recording time can be efficiently extended, and moreover, the first hierarchical data, which is the most important encoded data, is always retained. Therefore, it is possible to prevent a large quality deterioration during decoding.

The second embodiment of the present invention will be described below with reference to the drawings. FIG. 12 is a block diagram showing the configuration of a digital signal recording device according to the second embodiment of the present invention. In FIG. 12, reference numeral 21 is A for converting an analog voice input signal into, for example, a 16-bit digital signal.
/ D converter, 22 is a band divider that divides the 16-bit digital signal of the A / D converter 21 into four bands from the first band signal to the fourth band signal, and 28 is hierarchically coded It is a solid-state memory having a data storage area for storing data and an auxiliary information storage area for storing auxiliary information representing an attribute of the stored data, which is similar to that shown in the first embodiment. .

The second embodiment differs from the first embodiment in four points. The first point is that the band signals of the four bands output from the band divider 22 are divided at predetermined time intervals, the power ratio of the signals of the four bands is obtained at each time interval, and the power ratio is determined according to the power ratio. Thus, the adaptive bit allocator 30 for calculating the number of bits for quantizing each band signal is provided. The second point is that the first quantizer 23 quantizes the first band signal with the number of bits allocated to the first band by the adaptive bit allocator 30 and outputs the first code data. The second quantizer 24 quantizes the second band signal with the number of bits allocated to the second band by the adaptive bit allocator 30 and outputs second code data. A quantizer that quantizes the third band signal with the number of bits allocated to the third band by the adaptive bit allocator 30 and outputs third code data. A quantizer that quantizes the fourth band signal with the number of bits allocated to the fourth band by the adaptive bit allocator 30 and outputs fourth code data. The point is that it is a chemical device. The third point is that the layer divider 27 adaptively changes the layer division method according to the number of bits allocated to each band by the adaptive bit allocator 30 while the above-mentioned first to fourth quantizers are used. This is a layer divider that divides the coded data quantized by 4 into four layers. A fourth point is that, when the writable area of the solid-state memory 28 is insufficient, the write controller 29 retains at least the first hierarchical data among the hierarchical data stored in the solid-state memory 28 and retains the other data. At least a part of the data area of the hierarchical data of the arbitrary hierarchy is released, and the storage area corresponding to the released data area has the number of the arbitrary hierarchy of 4 or less including at least the first hierarchy data. This is a write controller for storing hierarchical data, and is also a write controller for writing the number of bits of each band allocated by the adaptive bit allocator 30 in the auxiliary information storage area of the solid-state memory 28.

FIG. 13 shows an adaptive bit allocator 30 for the first bit.
To 5 are allocated to the 4th band
In the case of bits, 6 bits, 2 bits, and 3 bits, the layer divider 27 causes the total 1 of the first to fourth code data.
It shows an example of which bit in the 6-bit code data is applied to which layer. FIG.
The number in each frame in is a number indicating which layer. Bands 1 to 4 shown in FIG. 13 are the lowest frequency bands in band 1, and become higher frequency bands in the order of band 4.

In FIG. 13, the first hierarchical data is 4-bit data of the MSB side of the first code data, which is 4 bits, and the second data.
Layer data is 4 bits in total, that is, the MSB side of the second code data is 4 bits, and the third layer data is the MSB side 2 bits of the third code data and the MSB of the fourth code data.
2 bits on the side, 4 bits in total, 4th layer data,
1 bit of the first LSB of the first code data, 2 bits of the LSB side of the second code data, and the first LS of the fourth code data
The hierarchical structure is such that B1 bit is a total of 4 bit data. The hierarchical division as described above is
It is based on the idea that the information in the lower frequency band and the information on the MSB side in each band are more important. That is, it is only necessary to perform hierarchical division in the order of importance of code data.

However, the hierarchical division as described above is not always necessary. An example of that is shown in FIG.
Is. 14 is similar to that shown in FIG. 13 when the number of bits allocated to the first to fourth bands by the adaptive bit allocator 30 is 5 bits, 6 bits, 2 bits and 3 bits, respectively. Fig. 7 shows another method of layer division, showing an example of which layer of the first to fourth code data the total 16-bit code data is applied to which layer. It is a thing. The numbers in each frame in FIG. 14 are numbers indicating which layer. In FIG. 14, the first hierarchical data is the first
4 bits of MSB side 4 bits of the code data, the second layer data is 3 bits of MSB side of the second code data and 1st LSB 1 bit of the first code data, total 4 bits data, 3rd layer The data is M of the third code data.
SB side 2 bits and second code data 2nd LSB side 3rd
4-bit data of the LSB, the fourth hierarchical data is the second
That is, the first LSB of the code data of 1 and the fourth code data of 3 bits make up a total of 4 bit data, which is a hierarchical structure.

In FIG. 3, when the number of bits allocated to each band is 6 bits, 4 bits, 3 bits, and 3 bits, respectively, the hierarchical divider 17 causes the code of the above-mentioned first to fourth code data to be 16 bits in total. It shows an example of which bit in the data is applied to which hierarchy. The number in each frame in FIG. 3 is a number indicating which layer. Bands 1 to 4 shown in FIG. 3 are the lowest frequency bands in band 1, and become higher frequency bands in the order of band 4. In FIG. 3, the first
Layer data is 4-bit data of 4 bits on the MSB side of the first code data, and the second layer data is the second LBS 1 bit of the first code data and the MSB of the second code data.
3 bits on the side, a total of 4 bits, the third layer data is
The MSB side 2 bits of the third code data and the MSB side 2 bits of the fourth code data, a total of 4 bits data, and the fourth hierarchical data is the first LSB 1 bit of the first code data and the second code data. First LSB 1 bit, first LSB 1 bit of third code data, and first LS of fourth code data
The hierarchical structure is such that B1 bit is a total of 4 bit data. The hierarchical division as described above is
It is based on the idea that the information in the lower frequency band and the information on the MSB side in each band are more important. In other words, since the hierarchical division may be performed in the order of importance of code data, the hierarchical division as described above is not always necessary.

In FIG. 4, when the number of bits assigned to each band is 6 bits, 5 bits, 3 bits, and 2 bits, respectively, the layer divider 17 causes the code of the above-mentioned first to fourth code data to be 16 bits in total. It shows an example of which bit in the data is applied to which hierarchy. The number in each frame in FIG. 4 is a number indicating which layer. In FIG. 4, the first hierarchical data is 4-bit data of 4 bits on the MSB side of the first coded data, and the second hierarchical data is the MSB of the second LBS 1 bit and the second coded data of the first coded data. 3 bits on the side, a total of 4 bits, and the third hierarchical data is the MSB of the third code data.
2 bits on the side and 2 bits on the MSB side of the fourth code data, a total of 4 bits, and the fourth hierarchical data is the first LSB 1 bit of the first code data, the 2 bits on the LSB side of the second code data, and the 3rd bit. That is, the hierarchical structure is such that the first LSB is 1 bit of the code data of 4 bits in total. The hierarchical division as described above is also based on the idea that, as in the above-described example, the lower frequency band information and the MSB side information in each band are more important. In other words, since the hierarchical division may be performed in the order of importance of code data, the hierarchical division as described above is not always necessary.

FIG. 15 shows an example of how the information representing the bit allocation pattern for each predetermined time interval is stored in the auxiliary information storage area.

Regarding the operation of the digital signal recording apparatus configured as described above, the operation will be described with reference to FIGS.
This will be described with reference to FIGS. 14, 15, 3, and 4.

In FIG. 12, first, an analog voice input signal is converted into a 16-bit digital signal by the A / D converter 21. The digital signal is a band divider 2
2 divides the signal into four bands from the first band signal to the fourth band signal. The above processing is the same as that shown in the first embodiment.

Next, the adaptive bit allocator 30 divides the band signals of the four bands output from the band divider 22 into predetermined time intervals and determines the power ratio of the signals of the four bands at each time interval. Then, the number of bits for quantizing each band signal is calculated according to the power ratio. In this embodiment, as a method for adaptively allocating bits, allocation is simply performed according to the power ratio of each band. However, as with MPEG audio encoding, auditory masking characteristics are used. Alternatively, a method using a psychoacoustic model using the method may be used (see ISO / IEC 11172-3: 1993).

Next, the first quantizer 23 quantizes the first band signal with the number of bits allocated to the first band by the adaptive bit allocator 30 and outputs the first code data. , The second quantizer 24 quantizes the second band signal by the number of bits allocated to the second band by the adaptive bit allocator 30, outputs second code data, and outputs the third quantized data. The quantizer 25 quantizes the third band signal with the number of bits allocated to the third band by the adaptive bit allocator 30 to generate a third band signal.
And the fourth quantizer 26 quantizes the fourth band signal with the number of bits allocated to the fourth band by the adaptive bit allocator 30 and outputs the fourth code data. To do.

In the hierarchical divider 27, the adaptive bit allocator 3
The code data quantized by the first to fourth quantizers is hierarchically divided into four hierarchies while adaptively changing the hierarchical division method according to the number of bits assigned to each band of 0.

FIG. 13 shows the adaptive bit allocator 30 with the first
To 5 are allocated to the 4th band
In the case of bits, 6 bits, 2 bits, and 3 bits, the layer divider 27 causes the total 1 of the first to fourth code data.
It shows an example of which bit in the 6-bit code data is applied to which layer. FIG.
The number in each frame in is a number indicating which layer. In FIG. 13, the first hierarchical data is the 4-bit data of the MSB side 4 bits of the first code data, the second hierarchical data is the 4-bit data of the MSB side 4 bits of the second code data, a total of 4 bits. The third hierarchical data is 2 bits on the MSB side of the third code data and 2 bits on the MSB side of the fourth code data, which is a total of 4 bits, and the fourth hierarchical data is the 1st LSB bit of the first code data. L of the second code data
The hierarchical structure is such that 2 bits on the SB side and 1 bit of the first LSB of the fourth code data make a total of 4 bits.

Further, FIG. 3 shows the adaptive bit allocator 30 in the case where the number of bits allocated to the first to fourth bands is 6 bits, 4 bits, 3 bits and 3 bits, respectively. Total 1 of the above-mentioned first to fourth code data
It shows an example of which bit in the 6-bit code data is applied to which layer. The number in each frame in FIG. 3 is a number indicating which layer. In FIG. 3, the first hierarchical data is 4-bit data of 4 bits on the MSB side of the first coded data, and the second hierarchical data is the MSB of the second LBS 1 bit and the second coded data of the first coded data. Side 3 bits total 4 bits data, 3rd hierarchy data, MSB side 2 bits 3rd code data and 4th code data MSB side 2 bits total 4 bits data, 4th hierarchy data, First of the first code data
The LSB 1 bit, the first LSB 1 bit of the second code data, the first LSB 1 bit of the third code data, and the first LSB 1 bit of the fourth code data, that is, a total of 4 bit data, have a hierarchical structure.

Further, FIG. 4 shows the adaptive bit allocator 30 in the case where the number of bits allocated to the first to fourth bands is 6 bits, 5 bits, 3 bits and 2 bits, respectively. Total 1 of the above-mentioned first to fourth code data
It shows an example of which bit in the 6-bit code data is applied to which layer. The number in each frame in FIG. 4 is a number indicating which layer. In FIG. 4, the first hierarchical data is 4-bit data of 4 bits on the MSB side of the first coded data, and the second hierarchical data is the MSB of the second LBS 1 bit and the second coded data of the first coded data. Side 3 bits total 4 bits data, 3rd hierarchy data, MSB side 2 bits 3rd code data and 4th code data MSB side 2 bits total 4 bits data, 4th hierarchy data, First of the first code data
The hierarchical structure is such that LSB 1 bit, 2 bits on the LSB side of the second code data and 1st LSB 1 bit of the third code data, that is, a total of 4 bits data.

As described above, the layer divider 17 changes which bit is assigned to which layer according to the number of bits of each band assigned by the adaptive bit assigner 30. Which bit is assigned to which layer may be determined in advance for each bit pattern assigned as described above, or may be determined sequentially by a predetermined ranking rule.

The write controller 29 stores the hierarchical data output as described above in the solid-state memory 28 together with the auxiliary information. This process is the same as in the first embodiment.
However, this is different from the first embodiment in that the auxiliary information storage area also stores information indicating a bit allocation pattern at each predetermined time interval for calculating the bit allocation amount. FIG. 15 shows an example of a state in which the information indicating the bit allocation pattern for each predetermined time interval is stored in the auxiliary information storage area.

FIG. 15 shows that 6 bits are assigned to the first band, 4 bits to the second band, 3 bits to the third band, and 3 bits to the fourth band in the first time interval. Similarly, in the second time interval, 6 bits are assigned to the first band, 5 bits are assigned to the second band, 3 bits are assigned to the third band, and 2 bits are assigned to the fourth band.
In the time interval, 5 bits are assigned to the first band, 5 bits are assigned to the second band, 3 bits are assigned to the third band, and 3 bits are assigned to the fourth band.

As described above, according to this embodiment, an A / D converter for converting an analog voice input signal into a 16-bit digital signal and M digital signals (M ≧ 1).
A band divider that divides each band signal into a band, and an adaptive bit allocator that adaptively distributes the number of bits for quantizing each band signal to the power distribution or frequency spectrum distribution of each band signal for each predetermined time interval, , M divided by the band divider
M band quantizers for quantizing each of the band signals with the number of bits determined by the adaptive bit allocator, and the M quantizers.
The total Q-bit quantized code quantized by the number of quantizers is received, and the number of quantized codes is N (N> N) according to the bit allocation pattern allocated by the adaptive bit allocator.
1) A hierarchical divider for hierarchically dividing the hierarchy, a data storage area for storing the data hierarchically divided by the hierarchical divider, and an auxiliary information storage area for storing auxiliary information indicating the attribute of the stored data. And a writable area of the solid-state memory are insufficient, among the hierarchical data stored in the solid-state memory, at least the first hierarchical data is held, and a hierarchy of any other hierarchy Free at least part of the data area of the data,
In the storage area corresponding to the released data area, the number of hierarchical data of any number of N or less including at least the first hierarchical data is stored in the data storage area,
A write controller that stores auxiliary information representing the attribute of the stored data in the auxiliary information storage area, and at least every time the data storage area becomes a memory full state, at least the hierarchical data already stored While retaining the first hierarchical data, at least a part of the data area of the hierarchical data of any other hierarchical layer is released, and the released area newly includes at least the first hierarchical data, By storing the hierarchical data of an arbitrary number of layers of N or less, the recording time can be efficiently extended, and moreover, the first hierarchical data, which is the most important encoded data, is always retained. Therefore, it is possible to prevent a large quality deterioration during decoding. Moreover, since the layer division method is changed based on the frequency distribution of the input signal, it is possible to reduce the deterioration of coding quality even when the layer data of the lower layer is lost.

The third embodiment of the present invention will be described below with reference to the drawings. FIG. 16 is a block diagram showing the arrangement of a digital signal recording apparatus according to the third embodiment of the present invention. In FIG. 16, numeral 31 is A for converting an analog voice input signal into, for example, a 16-bit digital signal.
/ D converter, 32 is a band divider that divides the 16-bit digital signal of the A / D converter 31 into four bands from the first band signal to the fourth band signal, and 38 is hierarchically coded Solid-state memory 39 having a data storage area for storing data and an auxiliary-information storage area for storing auxiliary information indicating the attribute of the stored data. Of the hierarchical data stored in, at least the first hierarchical data is held and at least a part of the data area of the hierarchical data of any other hierarchy is released, which corresponds to the opened data area. In the storage area, at least the first
Is a write controller that stores the hierarchical data of an arbitrary number of layers equal to or less than 4 including the hierarchical data of the hierarchical data. , A layer divider that divides the code data quantized by the first to fourth quantizers into four layers while adaptively changing the layer division method.
Is the same as that shown in the embodiment.

The difference between the third embodiment and the second embodiment is that the adaptive bit allocator 40 divides the band signals of four bands output from the band divider 32 into predetermined time intervals,
The ratio of the powers of the signals in the above four bands is calculated for each time interval,
When allocating the number of bits to quantize each band signal in accordance with the power ratio, at least an adaptive bit allocation that allocates a number of bits equal to or more than the number of bits (hereinafter referred to as core bits) previously allocated for each band And a first quantizer 33 quantizes the first band signal with the number of bits allocated to the first band by the adaptive bit allocator 40 and outputs first code data. The vessel, the second
Quantizer 34 is a quantizer that quantizes the second band signal with the number of bits allocated to the second band by adaptive bit allocator 40 and outputs the second code data.
Quantizer 35 is a quantizer that quantizes the third band signal with the number of bits allocated to the third band by adaptive bit allocator 40 and outputs third code data.
Is a quantizer 36 that quantizes the fourth band signal with the number of bits allocated to the fourth band by the adaptive bit allocator 40 and outputs fourth code data. The quantizer of is an embedded-ADPCM quantizer. Embedded-ADP
In the CM method, the coded signal to be fed back to the predictor in the ADPCM method is only the upper bits of a predetermined number of bits, and the other bits are the prediction loop on the encoder side and the prediction loop on the decoder side. However, it is an encoding method that is configured not to be used ("The Institute of Electronics, Information and Communication Engineers Transactions B-
I Vol. J72-BI No.12 pp.1199-1209 December 1989 "). With such a configuration, even if the lower bits are discarded, the prediction signals do not match on the encoder side and the decoder side, so that the deterioration of quality can be reduced. In this embodiment, the above-mentioned Embedded-ADPCM is used.
In the above, the bit to be fed back to the predictor is the core bit.

The operation of the digital signal recording apparatus configured as described above will be described below with reference to FIGS.
This will be described with reference to FIGS. 3 and 4.

In FIG. 16, first, an analog voice input signal is converted into a 16-bit digital signal by the A / D converter 31. The digital signal is a band divider 3
2 divides the signal into four bands from the first band signal to the fourth band signal. The above processing is the same as that shown in the second embodiment.

Next, the adaptive bit allocator 40 divides the band signals of the four bands output from the band divider 32 into predetermined time intervals and determines the power ratio of the signals of the four bands at each time interval. Then, the number of bits for quantizing each band signal is assigned according to the ratio of the powers. At this time, at least a number of bits equal to or more than the number of bits pre-assigned for each band (hereinafter referred to as core bits) assign. In this embodiment, the core bits of the first band are 4 bits, the core bits of the second band are 3 bits, the core bits of the third band are 2 bits, and the core bits of the fourth band are 2 bits.

Next, the first quantizer 33 quantizes the first band signal by the Embedded ADPCM with the number of bits allocated to the first band by the adaptive bit allocator 40, and outputs the first code data. The second quantizer 34 outputs the second band signal with the number of bits allocated to the second band by the adaptive bit allocator 40 as Embedded-
The second coded data is quantized by the ADPCM, and the second coded data is output. And outputs the third code data, and the fourth quantizer 36 quantizes the fourth band signal by the embedded-ADPCM with the number of bits allocated to the fourth band by the adaptive bit allocator 40. And outputs the fourth code data. At this time, the number of bits used in the prediction loop in the Embedded-ADPCM of each band is the core bit.

In the hierarchical divider 37, the adaptive bit assigner 4
The code data quantized by the first to fourth quantizers is hierarchically divided into four hierarchies while adaptively changing the hierarchical division method according to the number of bits assigned to each band of 0.

FIG. 13 shows the adaptive bit allocator 30 with the first
To 5 are allocated to the 4th band
In the case of bits, 6 bits, 2 bits, and 3 bits, the layer divider 27 causes the total 1 of the first to fourth code data.
It shows an example of which bit in the 6-bit code data is applied to which layer. FIG.
The number in each frame in is a number indicating which layer. Bands 1 to 4 shown in FIG. 13 are the lowest frequency bands in band 1, and become higher frequency bands in the order of band 4.

In FIG. 13, the first hierarchical data is the 4-bit data of the MSB side 4 bits of the first code data, and the second hierarchical data.
Layer data is 4 bits in total, that is, the MSB side of the second code data is 4 bits, and the third layer data is the MSB side 2 bits of the third code data and the MSB of the fourth code data.
2 bits on the side, 4 bits in total, 4th layer data,
1 bit of the first LSB of the first code data, 2 bits of the LSB side of the second code data, and the first LS of the fourth code data
The hierarchical structure is such that B1 bit is a total of 4 bit data. It should be noted here that the core bits of each band must be divided so that each band has the same layer.
For example, referring to FIG. 13, the core bits 4 bits of the first band are all in the first layer, and the core bits 3 of the second band are 3 bits.
All bits are in the second layer, core bit 2 bits in the third band are all in the third layer, and core bit 2 bits in the fourth band are all in the third layer. In this way, even if the specific lower layer data is lost, the prediction signals do not match on the encoder side and the decoder side, and the deterioration of quality can be reduced.

FIG. 3 is a block diagram of the adaptive bit allocator 30 in the case where the number of bits allocated to the first to fourth bands is 6 bits, 4 bits, 3 bits and 3 bits, respectively. Total 1 of the above-mentioned first to fourth code data
It shows an example of which bit in the 6-bit code data is applied to which layer. The number in each frame in FIG. 3 is a number indicating which layer. In FIG. 3, the first hierarchical data is 4-bit data of 4 bits on the MSB side of the first coded data, and the second hierarchical data is the MSB of the second LSB 1 bit and the second coded data of the first coded data. Side 3 bits total 4 bits data, 3rd hierarchy data, MSB side 2 bits 3rd code data and 4th code data MSB side 2 bits total 4 bits data, 4th hierarchy data, First of the first code data
The LSB 1 bit, the first LSB 1 bit of the second code data, the first LSB 1 bit of the third code data, and the first LSB 1 bit of the fourth code data, that is, a total of 4 bit data, have a hierarchical structure. By doing this, even if the specific lower layer data is lost, the prediction signals do not mismatch on the encoder side and the decoder side.
The deterioration of quality can be reduced.

FIG. 4 is a block diagram of the adaptive bit allocator 30 in the case where the number of bits allocated to the first to fourth bands is 6 bits, 5 bits, 3 bits and 2 bits, respectively. Total 1 of the above-mentioned first to fourth code data
It shows an example of which bit in the 6-bit code data is applied to which layer. The number in each frame in FIG. 4 is a number indicating which layer. In FIG. 4, the first hierarchical data is 4-bit data of 4 bits on the MSB side of the first coded data, and the second hierarchical data is the MSB of the second LBS 1 bit and the second coded data of the first coded data. Side 3 bits total 4 bits data, 3rd hierarchy data, MSB side 2 bits 3rd code data and 4th code data MSB side 2 bits total 4 bits data, 4th hierarchy data, First of the first code data
The hierarchical structure is such that LSB 1 bit, 2 bits on the LSB side of the second code data and 1st LSB 1 bit of the third code data, that is, a total of 4 bits data. In this way, even if the specific lower layer data is lost, the prediction signals do not match on the encoder side and the decoder side, and the deterioration of quality can be reduced.

As described above, the layer divider 17 changes which bit is assigned to which layer according to the number of bits of each band assigned by the adaptive bit assigner 30. Which bit is assigned to which layer may be determined in advance for each bit pattern assigned as described above, or may be determined sequentially by a predetermined ranking rule.

The write controller 29 stores the hierarchical data output as described above in the solid-state memory 28 together with the auxiliary information. This process is the same as in the second embodiment.

As described above, according to this embodiment, an A / D converter for converting an analog voice input signal into a 16-bit digital signal, and M digital signals (M ≧ 1).
A band divider that divides each band signal into a band, and an adaptive bit allocator that adaptively distributes the number of bits for quantizing each band signal to the power distribution or frequency spectrum distribution of each band signal for each predetermined time interval, , M divided by the band divider
M band quantizers for quantizing each of the band signals with the number of bits determined by the adaptive bit allocator, and the M quantizers.
The total Q-bit quantized code quantized by the number of quantizers is received, and the number of quantized codes is N (N> N) according to the bit allocation pattern allocated by the adaptive bit allocator.
1) A hierarchical divider for hierarchically dividing the hierarchy, a data storage area for storing the data hierarchically divided by the hierarchical divider, and an auxiliary information storage area for storing auxiliary information indicating the attribute of the stored data. And a writable area of the solid-state memory are insufficient, among the hierarchical data stored in the solid-state memory, at least the first hierarchical data is held, and a hierarchy of any other hierarchy Free at least part of the data area of the data,
In the storage area corresponding to the released data area, the number of hierarchical data of any number of N or less including at least the first hierarchical data is stored in the data storage area,
A write controller for storing auxiliary information representing the attribute of the stored data in the auxiliary information storage area, wherein the adaptive bit allocator has a bit number equal to or more than a predetermined bit number (core bit) for each band. Is used as an adaptive bit allocator, and the quantizer of each band uses an embedded-ADP that uses only the core bits in the prediction loop.
Each time the data storage area becomes a memory full state as a CM, at least one of the hierarchical data of any other hierarchical layers is retained while at least the first hierarchical data among the already stored hierarchical data is held. The recording area can be efficiently recorded by releasing the data area of a part and newly storing in the released area the layer data of N or less arbitrary layers including at least the first layer data. Extensions can be made. Moreover, since the first layer data, which is the most important encoded data, is always held, a large deterioration in quality can be prevented when decoding, and the quantizer for each band is It is an Embedded-ADPCM that is resistant to discarding lower layer data, and since the layer division method is changed based on the frequency distribution of the input signal, deterioration of coding quality is reduced even if layer data of the lower layer is lost. be able to.

The fourth embodiment of the present invention will be described below with reference to the drawings. FIG. 17 is a block diagram showing the arrangement of a digital signal recording apparatus according to the fourth embodiment of the present invention. In FIG. 17, reference numeral 41 is A for converting an analog voice input signal into, for example, a 16-bit digital signal.
The / D converter 45 is a solid-state memory having a data storage area for storing hierarchically encoded data and an auxiliary information storage area for storing auxiliary information representing the attribute of the stored data. It is similar to that shown in the embodiment.

The fourth embodiment differs from the first embodiment in that, in the first embodiment, the encoding unit for generating the code data to be the input of the hierarchical divider is the band divider and the first divider. While the first to fourth quantizers are used, in the present embodiment, the encoding unit that generates the code data that is the input of the hierarchical divider uses Np as the driving sound source of the synthesizer in the analysis and synthesis system. The point that the multi-pulse encoder 42 is represented by a pulse of a book, and the write controller 44 has the same function as that shown in the first embodiment, and also the output from the multi-pulse encoder 42. A write controller for storing the coefficient of the LPC synthesis filter to be stored in the auxiliary information storage area,
The layer divider 43 outputs at least one of the Np pulses.
This is a point in the hierarchy divider that divides each book into N groups or more and makes each group N hierarchy data.

The multi-pulse coding system is a system in which a driving sound source of a synthesizer in an analysis-synthesis system is expressed by a plurality of pulses and a decoded sound is generated by driving an LPC synthesis filter. This is a compression coding system capable of performing compression coding of voice at a lower bit rate than the compression coding system based on subband coding shown in the examples to the third embodiment ("Digital Signals," edited by the Institute of Electronics, Information and Communication Engineers, Japan). Processing Handbook pp.343 1993 ", or Ozawa et al.," Study on Multi-pulse Driven Speech Coding ", IEICE Communication Systems Study Group Material CS82-161, 1992-3).

FIG. 18 shows the input and output of the multi-pulse encoder 42, and shows how the input speech data is compression-encoded into the coefficients of the LPC synthesis filter and eight pulses at a predetermined time interval. It represents.

FIG. 19 shows how the layer divider 43 divides the eight pulses of the multi-pulse encoder 42 shown in FIG. 18 into groups of two pulses into four layers of data. ing.

Regarding the operation of the digital signal recording apparatus configured as described above, the operation will be described below with reference to FIGS.
This will be described with reference to FIG.

In FIG. 17, first, an analog voice input signal is converted into a 16-bit digital signal by the A / D converter 41. The digital signal is shown in FIG.
As shown in FIG. 8, the multi-pulse encoder 42 divides the signal into predetermined time intervals and encodes into 8 pulses with the coefficient of the LPC synthesis filter at each time interval. As shown in FIG. 19, the eight pulses are grouped into two by the hierarchical divider 43 and divided into four hierarchical data.

In this embodiment, the first hierarchical data is data obtained by encoding the position and amplitude of the pulse with the largest amplitude and the pulse with the second largest amplitude, and the second hierarchical data is the third amplitude. Of the pulse having the largest amplitude and the pulse having the fourth largest amplitude and the encoded data, and the third hierarchical data encodes the position and the amplitude of the pulse having the fifth largest amplitude and the pulse having the sixth largest amplitude. The fourth hierarchical data is the pulse data with the smallest amplitude and 2
The position and amplitude of the pulse with the second smallest amplitude are encoded data.

Here, the method of layer division is not performed as described above, the first layer data is data obtained by encoding the positions and amplitudes of the first and fifth pulses, and the second layer data is The second and sixth pulse positions and amplitudes are encoded data, the third hierarchical data is the third and seventh pulse position and amplitude encoded data, and the fourth hierarchical data is The position and amplitude of the fourth pulse and the eighth pulse may be coded data, or may be determined simply by the order of the positions or by combining them.

The write controller 44 stores the hierarchical data output as described above in the solid-state memory 45 together with the auxiliary information. This process is the same as that of the first embodiment.
However, the write controller 44 also stores the coefficient of the LPC synthesis filter output from the multi-pulse encoder 42 as auxiliary information in the auxiliary information storage area in the solid-state memory.

As described above, according to this embodiment, the A / D converter for converting an analog voice input signal into a 16-bit digital signal and the driving sound source of the combiner in the analysis and synthesis system are Np pulses. And a multi-pulse encoder represented by, and at least one of the Np pulses
A hierarchical divider that divides each group into N hierarchical data, a data storage area that stores hierarchically encoded data, and auxiliary information that represents an attribute of the stored data. When a storage device having a storage area for storing auxiliary information and a writable area of the storage device are insufficient, at least the first hierarchical data among the hierarchical data stored in the storage device is held,
At least a part of the data area of the hierarchy data of any other hierarchy other than that is released, and N or less arbitrary hierarchy including at least the first hierarchy data in the storage area corresponding to the released data area. And a write controller for storing the auxiliary data representing the attribute of the stored data in the auxiliary information storage area, and outputting the composite data output from the multipulse encoder. The filter coefficient of the container is stored in the auxiliary information storage area, and each time the data storage area becomes full of memory, at least the first hierarchical data among the already stored hierarchical data is retained, Other than at least a part of the hierarchical data of the hierarchical data is released, and the released area newly includes at least the first hierarchical data, By storing the hierarchical data of an arbitrary number of layers or less, the recording time can be efficiently extended, and the most important encoded data, the first hierarchical data, is always retained. Therefore, it is possible to prevent a large deterioration in quality when decoding. Moreover, since the multi-pulse coding method is used, the above-mentioned can be performed at a low bit rate.

The fifth embodiment of the present invention will be described below with reference to the drawings. FIG. 20 (a) shows the claim 1.
To a data storage area of a solid-state memory (storage device) in which hierarchical data hierarchically encoded by the hierarchical encoder constituting the digital signal reproducing apparatus according to claim 7 is stored. In this embodiment, the number of layers divided by the layer divider is two.
Is shown. The data storage area comprises a first data storage area from address A to address B. The write controller writes hierarchical data in the data storage area according to the following procedure.

First, from time t1, the first hierarchical data is stored from the address A to the address B, and the second hierarchical data is stored from the address B to the address A. As shown in FIG. 20B, when the entire hierarchical data storage area is full at time t2, when data is written at the next time, the area to which the second hierarchical data is to be written is Since the first hierarchical data, which is higher than the hierarchical data, has already been written, the writing of the second hierarchical data is stopped. On the other hand, since the second hierarchical data lower than the hierarchical order is written in the area where the first hierarchical data is to be written, the second hierarchical data is continuously stored in the area in which the second hierarchical data was written. ..

As a result, when recording in a limited data area, even after the data area is full, the writing of the lower layer data is stopped, and the upper layer data that has already been written is sequentially recorded in the upper layer. The recording time can be automatically extended by continuing the writing process of the data of the layer.
Furthermore, when the recording time is short, high quality recording is possible, and the limited data area can be effectively utilized.

Although the number of layers is two in this embodiment, the number of layers is not limited to two as long as write control is performed based on the above rule. Further, it is not necessary to determine the capacity of the data writing area in which each hierarchical data is written in advance. Furthermore, each hierarchical data need not be equal-length code.

The sixth embodiment of the present invention will be described below with reference to the drawings. FIG. 21 (a) shows the claim 1.
To a data storage area of a solid-state memory (storage device) in which hierarchical data hierarchically encoded by the hierarchical encoder constituting the digital signal reproducing apparatus according to claim 7 is stored. In this embodiment, the number of layers divided by the layer divider is two.
Is shown. The bit rate of the first layer data is a [bps], and the bit rate of the second layer data is b.
[Bps]. The data storage area is from address A to address B, and the capacity is D. Address A ′ at which the writing process of each hierarchical data is stopped first
The address is set in advance. Here, assuming that the recordable time when storing all hierarchical data is t, the capacity D of the recordable data storage area is represented by Expression (1).

D = a × t + b × t (1) The capacity of the data storage area from the address A to the address A ′ is a × t, and the data storage from the address A ′ to the address B is stored. The address A ′ is calculated in advance so that the capacity of the area is b × t. The write controller writes hierarchical data in the data storage area according to the following procedure.

The first hierarchical data is sequentially stored from the address A to the address B, and the second hierarchical data is sequentially stored from the address B to the address A.
After t, the write addresses of the first hierarchical data and the second hierarchical data reach the address A ′. Since the address A'is a write process stop address calculated in advance for the second layer data, the write process of the second layer data is stopped. Even if the write address of the first hierarchical data reaches the address A ′, the area for writing the first hierarchical data at the next time stores the second hierarchical data which is a lower hierarchical layer than the hierarchical order. Since it is a data area, the first hierarchical data is continuously stored in the direction of address B.

By thus calculating the address for stopping the writing process of each hierarchical data in advance, the rule for storing each hierarchical data can be freely set. As a result, when the write address of each hierarchical data reaches the address calculated in advance, the writing process of the lower hierarchical data is stopped, and only the upper hierarchical data is stored in the data storage area in which the lower hierarchical data is stored. Can be recorded for a long period of time by continuously storing, and high-quality recording can be performed when recording for a short time, and the limited data area can be effectively used.

The writing direction of each second hierarchical data is not particularly limited. Furthermore, each hierarchical data need not be equal-length code.

The seventh embodiment of the present invention will be described below. FIG. 22A shows the data storage area in this embodiment. The data storage area is a data storage area having a capacity D of a solid-state memory (storage device) in which hierarchical data hierarchically encoded by the hierarchical encoder constituting the digital signal reproducing apparatus according to claim 1 is stored. And address A
From the address to the address B. In this embodiment, the case where the number of layers divided by the layer divider is 2 is shown. The data storage area includes a data write prohibition area of the capacity D1. First, the addresses A'and B'of the data write prohibited area are set. It is assumed that the bit rate of the first layer data is a [bps] and the bit rate of the second layer data is b [bps]. Assuming that the recordable time when storing all hierarchical data is t, the capacity D-D1 of the recordable data storage area is represented by the equation (2).

D−D1 = a × t + b × t (2) The capacity of the data storage area from the address A to the address A ′ is a × t, and the data from the address B ′ to the address B is data. Address A'address and address B'address are calculated in advance so that the capacity of the storage area 113 is b × t. The write controller writes hierarchical data in the data area according to the following procedure.

The first layer data is from address A to address B, and the second layer data is address B.
The data is stored in the direction from the address to the address A. At time t after the start of recording, the write address of the first layer data reaches the address A ′ and the write address of the second layer data reaches the address B ′. At the next time, the first
Since the second layer data lower than the layer rank is stored in the data area in which the layer data is to be written, the write address of the first layer data is skipped in the write protected area and the address B'address is written. And continues to store data in the direction from address B'to address B. On the other hand, in the area where the second layer data is to be written, the first layer data higher than the layer order is already stored, so the writing is stopped.

As a result, when recording in a limited data area, even after the data area is full, the writing of the lower layer data is stopped and the already written lower layer data is sequentially overwritten. The recording time can be automatically extended by continuing to record the upper layer data. When the recording time is short, high quality recording is possible, and when the recording time is extended, high quality recording can be performed at the beginning of the data, so that the limited data area can be effectively utilized.

The data write prohibition area may not be provided, and each hierarchical data need not be an equal length code.

The eighth embodiment of the present invention will be described below. FIG. 23A shows the data storage area in this embodiment. The data storage area is a data storage area of a capacity D of a storage device in which hierarchical data that is hierarchically encoded by the hierarchical encoder that constitutes the digital signal reproducing apparatus according to claim 1 is stored. From the address to the address B. In this embodiment, the case where the number of layers divided by the layer divider is 2 is shown. The data storage area includes a data write prohibition area of the capacity D1. First
Addresses A'and B'of the data write prohibited area are set. The bit rate of the first layer data is a
[Bps], the bit rate of the second hierarchical data is b [b
ps]. Assuming that the recordable time when storing all hierarchical data is t, the capacity D-D1 of the recordable data storage area is represented by Expression (3).

D−D1 = a × t + b × t (3) The capacity of the data storage area from the address A to the address A ′ is a × t, and the data from the address B ′ to the address B is data. The address A ′ address and the address B ′ address are calculated in advance so that the capacity of the storage area is b × t. The write controller writes hierarchical data in the data area according to the following procedure.

The first hierarchical data is stored in the direction from address A to address B. The second layer data is stored in the direction from the address B ′ to the address B, and a rule is preliminarily set to stop writing when the write address of the second layer data reaches the address B.

At t after recording is started, the write address of the first hierarchical data reaches the address A'and the second data write address reaches the address B. At the next time, the second layer data reaches the write processing stop address B, so the write is stopped. Since the area in which the first hierarchical data is to be written stores the second hierarchical data, which is a hierarchical rank lower than the hierarchical rank,
The writing process of the hierarchical data is continued.

As a result, when the write address of the lower layer data reaches the preset address, the writing process is stopped and the upper layer data is stored in the lower layer data area where the data has already been written. By continuing the recording only in the upper layer, the recording time can be extended automatically. When recording for a long period of time, the end of the data is of high quality, and when recording for a short period of time, all the data can be recorded with high quality, and the limited data area can be effectively utilized.

The writing direction of the second hierarchical data is not particularly limited. Further, the write-protected area may not be provided, or a plurality of write-protected areas may be present.

The ninth embodiment of the present invention will be described below. FIG. 24A shows a data storage area in this embodiment. The data storage area consists of a first data storage area from address A to address B and a second data storage area from address C to address D. Information on addresses A, B, C, D and writing time is stored in the auxiliary information storage area (not shown). The write controller writes hierarchical data in the data storage area according to the following procedure.

The first hierarchical data is stored in the direction from address A to address B. When the address B is reached, the data is stored next from the address D to the address C. The second layer data is address C
The data is stored in the direction from the address to the address D. Also,
The third hierarchical data is stored alternately in the direction from address B to address A and from address D to address C as shown in the figure. Also, the second
For each of the third hierarchies, a rule is set to stop the writing when the data of the upper hierarchy is already written in the area to be written next.

Now, assuming that the entire data area is filled with the first to third hierarchical data, the writing of the third hierarchical data is stopped at the time of writing the next data.
As shown in (b), the first to second hierarchical data are the third hierarchical data.
It is written in the area where the hierarchical data was written.

Further, assuming that the entire data area is filled with the first and second hierarchical data, the writing of the second hierarchical data is stopped at the time of writing the next data.
As shown in (c), the data of the first layer is written from the address D to the address C in the area where the data of the second layer was written. Finally Figure 2
As shown in 4 (d), when the entire data area is filled with the first hierarchical data, the writing is completed.

As a result, even when recording for a long time, it is possible to continue recording with only the data of the upper layer while discarding the data of the lower layer in sequence, and it is possible to obtain high quality when recording for a short time. Recording is possible and the limited data area can be effectively used.

If a rule is set such that the writing of the third hierarchical data is stopped when the entire data area is full, the writing direction of the third hierarchical data is not particularly limited, and When the number of bits assigned to each layer is fixed, the data storage area for writing each layer data may be determined in advance, and it is not necessary to provide a rule for stopping the writing of the lower layer provided in this embodiment. ..

The tenth embodiment of the present invention will be described below. FIG. 25A shows a data storage area in this embodiment. The data storage area comprises a first address space from address A to address B and a second address space from address C to address D. The write controller writes hierarchical data in the data storage area according to the following procedure.

The first hierarchical data is stored in the direction from address A to address B. When the address B is reached, the data is stored next from the address D to the address C. The second layer data is address C
The data is stored in the direction from the address to the address D. Also,
The third hierarchical data is alternately stored in the data area between the address B and the address A ′ and between the address D and the address C ′. Here, the addresses A'and C'are preset between the address A and the address B, and between the address C and the address D, respectively.

Now, assuming that the data area for storing the third layer is full, the writing of the data of the third layer is stopped when the next data is written, and as shown in FIG. The first to second hierarchical data are written in the area where the third hierarchical data was written.

Further, assuming that the entire data area is filled with the first and second hierarchical data, the writing of the second hierarchical data is stopped when the next data is written.
As shown in (c), the data of the first layer is written in the area where the data of the second layer was written. Finally, the entire data area is first as shown in FIG.
When the layer data of is full, writing is completed.

In this embodiment, the case where the bit lengths of the respective layers are equal has been shown, but this is not always necessary. For example, the first layer is 4 bits, the second layer is 2 bits, and the third layer is
When the hierarchy is 4 bits, as shown in FIG. 25 (e), the data area of the first hierarchy and the data area of the second hierarchy are different in size. In this case, when the data of the third layer is alternately stored in the data area between the address B and the address A ′ and between the address D and the address C ′ as described above, the empty area becomes Will occur. In this case, as shown in FIG. 25 (e), the data is stored from the address A'to the address B, and when the address B is reached, the data is stored from the address D to the address C '. Just go. Of course, the writing direction of the third hierarchical data is not particularly limited.

As a result, even when recording for a long time, it is possible to continue recording with only the data of the upper layer while discarding the data of the lower layer in sequence, and it is possible to obtain high quality when recording for a short time. Recording is possible and the limited data area can be effectively used.

The eleventh embodiment of the present invention will be described below. FIG. 26A shows a data storage area in this embodiment. The data storage area consists of a first data storage area from address A to address B and a second data storage area from address C to address D. The write controller writes hierarchical data in the data storage area according to the following procedure.

The first hierarchical data is stored in the direction from address A to address B. When the address B is reached, the data is stored next from the address D to the address C. The second layer data is address C
The data is stored in the direction from the address to the address D. Also,
The third hierarchical data is alternately stored in the direction from address B to address A and from address D to address C. Further, the fourth hierarchical data is alternately stored in the direction from the address A'to the address A and from the address C'to the address C.

Here, the addresses A'and C'are preset between the address A and the address B, and between the address C and the address D, respectively. Also, the second to the fourth
For each of the layers, a rule is set to stop the writing when the data of the upper layer is already written in the area to be written next.

Now, assuming that the entire data area is filled with the data of the first to fourth layers, the writing of the data of the fourth layer is stopped when writing the next data.
As shown in (b), the first to third hierarchical data are the fourth
It is written in the area where the hierarchical data was written.

Next, assuming that the entire data area is filled with the data of the first to third layers, the writing of the data of the third layer is stopped when writing the next data.
As shown in (c), the first and second hierarchical data are the third hierarchical data.
It is written in the area where the hierarchical data was written.

Further, assuming that the entire data area is filled with the first and second hierarchical data, the writing of the second hierarchical data is stopped when the next data is written.
As shown in (d), the data of the first layer is written from the address D to the address C in the area where the data of the second layer was written. Finally Figure 2
As shown in 6 (e), when the entire data area is filled with the first hierarchical data, the writing is completed.

As a result, even when recording for a long time, it is possible to continue recording with only the data of the upper layer while discarding the data of the lower layer in sequence, and it is possible to obtain high quality when recording for a short time. Recording is possible and the limited data area can be effectively used.

Note that the writing direction of the fourth hierarchical data is not particularly limited, and when the number of bits assigned to each hierarchical layer is fixed, the data storage area in which each hierarchical data is written is set in advance. It suffices to make a decision, and it is not necessary to provide a rule for stopping writing in the lower hierarchy provided in this embodiment.

The twelfth embodiment of the present invention will be described below. FIG. 27A shows a data storage area in this embodiment. The data storage area comprises a first address space from address A to address B and a second address space from address C to address D. The write controller writes hierarchical data in the data storage area according to the following procedure.

The first hierarchical data is stored in the direction from address A to address B. When the address B is reached, the data is stored next from the address D to the address C. The second layer data is address C
The data is stored in the direction from the address to the address D. Also,
The third hierarchical data is alternately stored in the data areas from the address B to the address A "and from the address D to the address C". Here, the addresses A ″ and C ″ are preset between the address A and the address B, and between the address C and the address D, respectively. Further, the fourth hierarchical data is alternately stored in the data area between the address A'and the address B'and between the address C'and the address D '.

Here, the addresses A'and C'are preset between the address A and the address A "and between the address C and the address C", respectively, and the addresses B'and D'are the addresses respectively. A "address and address B
It is preset between the address, the address C ″ and the address D.

Now, assuming that the data area for storing the fourth layer is full, the writing of the data of the fourth layer is stopped when the next data is written, and as shown in FIG. The first to third hierarchical data are written in the area where the fourth hierarchical data was written.

Next, assuming that the data area for storing the third layer is full, the third data is written when the next data is written.
The writing of the hierarchical data is stopped, and as shown in FIG. 27C, the first and second hierarchical data are written in the area where the third hierarchical data was written.

Further, assuming that the entire data area is filled with the first and second hierarchical data, the writing of the second hierarchical data is stopped when the next data is written, and FIG.
As shown in (d), the data of the first layer is written in the area where the data of the second layer was written. Finally, as shown in FIG. 27 (e), the entire data area is first
When the layer data of is full, writing is completed.

As a result, even when recording for a long time, it is possible to continue recording with only the data of the upper layer while discarding the data of the lower layer one after another, and it is possible to obtain high quality when recording for a short time. Recording is possible and the limited data area can be effectively used.

The writing direction of the fourth hierarchical data is not particularly limited.

The thirteenth embodiment of the present invention will be described below. FIG. 28A shows a data storage area in this embodiment. The data storage area is a first data storage area from address A to address B, a second data storage area space from address C to address D, and a third data storage area from address E to address F. Data storage area. The write controller writes hierarchical data in the data storage area according to the following procedure.

The first hierarchical data is stored in the direction from address A to address B. Also, address B
When the address is reached, the data is stored in the direction from address D to address C. Further, when the address C is reached, the data is stored in the direction from the address E to the address F.
The second hierarchical data is stored in the direction from address E to address F. When the address F is reached, the data is stored in the direction from the address C to the address D. The third layer data is from address C to address D
Store in the direction of the address. The fourth hierarchical data is stored alternately in the direction from address B to address A, in the direction from address D to address C, and from the address F to address E. Further, the fifth hierarchical data is stored alternately in the direction from address B'to address A, from address D'to address C, and from address F'to address E.

The addresses B ', D', and F'are preset between the address A and the address B, the address C and the address D, and the address E and the address F, respectively. Further, for each of the second to fifth layers, a rule is set to stop the writing when the data of the upper layer is already written in the area to be written next.

Now, assuming that the entire data area is filled with the data of the first to fifth layers, the writing of the data of the fifth layer is stopped when writing the next data.
As shown in (b), the first to fourth hierarchical data are the fifth hierarchical data.
It is written in the area where the hierarchical data was written.

Next, assuming that the entire data area is filled with the data of the first to fourth layers, the writing of the data of the fourth layer is stopped when writing the next data.
As shown in (c), the first to third hierarchical data are the fourth hierarchical data.
It is written in the area where the hierarchical data was written.

Further, assuming that the entire data area is filled with the first to third hierarchical data, the writing of the third hierarchical data is stopped when the next data is written, and the data of FIG.
As shown in (d), the first and second hierarchical data are the third
It is written in the area where the hierarchical data was written. Finally, assuming that the entire data area is filled with the first and second hierarchical data, the writing of the second hierarchical data is stopped when writing the next data, as shown in FIG. , The data of the first layer is written in the area where the data of the second layer was written.

As a result, even when recording for a long time, it is possible to continue recording with only the data of the upper layer while discarding the data of the lower layer in sequence, and it is possible to obtain high quality when recording for a short time. Recording is possible and the limited data area can be effectively used.

The writing direction of the fifth layer data is not particularly limited, and when the number of bits assigned to each layer is fixed, the data storage area in which each layer data is written is previously set. It suffices to make a decision, and it is not necessary to provide a rule for stopping writing in the lower hierarchy provided in this embodiment.

The fourteenth embodiment of the present invention will be described below. FIG. 29A shows a data storage area in this embodiment. The data storage area is a first data storage area from address A to address B, a second data storage area from address C to address D,
It comprises a third data storage area from address E to address F. The write controller writes hierarchical data in the data storage area according to the following procedure.

The first hierarchical data is stored in the direction from address A to address B. Also, address B
When the address is reached, the data is stored in the direction from address D to address C. Further, when the address C is reached, the data is stored in the direction from the address E to the address F.
The second hierarchical data is stored in the direction from address E to address F. When the address F is reached, the data is stored in the direction from the address C to the address D. The third layer data is from address C to address D
Store in the direction of the address. The fourth hierarchical data is alternately stored between the address B and the address A ", between the address D and the address C", and between the address F and the address E ". The addresses A ″, C ″, and E ″ are preset between the address A and the address B, the address C and the address D, and the address E and the address F, respectively.

Further, the fifth hierarchical data is alternated between the address A'and the address B ', between the address C'and the address D', and between the address E'and the address F '. It will be stored in.

Here, the addresses A ', C', and E'are preset between the address A and the address A ", the address C and the address C", and the address E and the address E ", respectively. And address B ', D',
F'is preset between the address A "and the address B, the address C" and the address D, and the address E "and the address F, respectively.

Assuming now that the data area for storing the fifth layer is full, the writing of the data of the fifth layer is stopped when writing the next data, and as shown in FIG. The first to fourth layer data are written in the area where the fifth layer data was written.

Next, assuming that the data area for storing the fourth hierarchy is full, the next data is written in the fourth area.
The writing of the hierarchical data is stopped, and as shown in FIG. 29C, the first to third hierarchical data are written in the area where the fourth hierarchical data was written.

Next, assuming that the data area for storing the third layer is full, the third data is written when the next data is written.
The writing of the hierarchical data is stopped, and as shown in FIG. 29D, the first to second hierarchical data are written in the area where the third hierarchical data was written.

Further, assuming that the entire data area is filled with the first and second hierarchical data, the writing of the second hierarchical data is stopped when the next data is written.
As shown in (e), the data of the first layer is written in the area where the data of the second layer was written.

As a result, even in the case of recording for a long time, it is possible to continue the recording only by the data of the upper layer while discarding the data of the lower layer one by one, and at the same time, when recording for a short time, high quality is achieved. Recording is possible and the limited data area can be effectively used.

The writing directions of the fourth and fifth hierarchical data are not particularly limited.

A digital signal recording apparatus according to the fifteenth embodiment of the present invention will be described below with reference to the drawings.

FIG. 30 is a block diagram showing the structure of a digital signal recording device according to the fifteenth embodiment of the present invention.
In FIG. 30, reference numeral 300 denotes a layer encoder that encodes a digital signal from the first layer data to the maximum Nth layer data, and 301 denotes the first layer data of the layer encoder 300. A write controller 302 receives the maximum Nth hierarchical data and controls writing to the solid-state memory, and 302 receives the hierarchical data and auxiliary information data from the write controller 301 and stores the data. It is a solid-state memory. FIG. 31 is a flow chart showing the operation flow of the write controller.

Regarding the operation of the digital signal recording apparatus configured as described above, the operation will be described below with reference to FIGS. 30 and 31.
Will be explained.

In FIG. 30, first, the input digital signal is encoded by the hierarchical encoder 300 from the first hierarchical data to the maximum Nth hierarchical data, and the write controller 3
Sent to 01. The write controller 301 receives the maximum Nth hierarchical data from the first hierarchical data and controls the writing to the solid-state memory 302 as shown in the first to fourteenth embodiments. Here, the difference from the first to fourteenth embodiments is that instead of storing all the N hierarchical data output from the hierarchical encoder 300 in the solid-state memory 302, the N hierarchical data are not stored. N'of the data (N '≤
If the original digital signal can be accurately decoded by the N) hierarchical data, the hierarchical data other than the N ′ hierarchical data is not written in the solid-state memory 302.

A more detailed description will be given with reference to the flowchart of FIG. In step 310, N'is initialized to zero. In step 311, N ′ is incremented by 1, and in step 312 it is determined whether the value of N ′ is less than N.
If the value of N ′ is less than N, the upper N ′ hierarchical data is selected from the N hierarchical data in step 313, and the N ′ hierarchical data is selected in step 314. In step 315, the degree of coincidence between the two is compared with the original digital signal, and if the degree of coincidence is larger than a preset value, in step 316, the N ′ hierarchical data items are compared. Are stored in the solid-state memory 302. If step 315
If the degree of coincidence is smaller than the preset value, the process returns to step 311, and the above steps are repeated. If the value of N ′ becomes equal to N in step 312,
Jumping to step 316, all the N hierarchical data are stored in the solid-state memory 302.

In the above, the operation of the write controller is performed according to the flow chart of FIG. 31, but another method as shown in FIG. 32 may be used. FIG. 32 is a flowchart showing the flow of the second operation of the write controller. In FIG. 32, step 320
Initialize N'to N with. In step 321, N'is decremented by one, and in step 322 it is determined whether the value of N'is greater than zero. If the value of N7 is greater than zero, the upper N'layer data is selected from the N layer data in step 323, and N'in step 324.
The signal decoded by the hierarchical data is compared with the original digital signal, and the degree of coincidence between the two is judged in step 325. If the degree of coincidence is smaller than a preset value, step 32
At step 6, the value of N'is incremented by one to return the value of N'to the previous value, and at step 327, the N'th hierarchical data is decremented.
Data in the solid-state memory 302. If step 32
If the degree of coincidence is larger than the preset value in 5, the process returns to step 321 again and the above steps are repeated. If the value of N'is equal to zero in step 322, the process jumps to step 326 and all N hierarchical data are stored in the solid-state memory 302.

As described above, according to this embodiment, only the N ′ (N ′ ≦ N) layer data among the layer data of N layers output from the layer encoder are used as the original data. When the digital signal can be decoded, the hierarchical data other than the N'hierarchical layers is not written in the solid-state memory (storage device), so that the data of the lower hierarchical layer is less frequently stored in the storage device. Therefore, since the time until the upper layer data overwrites the lower layer data is extended, the deterioration of the quality at the time of decoding due to the overwriting of the upper layer can be minimized.

A digital signal recording apparatus according to the 16th embodiment of the present invention will be described below with reference to the drawings.

FIG. 33 is a block diagram showing the arrangement of a digital signal recording apparatus according to the 16th embodiment of the present invention.
In FIG. 33, reference numeral 330 denotes a hierarchical encoder that encodes a digital signal from the first hierarchical data to the maximum Nth hierarchical data, and 331 denotes the first hierarchical data of the hierarchical encoder 330. A layer number selector for receiving N'th (N'≤N) layer data from the upper layer in response to the maximum Nth layer data, 3
A decoder 32 receives the N'th layer data from the first layer data and combines them into a decoder 333. The decoder 332 receives the output of the decoder 332 and the original digital signal, and evaluates the difference signal between them. , The difference signal evaluator 334 that instructs the layer number selector 331 to select the number of layers and sends the control signal to the write controller 334. The difference signal evaluator 334 is the first layer data output from the layer encoder 330. From the write controller 334, the write controller 335 controls writing of each hierarchical data 335 to the solid-state memory according to the output of the difference signal evaluator 333. A solid-state memory that receives data and auxiliary information data and stores the data.

The operation of the digital signal recording apparatus configured as described above will be described below with reference to FIG.

In FIG. 33, first, the input digital signal is encoded by the layer encoder 300 from the first layer data to the maximum Nth layer data, and the layer number selector 33.
1 and the write controller 301. The layer number selector 331 receives the signal from the difference signal evaluator 333 and selects the number of layers. The decoder 332 receives the N'th layer data from the layer number selector 331 output from the layer number selector 331, combines them, and sends the output to the difference signal evaluator 333. The difference signal evaluator 333 receives the output of the decoder 332 and the original digital signal, evaluates the difference signal between them, instructs the hierarchy number selector 331 to select the hierarchy number, and controls the write controller 334 to control the same. Send a signal. The write controller 334 receives the Nth layer data from the first layer data output from the layer encoder 330, and outputs the difference signal evaluator 33.
According to the output of 3, the writing of each hierarchical data to the solid-state memory 335 is controlled. The solid-state memory 335 is controlled by the write controller 334 to have N'th (N ') first to N'th.
≤N) hierarchical data and auxiliary information data are stored. Here, the selection of the number of layers is performed by the same procedure as that shown in the fifteenth embodiment.

As described above, according to this embodiment, a decoder for decoding a digital signal by using N '(N'≤N) hierarchical data, the decoding digital signal and the original digital signal are used. A difference signal evaluator for calculating the magnitude of the difference signal with the signal is provided, and when the value of the difference signal evaluator is smaller than a preset value, the layer data other than the N ′ layers is: By not writing to the solid-state memory (storage device),
The data of the lower layer is less frequently stored in the storage device, and therefore the data of the lower layer is stored by the data of the upper layer.
Since the time until the data is overwritten is extended, it is possible to minimize the quality deterioration at the time of decoding due to the overwriting of the upper layer. By employing the present embodiment, the same effect can be obtained regardless of the structure of the hierarchical encoder.

A digital signal recording apparatus according to the seventeenth embodiment of the present invention will be described below with reference to the drawings.

FIG. 34 is a block diagram showing the arrangement of a digital signal recording apparatus according to the 17th embodiment of the present invention.
In FIG. 34, 340 is a band-division hierarchical encoder that encodes a digital signal from the first frequency band data to the maximum Nth frequency band data, and 341 is the first frequency band data. The first band data for receiving and evaluating whether or not the data is omitted at the time of decoding and the quality is not greatly damaged.
Data evaluator, also 342 and 343, respectively
Second band data evaluator for evaluating whether or not the quality of the data is greatly damaged even if the data is omitted at the time of decoding. In response to this, the N-th band data evaluator evaluates whether the quality is not greatly damaged even if the data is omitted during decoding. 344 is a number-of-layers selection that receives the output signals of the first band data evaluator 341, the second band data evaluator 342, and the Nth band data evaluator 343 and selects the number of layers. 345 receives the Nth frequency band data from the first hierarchical data output from the hierarchical encoder 340, and outputs each frequency band to the solid-state memory 346 according to the output of the hierarchical layer number selector 344. A write controller 346 for controlling the writing of data is a solid-state memory which receives the frequency band data and auxiliary information data from the write controller 345 and stores the data.

The operation of the digital signal recording apparatus configured as described above will be described below with reference to FIG.

In FIG. 34, first, the input digital signal is coded by the band-division type hierarchical encoder 340 from the first hierarchical data to the maximum Nth hierarchical data, and the write controller 345, And a first band data evaluator 341,
It is sent to the second band data evaluator 342 and the Nth band data evaluator 343. First band data evaluator 341
Receives the first frequency band data, evaluates whether the quality is not greatly damaged even if the data is omitted during decoding, and outputs it to the layer number selector 344. Similarly, the second band data evaluator 342 receives the second frequency band data, evaluates whether the data is omitted at the time of decoding, and does not significantly damage the quality. Output to the number selector 344. The Nth band data evaluator 343 receives the Nth frequency band data and evaluates whether the quality is not greatly damaged even if the data is omitted at the time of decoding. Three
To 44. The number of layers selector 344 uses the first band data.
The number of layers is selected by receiving the output signals of the data evaluator 341, the second band data evaluator 342, and the Nth band data evaluator 343. The procedure is similar to that of the fifteenth embodiment. The write controller 345 receives the Nth frequency band data from the first frequency band data output from the band division type hierarchical encoder 340, and selects the number of layers selector 344.
The writing of each frequency band data to the solid-state memory 346 is controlled according to the output of The solid-state memory 346 stores N ′ (N ′ ≦ N) frequency band data and auxiliary information data from the first to N′th by the write controller 345.

As described above, according to this embodiment, the N '(N'≤N) hierarchical data are hierarchical data in which only signals in a specific frequency band are coded. When the magnitude of the signal in the frequency band that is not coded in the N'layer data is smaller than a preset value, the layer data other than the N'layer data is not written to the storage device. By doing so, the data of the lower layer is less frequently stored in the storage device, and therefore, the time until the lower layer data is overwritten by the upper layer data is extended, so that the upper layer data is increased. It is possible to minimize deterioration of quality at the time of decoding due to overwriting of layers. By adopting this embodiment, the above effect can be realized by a simple method.

A digital signal reproducing apparatus according to the eighteenth embodiment of the present invention will be described below with reference to the drawings.

FIG. 35 is a block diagram showing the structure of a digital signal reproducing apparatus according to the eighteenth embodiment of the present invention.
In FIG. 35, reference numeral 191 denotes a solid-state memory having a data storage area for storing hierarchically encoded hierarchical data and an auxiliary information storage area for storing auxiliary information indicating an attribute of the stored data. The hierarchical data and the auxiliary information representing the attribute of the hierarchical data are solid-state memories recorded by the digital signal recording device of the present invention. Particularly, in the present embodiment, the case where the digital signal recording device described in the first embodiment is a solid-state memory in which hierarchical data and auxiliary information representing the attribute of the hierarchical data are recorded will be described as an example.

Numeral 192 reads out the hierarchical data stored in the solid-state memory 191 and the auxiliary information indicating the attribute of the stored hierarchical data, and sequentially reads each hierarchical data in order of the time when the hierarchical data is stored. It is a controller. Reference numeral 193 is a quantizing code restoring device for receiving the respective hierarchical data outputted from the read control device 192 and restoring the original first to fourth code data, and the quantizing code restoring device performs the reading control. The quantization code decompressor restores the quantization code to the hierarchical data that has not been read from the device 192, while assigning a predetermined value according to the missing hierarchical data.

Numeral 194 is a first inverse quantizer which receives the first code data outputted from the quantization code decompressor 193 and decompresses the first band signal, and numeral 195 is a quantization code decompressor 193. The first inverse quantizer 196, which receives the second coded data output from the above and restores the second band signal,
The third dequantizer 197, which receives the third code data output from the quantization code restorer 193 and restores the third band signal, includes the fourth dequantizer 197 that outputs the fourth coded data output from the quantization code restorer 193. 4 is a fourth dequantizer that restores the fourth band signal by receiving the code data of.

A band combiner 198 receives the above band signals and combines the original digital signals. A D / A converter 199 receives the output of the band synthesizer 198 and converts the digital signal into an analog signal.

In FIG. 36, when the number of bits assigned to each band is 6 bits, 4 bits, 3 bits and 3 bits, respectively, the quantization code decompressor 193 causes the first to fourth hierarchical data to be transferred to each band. 2 shows a state in which the code data is restored. The numbers in each frame in FIG. 36 are numbers showing which hierarchy, and represent the first code data, the second code data, the third code data, and the fourth code data in order from the left column. ing. In FIG. 36, the first hierarchical data is 4-bit data of 4 bits on the MSB side of the first coded data, and the second hierarchical data is the second L of the first coded data.
BS 1 bit and 3 bits on the MSB side of the second code data, 4 bits in total, and 3rd hierarchical data is the 2 bits on the MSB side of the third code data and 2 on the MSB side of the fourth code data.
4-bit data in total, the fourth hierarchical data is the first LSB1 bit of the first code data, the first LSB1 bit of the second code data, and the first LSB1 of the third code data.
4 bits, 1 LSB of 4th code data
Bit data is restored to code data.

In FIG. 37, when the number of bits assigned to each band is 6 bits, 4 bits, 3 bits and 3 bits, respectively, the quantization code decompressor 193 converts the first to fourth hierarchical data into It shows how the code data of the band is restored, but shows the processing when the read controller 192 does not read the fourth hierarchical data. The numbers in each frame in FIG. 37 are numbers showing which layer, and the first code data and the second code are sequentially output from the left column.
Represents the code data, the third code data, and the fourth code data. Here, since the fourth hierarchical data has not been read, the value "L", that is, the logical value 0 is assigned.

Similarly, in FIG. 38, when the number of bits assigned to each band is 6 bits, 4 bits, 3 bits, and 3 bits, respectively, the quantization code decompressor 193 causes the quantization code decompressor 193 to operate in the first to fourth layers. It shows how the data is restored to the coded data of each band. The read controller 192
It shows a process when the fourth hierarchical data and the third hierarchical data are not read. The numbers in each frame in FIG. 38 are numbers showing which hierarchy, and represent the first code data, the second code data, the third code data, and the fourth code data in order from the left column. ing. Here, since the fourth hierarchical data and the third hierarchical data have not been read, the value "L", that is, the logical value 0 is assigned.

Similarly, in FIG. 39, when the number of bits allocated to each band is 6 bits, 4 bits, 3 bits, and 3 bits, respectively, the quantization code decompressor 193 causes the quantization code decompressor 193 to operate in the first to fourth layers. It shows how the data is restored to the coded data of each band. The read controller 192
It shows the processing when the fourth hierarchical data, the third hierarchical data, and the second hierarchical data are not read.
The numbers in each frame in FIG. 39 are numbers showing which hierarchy, and represent the first code data, the second code data, the third code data, and the fourth code data in order from the left column. ing. Here, since the fourth hierarchical data, the third hierarchical data, and the second hierarchical data have not been read, the value other than the second LSB of the first code data is "L", that is, the logical value 0.
Have been assigned. The second LSB of the first coded data is assigned the value "H", that is, the logical value 1, which is
In the coded data of each band, if two or more bits are discarded on the LSB side, and at least one MSB bit of the coded data is stored, the most significant bit among the discarded bits has a logical value of 1 This is because the rule of assigning is set in advance. The reason for providing such a rule is to obtain a decoded signal in an intermediate case from the case where all the discarded bits in the band have a logical value of 0 to the case where all the bits have a logical value of 1. As a result, even if the lower layer data is discarded, the deterioration of the decoding quality can be suppressed.

FIG. 40 shows the band synthesizer 198 shown in FIG.
3 is a block diagram showing a configuration example of FIG. As shown in FIG. 40, the band synthesizer 198 is composed of a QMF filter bank and is a band divider that has been widely used from the past ("Digital Signal Processing Handbook, pp.135-137, edited by the Institute of Electronics, Information and Communication Engineers"). 1993 ''). In the present embodiment, the QMF filter bank as described above is used as an example of the band divider, but in addition to this, a polyphase filter bank or a hybrid poly filter filter performed by an MPEG audio encoding algorithm or the like is used. Phase / MDC
It may be one using a T filter bank (ISO / IEC
11172-3: 1993).

FIG. 41 is a diagram showing a state of a data storage area in which hierarchical data is recorded. This is the first of the present invention.
10 is a view similar to FIG. 10 showing the state of the data storage area recorded by the digital signal recording apparatus according to the embodiment of FIG.

FIG. 42 is a diagram showing the contents of auxiliary information for hierarchical data. This is the same as FIG. 11 showing the state of the auxiliary information storage area recorded by the digital signal recording apparatus according to the first embodiment of the present invention.

The operation of the digital signal reproducing apparatus configured as described above will be described below with reference to FIGS. 35 to 42.
Will be explained.

In FIG. 35, first, the reading controller 1
Reference numeral 92 reads the auxiliary information stored in the auxiliary information storage area, and analyzes in what manner each hierarchical data is stored in the data storage area. For example, FIG.
When the auxiliary information shown in is read, it is analyzed as follows.

At the time of data recording, first, the first layer data is stored in the area from address 0000 to address 0FFF, the second layer data is stored in the area from address 1000 to address 1FFF, and the area from address 2000 to address 2FFF is stored. The third hierarchical data is stored, the fourth hierarchical data is stored in the area from the address 3000 to the address 3FFF, and subsequently, when the data storage area becomes the memory full state, the area from the address 2000 to the address 2FFF is stored. And address 3000 to address 3
The FFF area is released, the first layer data is stored in the area from the address 2000 to the address 2FFF, the second layer data is stored in the area from the address 3000 to the address 3FFF, and the data storage area is full of memory. When the state becomes, the area from the address 3000 to the address 3FFF is released, and the first layer data is stored in the area from the address 3000 to the address 3FFF.
Confirm that the recording process is completed in that state.

Therefore, the read controller 192 first
The data stored in the area from address 0000 to address 0FFF is sequentially read as the first hierarchical data, and at the same time, the data stored in the area from address 1000 to address 1FFF is sequentially read as the second hierarchical data, The first hierarchical data and the second hierarchical data are output to the coded decoder 193. Quantization code decoder 193
In the received hierarchical data, since the third hierarchical data and the fourth hierarchical data are missing, the code data of each band is restored according to FIG. 38.

Next, the first dequantizer 194 to the fourth dequantizer 197 dequantize the code data of each of the bands, respectively, and convert the code data of the first band signal to the fourth band signal. A band signal is generated and sent to the band synthesizer 198. The band combiner 198 decodes the band signal combination from the first band signal to the fourth band signal into the original digital signal, and the D / A converter 199 converts the band signal into an analog signal for output.

When all the data stored in the area from address 0000 to address 1FFF is read,
Next, the data stored in the area from address 2000 to address 2FFF is sequentially read as the first layer data, and the first layer data is output to the quantization code decoder 193. Since the second layer data, the third layer data, and the fourth layer data among the received layer data are missing, the quantizing code decoder 193 extracts the code data of each band according to FIG. 39. Restore.

Next, the first dequantizer 194 to the fourth dequantizer 197 dequantize the code data of each band, respectively, and convert the code data of the first band signal to the fourth band signal. A band signal is generated and sent to the band synthesizer 198. The band combiner 198 decodes the band signal combination from the first band signal to the fourth band signal into the original digital signal, and the D / A converter 199 converts the band signal into an analog signal for output.

When all the data stored in the area from address 2000 to address 2FFF is read,
Next, the data stored in the area from address 3000 to address 3FFF is sequentially read as the first layer data, and the first layer data is output to the quantization code decoder 193. Since the second layer data, the third layer data, and the fourth layer data among the received layer data are missing, the quantization coding / decoding unit 193, according to FIG.
The coded data of each band is restored.

Next, the first dequantizer 194 to the fourth dequantizer 197 dequantize the code data of each of the above bands, respectively, and convert the code data of the first band signal to the fourth band signal. A band signal is generated and sent to the band synthesizer 198. The band combiner 198 decodes the band signal combination from the first band signal to the fourth band signal into the original digital signal, and the D / A converter 199 converts the band signal into an analog signal for output.

As described above, according to this embodiment, the data storage area for storing the hierarchically encoded hierarchical data and the auxiliary information storage area for storing the auxiliary information indicating the attribute of the stored data are provided. The solid-state memory in which the hierarchical data and the auxiliary information indicating the attribute of the hierarchical data are recorded by the digital signal recording device of the present invention, the hierarchical data stored in the solid-state memory, and the stored Auxiliary information that represents the attributes of the hierarchical data is read, and a hierarchical decoder that decodes the original digital signal according to the hierarchy of the hierarchical data is provided, and the auxiliary information in the solid-state memory is provided inside the hierarchical decoder. A reading controller for reading the auxiliary information stored in the storage area and sequentially reading the hierarchical data stored in the data storage area in the solid-state memory based on the auxiliary information. Therefore, the data recorded by the digital signal recording apparatus of the present invention, it is possible to decode read efficiently.

[0191]

As described above, the digital signal recording apparatus according to the first aspect of the present invention includes a hierarchical encoder for hierarchically encoding digital signals, a solid-state memory for storing these hierarchical data,
And a write controller for controlling how the hierarchical data is stored in the solid-state memory, the write controller having a portion of the hierarchical data when the memory is full (preferably less important lower hierarchical data). By repeating the series of processes of releasing the stored data storage area to secure a free area and storing new hierarchical data in the free area, while maintaining the recording quality as much as possible, The recording time can be efficiently extended, and since the data is effectively stored in the solid-state memory, the solid-state memory can be effectively used.

Further, in the digital signal recording apparatus of the second invention, when the write controller has already written the hierarchical data higher than itself at the address to be written next, the write processing is performed at that time. By providing a rule to stop the writing, when the memory is full, the writing is automatically stopped from the lower hierarchy, and the recording time can be efficiently extended by an extremely simple process.

Further, in the digital signal recording apparatus of the third invention, by predetermining the address at which the writing of the hierarchical data is stopped, the writing processing can be stopped in any order regardless of the number of layers. it can.

Further, according to the digital signal reproducing apparatus of the present invention, the data storage area for storing the hierarchically encoded hierarchical data and the auxiliary information storage area for storing the auxiliary information representing the attribute of the stored data. The solid-state memory in which the hierarchical data and the auxiliary information representing the attribute of the hierarchical data are respectively recorded by the digital signal recording device of the present invention, the hierarchical data stored in the solid-state memory, and the stored And the auxiliary information indicating the attribute of the hierarchical data, and a hierarchical decoder for decoding the original digital signal according to the hierarchical layer of the hierarchical data, and the auxiliary decoder in the solid-state memory inside the hierarchical decoder. Read control for reading auxiliary information stored in the information storage area and sequentially reading hierarchical data stored in the data storage area in the solid-state memory based on the auxiliary information By providing the data recorded by the digital signal recording apparatus of the present invention,
It is possible to efficiently read and decrypt.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital signal recording device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a configuration of a band divider according to the embodiment.

FIG. 3 is a diagram showing a first example of layer division.

FIG. 4 is a diagram showing a second example of hierarchical division.

FIG. 5 is a flowchart showing the operation of the write controller according to the present embodiment.

FIG. 6 is a diagram showing a state of the data storage area when the above-mentioned data storage area becomes a memory full state for the first time during data recording.

FIG. 7 is a diagram showing the contents of auxiliary information when the above-mentioned data storage area becomes memory full for the first time during data recording.

FIG. 8 is a diagram showing a state of the data storage area when the above-mentioned data storage area becomes a memory full state for the second time during data recording.

FIG. 9 is a diagram showing the contents of auxiliary information when the above-mentioned data storage area is in the second memory full state during data recording.

FIG. 10 is a diagram showing a state of a data storage area at the end of data recording.

FIG. 11 is a diagram showing the contents of auxiliary information at the end of data recording.

FIG. 12 is a block diagram showing a configuration of a digital signal recording device according to a second embodiment of the present invention.

FIG. 13 is a diagram showing a third example of hierarchical division.

FIG. 14 is a diagram showing a fourth example of hierarchical division.

FIG. 15 is a diagram showing an example of a state in which information indicating a bit allocation pattern for each predetermined time interval is stored in an auxiliary information storage area.

FIG. 16 is a block diagram showing the configuration of a digital signal recording device according to a third embodiment of the present invention.

FIG. 17 is a block diagram showing the configuration of a digital signal recording device according to a fourth embodiment of the present invention.

FIG. 18 is a diagram showing input / output of the multi-pulse encoder according to the embodiment.

FIG. 19 is a diagram showing how the output of the multi-pulse encoder is divided into layers.

20A is a diagram showing a data storage area in the fifth embodiment. FIG. 20B is a diagram showing a data writing process after the data storage area is full in the fifth embodiment.

FIG. 21A is a diagram showing a data storage area in the sixth embodiment. FIG. 21B is a diagram showing a data writing process after the data storage area is full in the sixth embodiment.

22A is a diagram showing a data storage area in the seventh embodiment. FIG. 22B is a diagram showing a data writing process after the data storage area is full in the seventh embodiment.

23A is a diagram showing a data storage area in the eighth embodiment. FIG. 23B is a diagram showing a data writing process after the data storage area is full in the eighth embodiment.

FIG. 24 (a) shows a data storage area in the ninth embodiment. FIG. 24 (b) shows data after the entire data area in the ninth embodiment is filled with first to third hierarchical data. FIG. 6C is a diagram showing a writing process of FIG. 9C, and FIG. 9D is a diagram showing a writing process of data after the entire data area is filled with the first to second hierarchical data in the ninth embodiment. A diagram showing how the entire data area is filled with the first hierarchical data in the example

FIG. 25 (a) shows a data storage area in the tenth embodiment. FIG. 25 (b) shows a data writing process after the data area storing the third tier is full in the tenth embodiment. In the diagram (c), all the data areas in the tenth embodiment are
FIG. 6D is a diagram showing a data writing process after being filled with the second hierarchical data, and FIG. 8D is a diagram showing a state in which the entire data area is full with the first hierarchical data in the tenth embodiment. 10] is a diagram showing a writing process of the first to third hierarchical data in the tenth embodiment when the bit lengths of the respective hierarchical layers are not equal.

FIG. 26 (a) shows a data storage area in the eleventh embodiment. FIG. 26 (b) shows that all data areas in the eleventh embodiment are the first to the first data storage areas.
The figure (c) showing the data writing process after being filled with the fourth hierarchical data is shown in FIG.
The diagram (d) showing the data writing process after the third layer data is full is shown in FIG.
The figure which shows the write-in process of the data after being full with the 2nd hierarchy data, (e) is a figure which shows a mode that the whole data area is full with the 1st hierarchy data in the 11th Example

FIG. 27 (a) shows a data storage area in the twelfth embodiment. FIG. 27 (b) shows a data writing process after the data area storing the fourth tier is full in the twelfth embodiment. FIG. 13C shows the process of writing data after the data area for storing the third layer is full in the twelfth embodiment. FIG. 12D shows that the entire data area is first in the twelfth embodiment. ~
The figure which shows the write-in process of the data after becoming full with the 2nd hierarchy data (e) is a figure which shows a mode that the whole data area is full with the 1st hierarchy data in a 12th Example

FIG. 28 (a) shows a data storage area in a thirteenth embodiment. FIG. 28 (b) shows that all data areas in the thirteenth embodiment are first to third.
FIG. 13C is a diagram showing a data writing process after the fifth layer data is full, and FIG.
FIG. 12D is a diagram showing a data writing process after the data is filled with the fourth hierarchical data. In FIG.
The figure (e) showing the data writing process after the third layer data is full is shown in FIG.
The figure which shows the writing process of the data after being filled with the second hierarchical data

FIG. 29 (a) shows a data storage area in the fourteenth embodiment. FIG. 29 (b) shows a data writing process after the data area for storing the fifth layer is full in the fourteenth embodiment. The figure (c) shows the process of writing data after the data area for storing the fourth hierarchy is full in the fourteenth embodiment. The figure (d) shows that the third hierarchy is stored in the fourteenth embodiment. The diagram (e) showing the data writing process after the data area is full is shown in FIG.
The figure which shows the writing process of the data after being filled with the second hierarchical data

FIG. 30 is a block diagram showing the configuration of a digital signal recording device according to a fifteenth embodiment.

FIG. 31 is a flowchart showing the operation flow of the write controller.

FIG. 32 is a flowchart showing the second operation flow of the write controller.

FIG. 33 is a block diagram showing the configuration of a digital signal recording device according to a sixteenth embodiment.

FIG. 34 is a block diagram showing a configuration of a digital signal recording device in a seventeenth embodiment.

FIG. 35 is a block diagram showing the arrangement of a digital signal reproducing apparatus according to the 18th embodiment.

FIG. 36 is a diagram showing a state in which hierarchically divided data is restored to the original quantization code.

FIG. 37 is a diagram showing a state in which hierarchical data is restored to a quantized code when the fourth hierarchical data is missing.

FIG. 38 is a diagram showing a state in which hierarchical data is restored to a quantized code when the third and fourth hierarchical data are missing.

FIG. 39 is a diagram showing how hierarchical data is restored to a quantized code when the second, third and fourth hierarchical data are missing.

FIG. 40 is a block diagram showing the configuration of the band synthesizer according to the embodiment.

FIG. 41 is a diagram showing a state of a data storage area in which hierarchical data is recorded.

FIG. 42 is a diagram showing the contents of auxiliary information for hierarchical data.

[Explanation of symbols]

11, 21, 31, 41 A / D converter 12, 22, 32 Band divider 13, 23, 33 First quantizer 14, 24, 34 Second quantizer 15, 25, 35 Third Quantizer 16, 26, 36 Fourth quantizer 17, 27, 37, 43 Hierarchical divider 18, 28, 38, 45, 191, 302, 335, 3
46 solid state memory 19, 29, 39, 44, 301, 334, 345 write controller 30, 40 adaptive bit allocator 42 multi-pulse encoder 192 read controller 193 quantized code decompressor 194 first dequantization 195 Second dequantizer 196 Third dequantizer 197 Fourth dequantizer 198 Band combiner 199 D / A converter 300, 330 Hierarchical encoder 331, 344 Hierarchical number selector 332 Decoder 333 Difference signal evaluator 340 Band division type hierarchical coder 341 First band data evaluator 343 Nth band data evaluator 342 Second band data evaluator

[Procedure amendment]

[Submission date] July 25, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

Front page continuation (72) Inventor Tsuneo Tanaka 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Toshihiko Nagano 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (46)

[Claims] 1. A hierarchical encoder for encoding a digital signal from first hierarchical data to maximum Nth hierarchical data, and a data storage area for storing the data hierarchically encoded by the hierarchical encoder. A storage device having an auxiliary information storage area for storing auxiliary information representing an attribute of the stored data,
When the writable area of the storage device is insufficient, at least a part of the hierarchy data of any other hierarchy is retained while at least the first hierarchy data is retained among the hierarchy data stored in the storage device. The data area is released, and the storage area corresponding to the released data area stores the hierarchical data of any number of N or less, including at least the first hierarchical data, in the data storage area, And a write controller for storing auxiliary information representing an attribute of the stored data in the auxiliary information storage area, wherein the hierarchical encoder divides an input signal into M (M ≧ 1) bands. And M quantizers that receive the M band signals divided by the band divider and quantize them with a predetermined number of bits respectively, and quantize by the M quantizers. Total It is characterized in that it is configured to have a hierarchical divider that receives a quantized code of bits and hierarchically divides the quantized code into N (N> 1) hierarchical layers by a predetermined method. Digital signal recorder. 2. The number of bits for quantizing each band signal is
The power distribution or frequency spectrum distribution of each band signal for each predetermined time interval is adaptively distributed, and the method of hierarchical division in the hierarchical divider is changed according to the number of bits given to each band. The digital signal recording apparatus according to claim 1, wherein the digital signal recording apparatus is a digital signal recording apparatus. 3. The number of bits distributed to each band is
3. The digital signal recording apparatus according to claim 2, wherein the number of bits is at least a predetermined number of bits Bc (hereinafter referred to as core bit number) for each band. 4. At least a part of the quantizer for each band is an ADPCM encoder, and the number of core bits is
4. The digital signal recording device according to claim 3, wherein the number of bits is used for a prediction loop in ADPCM. 5. A hierarchical encoder for encoding a digital signal from the first hierarchical data to the maximum Nth hierarchical data, and a data storage area for storing the data hierarchically encoded by the hierarchical encoder. A storage device having an auxiliary information storage area for storing auxiliary information representing an attribute of the stored data,
When the writable area of the storage device is insufficient, at least a part of the hierarchy data of any other hierarchy is retained while at least the first hierarchy data is retained among the hierarchy data stored in the storage device. The data area is released, and the storage area corresponding to the released data area stores the hierarchical data of any number of N or less, including at least the first hierarchical data, in the data storage area, And a write controller for storing auxiliary information indicating an attribute of the stored data in the auxiliary information storage area, wherein the hierarchical encoder expresses a driving sound source of the combiner in the analysis-synthesis system by Np pulses. It is a multi-pulse encoder, and at least one Np pulse is used for each N or more pulses.
A hierarchical encoder that divides each group into N groups of hierarchical data, and stores the filter coefficient of the combiner output from the multipulse encoder in the auxiliary information storage area. A digital signal recording device. 6. The digital signal recording according to claim 5, wherein, when the Np pulses are divided into N layers, the pulses are divided into layers having higher amplitude in order from higher amplitude pulses. apparatus. 7. The first hierarchical data output from the hierarchical encoder is the hierarchical data having the highest degree of importance in decoding, and the following hierarchical order is such that the degree of importance decreases according to the layer number. 7. The digital signal recording device according to claim 1, wherein the digital signal recording device is hierarchical data. 8. The write controller is a write controller for sequentially writing each layer data in a storage device in a predetermined address order for each layer data, and when writing each layer data in the address order, the layer 3. The writing process of the hierarchical data is stopped when the hierarchical data having a hierarchical rank higher than the hierarchical rank of the hierarchical data is already written in the area to which the data is to be written. 7. The digital signal recording device according to any one of 7. 9. An address for stopping the writing process of each hierarchical data is calculated in advance by the bit rate of each hierarchical data and the capacity of the data storage area, and the writing address of each writing process of each hierarchical data is 9. The process is stopped when the address is reached.
The described digital signal recording device. 10. The write controller stores the first hierarchical data in the data storage area from address A to address B in the direction from address A to address B, and stores the second hierarchical data. 9. The data is stored from address B to address A.
Alternatively, the digital signal recording device according to claim 9. 11. A write controller stores the first hierarchical data in the data storage area from address A to address B in the direction from address A to address B, and stores the second hierarchical data. 10. The digital signal recording according to claim 8 or 9, wherein data is stored in a preset data storage area from address A'to address B between address A and address B. apparatus. 12. A write controller has a data storage area consisting of a first data storage area from address A to address B and a second data storage area from address C to address D. Store the layer 1 data in the direction from address A to address B,
Further, when data is stored up to the address B, the data is stored in the direction from the address D to the address C, and the second
Layer data is stored in the direction from address C to address D, and the third layer data is stored alternately from address B to address A and from address D to address C. The digital signal recording device according to claim 8 or 9, characterized in that. 13. A write controller has a data storage area consisting of a first data storage area from address A to address B and a second data storage area from address C to address D. Store the layer 1 data in the direction from address A to address B,
Further, when data is stored up to the address B, the data is stored in the direction from the address D to the address C, and the second
From the address C to the address D, and the third hierarchical data is stored from the address A'to the address B and the preset address A'to the address B. 10. The data storage area of No. 8 and the data storage area from a predetermined address C'to an address D between addresses C and D are stored. Digital signal recorder. 14. A write controller has a first data storage area from address A to address B and a second data storage area from address C to address D in a data storage area. Store the layer 1 data in the direction from address A to address B,
Further, when data is stored up to the address B, the data is stored in the direction from the address D to the address C, and the second
Layer data is stored in the direction from address C to address D, and the third layer data is stored alternately from address B to address A and from address D to address C. , The fourth hierarchical data from the preset address A'between the address A and the address B to the preset address B'between the address A'and the address B Data storage area and data from a preset address C'between address C and address D to a preset address D'between address C'and address D The digital signal recording device according to claim 8 or 9, wherein the digital signal recording device is stored in a storage area. 15. The write controller has a data storage area consisting of a first data storage area from address A to address B and a second data storage area from address C to address D. Store the layer 1 data in the direction from address A to address B,
Further, when data is stored up to the address B, the data is stored in the direction from the address D to the address C, and the second
Layer data in the direction from address C to address D, and the fourth layer data from address A'set in advance between address A and address B to address A '. A data storage area up to a preset address B'between the address and the address B, and a preset address C'between the address C and the address D to an address C '. The data is stored in a data storage area up to a preset address D ′ between the address D and the third hierarchical data set in advance between the address A ′ and the address B ′. A data storage area from the address A '' to the address B and a preset data area from the address C '' to the address D between the address C'and the address D '. Digital signal recording apparatus according to claim 8 or claim 9, wherein the storing in the data storage area. 16. A write controller comprising: a first data storage area from address A to address B; a second data storage area from address C to address D; and address E to address F. In the data storage area consisting of the third data storage area and the third data storage area, the first hierarchical data is stored in the direction from the address A to the address B, and when the data is further stored up to the address B, the address D is stored. From the address E to the address F, when the data is further stored from the address E to the address F, the second hierarchical data is stored from the address E to the address F. Direction, and when data is further stored up to address F, it is stored in the direction from address C to address D. , The third layer data is stored from address C to address D, and the fourth layer data is stored from address B to address A and from address D to address C and address F. The data is alternately stored in the direction from the address E to the address E, and the fifth hierarchical data is stored in the address A and the address B.
A data storage area from a preset address A'to the address to a preset address B'between the address A'and the address B, and an address C'and an address D '. Between the preset address C'and the address C'to the preset address D'between the addresses C'and D, and between the addresses E and F. 9. The data is stored in the data storage area from the preset address E'to the preset address E'to the preset address F'between the address E'and the address F '. The digital signal recording device according to claim 9. 17. The write controller comprises a first data storage area from address A to address B, a second data storage area from address C to address D, and address E to address F. In the data storage area consisting of the third data storage area and the third data storage area, the first hierarchical data is stored in the direction from the address A to the address B, and when the data is further stored up to the address B, the address D is stored. From the address E to the address F, when the data is further stored from the address E to the address F, the second hierarchical data is stored from the address E to the address F. Direction, and when data is further stored up to address F, it is stored in the direction from address C to address D. , The third layer data is stored in the direction from address C to address D, and the fifth layer data is stored from address A'set in advance between address A and address B, Address A '
A data storage area up to a preset address B'between the address and the address B and a preset address C'between the address C and the address D
From the address to the preset address D'address between the address C'and the address D, and from the preset address E'between the address E and the address F , The data is stored in a data storage area between the address E'and the address F up to the preset address F ', and the fourth layer data is stored between the address A'and the address B'. Data storage area from the preset address A '' to the address B, and the preset address C '' to the address D between the addresses C'and D ' And a data storage area from a preset address E ″ between the address E ′ and the address F ′ to the address F. Digital signal recording apparatus according to claim 8 or claim 9, wherein that. 18. If the original digital signal can be accurately decoded using only N ′ (N ′ <N) hierarchical data among the N hierarchical data output from the hierarchical encoder, the N ′ is used. 18. The digital signal recording device according to any one of claims 1 to 17, wherein hierarchical data other than the individual layers is not written in the storage device. 19. A decoder for decoding a digital signal using the N ′ hierarchical data, and a difference signal evaluator for calculating the magnitude of the difference signal between the digital signal and the original digital signal. 19. The digital signal recording apparatus according to claim 18, wherein when the value of the difference signal evaluator is smaller than a preset value, the hierarchical data other than the N'hierarchical layers is not written in the storage device. 20. The N ′ pieces of hierarchical data are hierarchical data in which only signals in a specific frequency band are encoded,
When the magnitude of a signal in a frequency band that is not encoded by the N ′ number of hierarchical data is smaller than a preset value, the hierarchical data other than the N ′ number of hierarchical data is not written in the storage device. 19. The digital signal recording device according to claim 18. 21. Read arbitrary hierarchical data stored in a data storage area in a storage device and auxiliary information stored in an auxiliary information storage area in the storage device, which represents attributes of the stored hierarchical data. However, a hierarchical decoder for decoding the original digital signal according to the hierarchy of the hierarchical data is provided, and the hierarchical decoder is the missing hierarchical data for the hierarchical data that does not exist in the storage device. A digital signal recording device, wherein decoding is performed while assigning a value according to a predetermined rule according to the above. 22. The hierarchical data and auxiliary information stored in the storage device are hierarchical data and auxiliary information recorded by the digital signal recording device according to any one of claims 1 to 20. The digital signal recording device according to claim 21. 23. The hierarchical data and auxiliary information stored in the storage device are hierarchical data and auxiliary information recorded by the digital signal recording device according to claim 1, wherein the hierarchical data and auxiliary information are stored in the storage device. The decoder is a hierarchical decoder that decodes hierarchical data that does not exist in the storage device while assigning a value according to a predetermined rule according to the missing hierarchical data, and the rule is In the coded data of each band, if two or more bits are discarded on the LSB side, and at least one MSB bit of the coded data is stored, the most significant bit among the discarded bits has a logical value of 1 22. The digital signal recording apparatus according to claim 21, wherein the rule is to assign a value of 0 and a logical value of 0 to the other values. 24. A hierarchical encoder for encoding a digital signal from first hierarchical data to maximum Nth hierarchical data, and a data storage area for storing the data hierarchically encoded by the hierarchical encoder. A storage device having an auxiliary information storage area for storing auxiliary information representing the attribute of the stored data, and a writable area of the storage device being insufficient,
Of the hierarchical data stored in the storage device, at least the first hierarchical data is held, and at least a part of the data area of the hierarchical data of any other hierarchy is released, and the released data area In the storage area corresponding to, at least the first hierarchical data including at least the number of hierarchical data of N or less are stored in the data storage area, and the auxiliary information representing the attribute of the stored data is stored in the storage area. The hierarchical encoder includes a write controller for storing the auxiliary information in the auxiliary information storage area, and the hierarchical encoder divides the input signal into M (M ≧ 1) bands, and M divided by the band divider. Receiving the band signals, receiving M number of quantizers each of which is quantized with a predetermined number of bits, and receiving a total Q-bit quantization code quantized by the M number of quantizers, Predict the quantization code N number (N> in a defined manner
A digital signal reproducing apparatus, characterized in that the digital signal reproducing apparatus is configured to have a hierarchy divider that divides the hierarchy into 1). 25. The number of bits for quantizing each band signal is distributed in accordance with the power distribution or frequency spectrum distribution of each band signal for each predetermined time interval, and is hierarchically divided by the hierarchical divider. 25. The digital signal reproducing apparatus according to claim 24, wherein the method is changed according to the number of bits given to each band. 26. The number of bits distributed to each band is at least a predetermined number of bits Bc (hereinafter referred to as a core bit number) for each band. Digital signal playback device. 27. The quantizer for each band is at least a part of an ADPCM encoder, and the number of core bits is a number of bits used for a prediction loop in ADPCM. Digital signal playback device. 28. A hierarchical encoder for encoding a digital signal from the first hierarchical data to the maximum Nth hierarchical data, and a data storage area for storing the data hierarchically encoded by the hierarchical encoder. A storage device having an auxiliary information storage area for storing auxiliary information representing the attribute of the stored data, and a writable area of the storage device being insufficient,
Of the hierarchical data stored in the storage device, at least the first hierarchical data is held, and at least a part of the data area of the hierarchical data of any other hierarchy is released, and the released data area In the storage area corresponding to, at least the first hierarchical data including at least the number of hierarchical data of N or less are stored in the data storage area, and the auxiliary information representing the attribute of the stored data is stored in the storage area. And a write controller for storing in the auxiliary information storage area, wherein the hierarchical encoder is a multipulse encoder that expresses a driving sound source of a synthesizer in an analysis-synthesis system by Np pulses, and the Np pulses. Is divided into at least one or more N groups, and each group is made into N hierarchical data. Digital signal reproducing apparatus characterized by storing the filter coefficient of the combiner output to the auxiliary information storage area. 29. When the Np pulses are divided into N hierarchies, the hierarchies are hierarchized so that pulses having a larger amplitude become higher hierarchy data.
The described digital signal reproducing device. 30. The first layer data output from the layer encoder is the layer data having the highest importance in decoding, and the layer order is set such that the importance becomes lower according to the layer number. 30. The digital signal reproducing device according to claim 24, wherein the digital signal reproducing device is hierarchical data. 31. The write controller is a write controller for sequentially writing each layer data in a storage device in a predetermined address order for each layer data, and when writing each layer data in the address order, the layer 25. The writing process of the hierarchical data is stopped when the hierarchical data having a hierarchical rank higher than the hierarchical rank of the hierarchical data is already written in the area in which the data is to be written. 31. The digital signal reproducing device according to any one of 30. 32. An address for stopping the writing process of each hierarchical data is calculated in advance based on the bit rate of each hierarchical data and the capacity of the data storage area, and the writing address of the writing process of each hierarchical data is 32. The digital signal reproducing apparatus according to claim 31, wherein the operation is stopped when the address is reached. 33. The write controller stores the first hierarchical data in the data storage area from address A to address B in the direction from address A to address B, and stores the second hierarchical data. 4. The data is stored in the direction from the address B to the address A.
33. The digital signal reproducing device according to claim 1 or 32. 34. The write controller stores the first hierarchical data in the data storage area from address A to address B in the direction from address A to address B, and stores the second hierarchical data. 33. Digital signal reproduction according to claim 31 or 32, characterized in that the data is stored in a preset data storage area from address A'to address B between address A and address B. apparatus. 35. A write controller has a data storage area consisting of a first data storage area from address A to address B and a second data storage area from address C to address D. Store the layer 1 data in the direction from address A to address B,
Further, when data is stored up to the address B, the data is stored in the direction from the address D to the address C, and the second
Layer data is stored in the direction from address C to address D, and the third layer data is stored alternately from address B to address A and from address D to address C. 33. The digital signal reproducing device according to claim 31 or 32. 36. A write controller has a data storage area consisting of a first data storage area from address A to address B and a second data storage area from address C to address D. Store the layer 1 data in the direction from address A to address B,
Further, when data is stored up to the address B, the data is stored in the direction from the address D to the address C, and the second
From the address C to the address D, and the third hierarchical data is stored from the address A'to the address B and the preset address A'to the address B. 33. The data storage area according to claim 31 or 32, and the data storage area from address C'to address D set in advance between address C and address D. Digital signal playback device. 37. A write controller has a data storage area consisting of a first data storage area from address A to address B and a second data storage area from address C to address D. Store the layer 1 data in the direction from address A to address B,
Further, when data is stored up to the address B, the data is stored in the direction from the address D to the address C, and the second
Layer data is stored in the direction from address C to address D, and the third layer data is stored alternately from address B to address A and from address D to address C. , The fourth hierarchical data from the preset address A'between the address A and the address B to the preset address B'between the address A'and the address B Data storage area and data from a preset address C'between address C and address D to a preset address D'between address C'and address D 33. The digital signal reproducing device according to claim 31, wherein the digital signal reproducing device is stored in a storage area. 38. A write controller has a data storage area consisting of a first data storage area from address A to address B and a second data storage area from address C to address D. Store the layer 1 data in the direction from address A to address B,
Further, when data is stored up to the address B, the data is stored in the direction from the address D to the address C, and the second
Layer data in the direction from address C to address D, and the fourth layer data from address A'set in advance between address A and address B to address A '. A data storage area up to a preset address B'between the address and the address B, and a preset address C'between the address C and the address D to an address C '. The data is stored in a data storage area up to a preset address D ′ between the address D and the third hierarchical data set in advance between the address A ′ and the address B ′. A data storage area from the address A '' to the address B and a preset data area from the address C '' to the address D between the address C'and the address D '. Claim, characterized in that stored in the data storage area 31 or claim 32
The described digital signal reproducing device. 39. A write controller comprises a first data storage area from address A to address B, a second data storage area from address C to address D, and address E to address F. In the data storage area consisting of the third data storage area and the third data storage area, the first hierarchical data is stored in the direction from the address A to the address B, and when the data is further stored up to the address B, the address D is stored. From the address E to the address F, when the data is further stored from the address E to the address F, the second hierarchical data is stored from the address E to the address F. Direction, and when data is further stored up to address F, it is stored in the direction from address C to address D. , The third layer data is stored from address C to address D, and the fourth layer data is stored from address B to address A and from address D to address C and address F. The data is alternately stored in the direction from the address E to the address E, and the fifth hierarchical data is stored in the address A and the address B.
A data storage area from a preset address A'to the address to a preset address B'between the address A'and the address B, and an address C'and an address D '. Between the preset address C'and the address C'to the preset address D'between the addresses C'and D, and between the addresses E and F. 32. The data is stored in a data storage area from the preset address E'to the preset address E'to the preset address F'between the address E'and the address F '. The digital signal reproducing device according to claim 32. 40. A write controller comprising: a first data storage area from address A to address B; a second data storage area from address C to address D; and address E to address F. In the data storage area consisting of the third data storage area and the third data storage area, the first hierarchical data is stored in the direction from address A to address B, and when data is further stored up to address B, address D is stored. From the address E to the address F, when the data is further stored from the address E to the address F, the second hierarchical data is stored from the address E to the address F. Direction, and when data is further stored up to address F, it is stored in the direction from address C to address D. , The third layer data is stored in the direction from address C to address D, and the fifth layer data is stored from address A'set in advance between address A and address B, Address A '
A data storage area up to a preset address B'between the address and the address B and a preset address C'between the address C and the address D
From the address to the preset address D'address between the address C'and the address D, and from the preset address E'between the address E and the address F , The data is stored in a data storage area between the address E'and the address F up to the preset address F ', and the fourth layer data is stored between the address A'and the address B'. Data storage area from the preset address A '' to the address B, and the preset address C '' to the address D between the addresses C'and D ' And a data storage area from a preset address E ″ between the address E ′ and the address F ′ to the address F. Digital signal reproducing apparatus according to claim 31 or claim 32, wherein that. 41. If the original digital signal can be accurately decoded only by N ′ (N ′ <N) hierarchical data among the N hierarchical data output from the hierarchical encoder, the N ′ is used. The digital signal reproducing device according to any one of claims 24 to 40, wherein hierarchical data other than the individual hierarchical layers is not written in the storage device. 42. A decoder is further provided for decoding a digital signal using the N ′ hierarchical data, and a difference signal evaluator for calculating the magnitude of the difference signal between the digital signal and the original digital signal. 42. The digital signal reproducing apparatus according to claim 41, wherein when the value of the difference signal evaluator is smaller than a preset value, hierarchical data other than the N'hierarchical layers is not written in the storage device. 43. The N ′ hierarchical data are hierarchical data in which only signals in a specific frequency band are encoded,
When the magnitude of a signal in a frequency band that is not encoded by the N ′ number of hierarchical data is smaller than a preset value, the hierarchical data other than the N ′ number of hierarchical data is not written in the storage device. 42. The digital signal reproducing device according to claim 41. 44. Read arbitrary hierarchical data stored in a data storage area in a storage device, and auxiliary information stored in an auxiliary information storage area in the storage device, which represents attributes of the stored hierarchical data. However, a hierarchical decoder for decoding the original digital signal according to the hierarchy of the hierarchical data is provided, and the hierarchical decoder is the missing hierarchical data for the hierarchical data that does not exist in the storage device. A digital signal reproducing apparatus characterized in that decoding is performed while assigning a value according to a predetermined rule according to the above. 45. The hierarchical data and auxiliary information stored in the storage device are the hierarchical data and auxiliary information recorded by the digital signal recording device according to any one of claims 1 to 20. The digital signal reproducing device according to claim 44. 46. The hierarchical data and auxiliary information stored in the storage device are the hierarchical data and auxiliary information recorded by the digital signal recording device according to claim 1, wherein the hierarchical data and auxiliary information are stored in the storage device. The decoder is a hierarchical decoder that decodes hierarchical data that does not exist in the storage device while assigning a value according to a predetermined rule according to the missing hierarchical data, and the rule is In the code data of each band, if two or more bits are discarded on the LSB side, and at least one MSB bit of the code data is stored, the most significant bit of the discarded bits has a logical value of 1 45. The digital signal reproducing apparatus according to claim 44, wherein the rule is to assign a value of 0 and a logical value of 0 otherwise.