JP2888129B2 - Digital signal recording device - Google Patents

Abstract

PURPOSE:To efficiently increase a recording time while maintaining the recording quality of digital signal to be recorded in a solid-state memory in quality as high as possible. CONSTITUTION:A hierarchial encoder is constituted of a band divider 12. quantizers 13 to 16, a hierarchy divider 17 and an input signal is divided into M pieces of bands by the band divider 12 and bands are respectively quantized into previously given number of bits by quantizers 13 to 16 and then quantized codes having quantized Q bits in total are inputted to the hierarchy divider 17 to be divided into a first to Nth hierarchies by a predetermined method. A write-in controller 19 writes respective hierarchial data in data storage areas of a solid-state memory 18 in a predetermined address order. At this time, in the case high-order hierarchial data are aleady written in an address in which the data are to be written, the controller 19 stops the writing. Then, auxiliary information expressing attributions of data such as the address in which hierarchial data are to be stored, etc., are stored in the atociliary information storage area of the solid-state memory 18.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal recording device and a digital signal reproducing device for encoding and recording digital signals in a solid-state memory.

[0002]

2. Description of the Related Art In recent years, a digital signal recording / reproducing apparatus using a solid-state memory as a recording medium is expected as a next-generation recording / reproducing apparatus with the increase in capacity and cost of semiconductor memories (solid-state memories). However, at present, solid-state memories are extremely expensive compared to other recording media such as magnetic tapes, magnetic disks, and optical disks, which hinders the practical use of digital signal recording / reproducing devices using solid-state memories. Signal compression technology is an effective means for effective use of solid-state memory and practical use of digital signal recording / reproducing devices.
Increasing the compression ratio has the problem that the recording quality is reduced.

A conventional example closest to the present invention will be described below with reference to Japanese Patent Application Laid-Open No. Hei 2-305053. The invention described in this publication makes it possible to change a bit rate when encoding a digital signal. When the memory capacity is sufficient, the digital signal is encoded at a high bit rate and recorded in the solid-state memory. Next, when the remaining capacity of the solid-state memory becomes small, data recorded at a high bit rate is read out from the solid-state memory, and the bit rate is reduced and re-encoded by a compression algorithm different from the original one. To record. This secures an empty area in the solid-state memory. By repeating this series of processes, the conflicting issues of recording quality and long time are addressed.

Further, the present applicant has filed a Japanese Patent Application No. Hei 5-27181.
No. 8 (hereinafter abbreviated to the prior application) proposes a digital signal recording / reproducing apparatus based on a hierarchical coding system, which is the basis of the present application.

[0005]

However, in the above conventional example, in order to secure an empty area in the solid-state memory, data recorded at a high bit rate is read from the solid-state memory, and the data is compressed by a compression algorithm different from the initial one. Re-encoding has to be performed again at a lower rate, so that there is a problem that the load on hardware is large and efficiency is low. Further, there is a problem that an unused area is generated in the solid-state memory depending on the data amount, and the solid-state memory cannot be effectively used.

Further, in the above-mentioned prior application by the present applicant, there is no particular limitation on the specific configuration of the hierarchical encoder and the method of storing the hierarchical data in the solid-state memory.

SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a digital signal recording / reproducing apparatus capable of efficiently extending a recording time while maintaining recording quality as much as possible and effectively utilizing a solid-state memory. With the goal. Further, the above-mentioned object can be realized by a simple process by adding a new configuration for the specific configuration of the hierarchical encoder and the method for storing the hierarchical data in the solid-state memory, which are not limited in the above-mentioned prior application. Things.

[0008]

In order to achieve the above object, a digital signal recording apparatus according to claim 1 comprises a hierarchical code
(12-17), recording device (18), writing controller (19)
Digital signal recording device, the hierarchical encoder (12-
17) converts the input digital signal into the first to Nth floors.
The data is encoded into the hierarchical data divided into the layer order, and the recording device (1
8) has a data storage area and an auxiliary information storage area,
The data storage area is the floor encoded by the hierarchical encoder (12-17).
Layer data is stored, and the auxiliary information storage area
Indicates which data storage area the data was stored in
The auxiliary information is stored, and the writing controller (19)
Record each layer data and its auxiliary information in the specified address order
Write to device (18), write hierarchical data with lower hierarchical order
Address matches the hierarchical data with the higher hierarchical order
When writing of hierarchical data with a lower hierarchical order is stopped
Both release some areas of hierarchical data with lower hierarchical order
It is configured to. The digital signal recording device according to claim 2 is the digital signal recording device according to claim 1,
9) The predetermined address order is the first hierarchical data
Is stored from address A to address B, and the second
From the address B to the address A
What to store. The digital signal recording device according to claim 3 is the digital signal recording device according to claim 1,
The determined address order is such that the first hierarchical data is
From address A to address B, to address B
Is stored from address D to address C
Then, the second hierarchical data is transferred from the address C to the address
Address A, address D alternates from address D to address C
It is something to pay. However, A <B, C <D (A>
B, C> D). According to a fourth aspect of the present invention, in the digital signal recording apparatus according to the first aspect, the write controller (19) has
The specified address order stores the first hierarchical data in the address.
From dress A to address B, to address B
When it reaches, it is stored from address D to address C
Then, the second hierarchical data is transferred from the address C to the address
The data is stored at address D, and the third hierarchical data is stored at address B.
To address A, address D to address C
And store the fourth hierarchical data in the address A '
From address to address A or address B, address
Address C 'to address C or address D
They are stored alternately. However, A <A '<B, C <
C '<D (A>A'> B, C> C '> D)
You. The digital signal recording apparatus according to claim 5 is the first embodiment
At a predetermined address of the writing controller (19).
The order of the addresses is such that the first hierarchical data is
When the address B is reached, the address is
Address D to address C, address C
Is stored in the address from address E to address F,
The second hierarchical data is transferred from address E to address F
When address F is reached, address C
From the address D, and the third hierarchical data
From the address C to the address D, and
Data from address B to address A, address
From address D to address C, from address F to address
Address E, and store the fifth hierarchical data in the address
Address A 'to address A or address B,
From address C 'to address C or D,
From address E 'to address E or address F
It is stored alternately on the ground. Where A <A ′ <B,
C <C ′ <D, E <E ′ <F (A> A ′> B, C
> C ′> D, E> E ′> F). The digital signal recording device according to claim 6 is the digital signal recording device according to claim 1.
The encoder (12-17) includes LPC synthesis filter coefficients and hierarchical data.
Multi-pulse code that outputs pulse information divided into data
The pulse information is a pulse amplitude (42)
The hierarchy order is determined based on the pulse amplitude value.
Is to be determined.

[0009]

[0010]

[0011]

[0012]

[Action] Digital signal recording apparatus according to claim 1 wherein, said
Composed of, if there is sufficient memory capacity for Recording time length, since all of the hierarchical data is held high-quality recording is performed, even when the memory is full,
Since the writing is automatically stopped from the lower hierarchy and the data of the upper hierarchy is overwritten, the recording time can be efficiently extended by extremely simple processing. That is, while maintaining the recording quality as much as possible, the recording time can be efficiently extended, and the data is effectively stored in the solid-state memory, so that the solid-state memory can be effectively used. According to the digital signal recording device of the present invention , both the first hierarchical data and the second hierarchical data can be written into the memory with extremely simple address control, and the write address of the second hierarchical data can be obtained. The recording time can be extended by discarding the lower layer (in this case, the second layer) data, based on a very simple criterion of whether or not the write address of the first layer data matches the write address of the first layer data. According to the digital signal recording device of the third aspect ,
Even when the number of hierarchies is three, the first, second, and third hierarchical data can be written into the memory by extremely simple address control, and the write address of the third hierarchical data is the first or second hierarchical data. A very simple criterion for determining whether or not the write address of the hierarchical data matches the write address of the second hierarchical data and whether or not the write address of the second hierarchical data matches the write address of the first hierarchical data allows the lower hierarchical data to be discarded. The recording time can be extended. The digital signal recording device according to claim 4 is configured as described above.
Therefore, even if the number of layers is 4, the first, second, third,
The fourth hierarchical data can be written to the memory with very simple address control, and whether the write address of the fourth hierarchical data matches the write address of the first, second, or third hierarchical data. Whether the write address of the third hierarchical data matches the write address of the first or second hierarchical data, and whether the write address of the second hierarchical data matches the write address of the first hierarchical data. With such a very simple criterion, the recording time can be extended by discarding the lower hierarchical data. According to the digital signal recording device of the present invention, even when the number of layers is five, the first, second, third, fourth, and fifth layer data can be stored in the memory by extremely simple address control. Writing can be performed, and whether the write address of the fifth hierarchical data matches the write address of the first, second, third, or fourth hierarchical data, whether the write address of the fourth hierarchical data is the first Or, whether or not it matches the write address of the second or third hierarchical data,
Whether the write address of the third hierarchical data matches the write address of the first or second hierarchical data,
The recording time can be extended by discarding the lower hierarchical data by a very simple criterion for determining whether the write address of the second hierarchical data matches the write address of the first hierarchical data. According to a sixth aspect of the present invention, in the digital signal recording apparatus , a multi-path
While maintaining the recording quality as much as possible in the Luth encoding system, the recording time can be efficiently extended, and the data is effectively stored in the solid-state memory, so that the solid-state memory can be effectively used. .

[0013]

[0014]

[0015]

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital signal recording apparatus and a digital signal reproducing apparatus according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a digital signal recording apparatus according to a first embodiment of the present invention. FIG.
, An analog audio input signal, for example, 1
A / D converter for converting to 6-bit digital signal, 1
2 is a band divider that divides the 16-bit digital signal from the A / D converter 11 into four bands from a first band signal to a fourth band signal, and 13 is a band divider that divides the first band signal into 6 bands. A first code which quantizes with bits and outputs first code data
A quantizer 14 quantizes the second band signal with 4 bits and outputs a second code data. A second quantizer 15 quantizes the third band signal with 3 bits. And a third quantizer 16 for outputting the third code data.
Is a fourth quantizer that quantizes the fourth band signal with 3 bits and outputs fourth code data, and 17 converts the total of 16 bits of the first to fourth code data into 16-bit code data. Upon receiving the data, the hierarchical divider 18 outputs 4-layer hierarchical data from the first hierarchical data to the fourth hierarchical data of 4 bits each. A data storage 18 stores the data hierarchically encoded by the hierarchical divider 17. A solid-state memory having an area and an auxiliary information storage area for storing auxiliary information indicating an attribute of the stored data; 19 is a hierarchical data stored in the solid-state memory 18 when a writable area of the solid-state memory 18 is insufficient. Among them, while retaining at least the first hierarchical data, at least a part of the data area of the hierarchical data of the other arbitrary layers is released, and a record corresponding to the released data area is released. In the region, including at least the first layer data, a write controller for storing hierarchical data in the number of 4 or less arbitrary hierarchy.

Here, the meaning of releasing the data area means that even if there is data already written in the data area, a state in which data can be newly written in the area is permitted. It is.

FIG. 2 is a block diagram showing an example of the configuration of the band divider 12 shown in FIG. As shown in FIG. 2, the band splitter 12 includes a quadrature mirror filter (QMF) 2
It is a QMF filter bank composed of stages and is a band splitter that has been widely used in the past (for example, “Digital Signal Processing Handbook, edited by IEICE, pp.135-
137 1993 ”). In the present embodiment, the QMF filter bank as described above is used as an example of the band splitter. In addition, a polyphase filter bank or a hybrid Such as using a phase / MDCT filter bank (ISO / IEC 11172-3: 199)
3).

In the present embodiment, the number of bits to be quantized by the first to fourth quantizers is 6 bits, 4 bits, 3 bits, and 3 bits, respectively. 6 bits, 5 bits, 3 bits,
It may be two bits or the like. In the present embodiment, the first to fourth quantizers are quantizers that perform linear quantization with a predetermined number of bits as described above.
It may be a non-linear quantizer that performs non-linear transformation using a logarithmic function, a hyperbolic function, or the like. Further, a quantizer that performs quantization while normalizing the amplitude according to the amplitude value of the input signal as performed by an MPEG audio encoding algorithm or the like (ISO
/ IEC 11172-3: 1993).

FIG. 3 shows that when the number of bits allocated to each band is 6, 4, 3, and 3, respectively, the hierarchical divider 17 outputs a code of a total of 16 bits of the first to fourth code data. It shows an example of which bit in the data is applied to which hierarchy. The number in each frame in FIG. 3 is a number indicating which layer. Note that bands 1 to 4 shown in FIG. 3 are the lowest frequency bands in band 1 and become higher frequency bands as they go to band 4 in order. In FIG. 3, the first
Is 4-bit data of 4 bits on the MSB side of the first code data, and the second hierarchy data is 1 bit of the second LBS of the first code data and the MSB of the second code data.
The 3rd side data is a total of 4 bits data of 3 bits on the side,
A total of 4-bit data of 2 bits on the MSB side of the third code data and 2 bits on the MSB side of the fourth code data, and the fourth hierarchical data is the 1st LSB 1 bit of the first code data and the 2nd code data of the second code data. The first LSB1 bit and the first LSB1 bit of the third code data and the first LSB of the fourth code data
This is a hierarchical structure such as a total of 4 bits of B1 bits. Performing the above hierarchical division
It is based on the idea that the information on the lower frequency band and the information on the MSB side in each band are more important. That is, it is only necessary to perform the hierarchical division in the order of the importance of the code data. Therefore, the hierarchical division is not necessarily required.

FIG. 4 shows that when the number of bits to be allocated to each band is 6, 5, 3, and 2, respectively, the hierarchical divider 17 outputs a code of a total of 16 bits of the first to fourth code data. It shows an example of which bit in the data is applied to which hierarchy. The number in each frame in FIG. 4 is a number indicating the hierarchy. In FIG. 4, the first hierarchical data is 4-bit data of 4 bits on the MSB side of the first code data, and the second hierarchical data is 1st bit of the second LBS of the first code data and the MSB of the second code data. The third hierarchical data is the MSB of the third code data.
The fourth hierarchical data is a total of 4-bit data of 2 bits on the MSB side and 2 bits on the MSB side of the fourth code data. The first LSB of the coded data is a 4-bit data of a total of 4 bits. Similar to the above-described example, the hierarchical division described above is based on the idea that the information in the low frequency band and the information on the MSB side in each band are more important. That is, it is only necessary to perform the hierarchical division in the order of the importance of the code data. Therefore, the hierarchical division is not necessarily required.

FIG. 5 is a flowchart showing the operation of the write controller 19. FIG. 6 is a diagram showing a state of the data storage area when the data storage area becomes a memory full state for the first time during data recording. Also, FIG.
FIG. 7 is a diagram showing the contents of auxiliary information when the data storage area is full of memory for the first time during data recording.

FIG. 8 is a diagram showing the state of the data storage area when the data storage area is full for the second time during data recording. FIG. 9 is a diagram showing the contents of the auxiliary information when the data storage area enters the memory full state for the second time during data recording.

FIG. 10 is a diagram showing the state of the data storage area at the end of data recording, and FIG. 11 is a diagram showing the contents of auxiliary information at the end of data recording.

The operation of the digital signal recording apparatus of the present embodiment configured as described above will be described below with reference to FIGS.

In FIG. 1, an analog audio input signal is first converted by an A / D converter 11 into a 16-bit digital signal. The digital signal is supplied to a band splitter 12.
Is divided into four bands from the first band signal to the fourth band signal. At this time, band division is performed by a QMF filter bank as shown in FIG.

The first quantizer 13 quantizes the first band signal by 6 bits and outputs first code data. The second quantizer 14 quantizes the second band signal with 4 bits and outputs second code data. The third quantizer 15 quantizes the third band signal with 3 bits and outputs third code data. Fourth quantizer 1
6 quantizes the fourth band signal by 3 bits,
Is output.

The hierarchical divider 17 receives the code data of a total of 16 bits of the first to fourth code data, and
As shown in (1), four layers of four-layer data from the first layer data to the fourth layer data are output.

As shown in FIG. 5, at the start of recording, the write controller 19 releases the entire area of the data storage area and writes the hierarchical data generated by the hierarchical divider 17 into that area. In this embodiment, all layers from the first layer data to the fourth layer data are selected and written. The write controller 19 also writes auxiliary information indicating in which area the data of the selected hierarchy is to be written.
Write to the auxiliary information storage area.

FIG. 6 shows the state of the data storage area in which the hierarchical data from the first hierarchical level to the fourth hierarchical level are stored as described above and the memory is full. In the present embodiment, the address 0000 to the address 0F
The first hierarchical data is stored up to the FF and the address 10
Second hierarchical data is stored from 00 to address 1FFF, third hierarchical data is stored from address 2000 to address 2FFF, and fourth hierarchical data is stored from address 3000 to address 3FFF.

FIG. 7 shows the contents of the auxiliary information when the layer data from the first layer to the fourth layer is stored as described above and the data storage area is full. ing. This is because the first hierarchical data is stored from address 0000 to address 0FFF, the second hierarchical data is stored from address 1000 to address 1FFF, and the address is stored from address 2000 to address 2FFF.
The third hierarchical data is stored up to the FF and the address 30
The content indicates that the fourth hierarchical data is stored from 00 to the address 3FFF.

When the memory is full, the write controller 19 checks the auxiliary information, selects a specific area of the data storage area, releases the area, and releases the area as shown in FIG. The hierarchical data generated by the hierarchical divider 17 is written in the open area. In this embodiment,
The area from the address 2000 to the address 3FFF, which is the area where the third hierarchical data and the fourth hierarchical data are stored, is released, and the hierarchical data generated by the hierarchical divider 17 is written in the released area. In this embodiment,
Layer data from the first layer to the second layer is selected and written. Further, the write controller 19 writes information indicating in which area the selected hierarchical data is to be written in the auxiliary information storage area.

FIG. 8 shows the state of the data storage area where the data of the first to second layers is newly stored as described above and the memory is full. . In this embodiment, the first hierarchical data is stored from address 0000 to address 0FFF, the second hierarchical data is stored from address 1000 to address 1FFF, and the address is stored from address 2000 to address 2FF.
F, the first hierarchical data is stored, and the address 300
Second hierarchical data is stored from 0 to address 3FFF.

FIG. 9 shows the auxiliary information when the data of the first to second layers is newly stored as described above and the data storage area is full. Indicates the content. This indicates that the first hierarchical data is newly stored from address 2000 to address 2FFF and the second hierarchical data is stored from address 3000 to address 3FFF.

When the memory becomes full, the write controller 19 checks the auxiliary information, selects a specific area of the data storage area, releases the area, and releases the area as shown in FIG. The hierarchical data generated by the hierarchical divider 17 is written in the open area. In this embodiment,
The area from the address 3000 to the address 3FFF is released, and the hierarchical data generated by the hierarchical divider 17 is written in the released area. In the present embodiment, the hierarchical data of the first hierarchy is selected and written. Further, the write controller 19 writes information indicating in which area the selected hierarchical data is to be written in the auxiliary information storage area.

FIG. 10 shows the state of the data storage area when the first hierarchical data is newly stored as described above and the recording state ends. Here, the first hierarchical data is stored from address 0000 to address 0FFF, and the address is stored from address 1000 to address 1FFF.
By the time the second hierarchical data is stored, the address 2000
From the address 3000 to the address 2FFF, and the first hierarchical data from the address 3000 to the address 3FFF.
Is stored.

FIG. 11 shows the contents of the auxiliary information when the first hierarchical data is newly stored as described above and the recording state ends. This indicates that the first hierarchical data is newly stored from the address 3000 to the address 3FFF.

What is important in the above processing is that the write controller 19 does not write data at a new time in the area where the first-layer data having the highest importance is stored. At the time, the first hierarchical data is always written.

As described above, according to this embodiment, an A / D converter for converting an analog audio input signal into a 16-bit digital signal, and M digital signals (M ≧ 1)
, A M band quantizer that receives the M band signals divided by the band divider and quantizes them with a predetermined number of bits, and a M band quantizer. Upon receiving a total of Q-bit quantization codes quantized by the quantizer, the number of the quantization codes is N (N> N) by a predetermined method.
(1) a hierarchical divider for hierarchically dividing into layers, a data storage area for storing data hierarchically divided by the hierarchical divider, and an auxiliary information storage area for storing auxiliary information indicating attributes of the stored data. And when the writable area of the solid-state memory is insufficient, at least the first hierarchical data among the hierarchical data stored in the solid-state memory is retained, and the hierarchy of any other hierarchy is retained. Release at least part of the data area of the data,
Storing in the data storage area in the storage area corresponding to the released data area any number of hierarchical data of at most N layers including at least the first hierarchical data,
A write controller for storing auxiliary information representing the attribute of the stored data in the auxiliary information storage area, wherein each time the data storage area becomes full, at least While retaining the first hierarchical data, at least a part of the data area of the hierarchical data of any other layer is opened, and the opened area newly includes at least the first hierarchical data. By storing N or less layers of arbitrary layer data, the recording time can be efficiently extended, and the first layer data, which is the most important encoded data, must be retained. Thus, large quality degradation can be prevented when decoding.

Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. FIG. 12 is a block diagram showing the configuration of the digital signal recording device according to the second embodiment of the present invention. In FIG. 12, reference numeral 21 denotes an A which converts an analog audio input signal into a 16-bit digital signal, for example.
A / D converter 22 is a band divider for dividing the 16-bit digital signal of the A / D converter 21 into four bands from a first band signal to a fourth band signal, and 28 is hierarchically coded. This is a solid-state memory having a data storage area for storing data and an auxiliary information storage area for storing auxiliary information indicating an attribute of the stored data, and is similar to that shown in the first embodiment. .

The second embodiment differs from the first embodiment in four points. The first point is that the band signals of the four bands output from the band divider 22 are divided at predetermined time intervals, and the power ratio of the signals of the four bands is obtained at each time interval. In addition, an adaptive bit allocator 30 for calculating the number of bits for quantizing each band signal is provided. The second point is that the first quantizer 23 quantizes the first band signal with the number of bits allocated to the first band by the adaptive bit allocator 30, and outputs the first code data. A second quantizer 24 quantizes the second band signal with the number of bits allocated to the second band by the adaptive bit allocator 30, and outputs a second code data. A third quantizer 25 that quantizes the third band signal with the number of bits allocated to the third band by the adaptive bit allocator 30, and outputs third code data. A fourth quantizer 26 quantizes the fourth band signal with the number of bits allocated to the fourth band by the adaptive bit allocator 30 and outputs fourth code data. It is a chemical converter. The third point is that while the hierarchical divider 27 adaptively changes the hierarchical division method according to the number of bits allocated to each band by the adaptive bit allocator 30, the first to fourth quantizers are used. This is a hierarchical divider that divides the code data quantized by the above into four layers. Fourthly, when the writable area of the solid-state memory 28 runs short, the write controller 29 keeps at least the first hierarchical data among the hierarchical data stored in the solid-state memory 28, At least a part of the data area of the hierarchical data of an arbitrary layer is released, and a storage area corresponding to the released data area is provided with at least four arbitrary layers including the first hierarchical data. This is a write controller for storing hierarchical data, and is also a write controller for writing the number of bits of each band allocated by the adaptive bit allocator 30 into the auxiliary information storage area of the solid-state memory 28.

FIG. 13 shows an adaptive bit allocator 30 in which the first
And the number of bits allocated to the fourth band is 5
Bits, 6 bits, 2 bits, and 3 bits, the hierarchical divider 27 outputs a total of 1 to 4 code data.
It shows an example of which bit in the 6-bit code data is applied to which hierarchy. FIG.
Is a number indicating which layer the number in each frame is. It is assumed that bands 1 to 4 shown in FIG. 13 are the lowest frequency bands in band 1 and become higher frequency bands in order as band 4 is reached.

In FIG. 13, the first hierarchical data is 4-bit data of 4 bits on the MSB side of the first code data,
Is the total 4-bit data of the 4 bits on the MSB side of the second code data, and the third layer data is the 2 bits on the MSB side of the third code data and the MSB of the fourth code data.
A total of 4-bit data of 2 bits on the side, and the fourth hierarchical data are:
The first LSB1 bit of the first code data, the LSB side 2 bits of the second code data, and the first LS of the fourth code data
This is a hierarchical structure such as a total of 4 bits of B1 bits. Performing the above hierarchical division
It is based on the idea that the information on the lower frequency band and the information on the MSB side in each band are more important. In other words, the hierarchical division may be performed in the order of the importance of the code data.

However, the hierarchical division is not necessarily required. FIG. 14 shows an example of this.
It is. FIG. 14 shows a case where the number of bits allocated to the first to fourth bands by the adaptive bit allocator 30 is 5 bits, 6 bits, 2 bits, and 3 bits, respectively, as in FIG. 14 shows another method of hierarchical division, and shows an example in which the hierarchical divider 27 applies any one of the bits in the total 16-bit code data of the first to fourth code data to which layer. It is a thing. The number in each frame in FIG. 14 is a number indicating the hierarchy. In FIG. 14, the first hierarchical data is the first hierarchical data.
The 4th bit data of the 4 bits on the MSB side of the code data of No. 3 and the second hierarchical data are the total 4 bit data of the 3 bits on the MSB side of the second code data and the 1st LSB 1 bit of the first code data, The data is M of the third code data.
2 bits on the SB side and 3rd on the second LSB side of the second code data
LSB total 4-bit data, the fourth hierarchical data is the second
Has a hierarchical structure such as 1 bit LSB of the first LSB and 3 bits of the 4th code data.

FIG. 3 shows that when the number of bits to be allocated to each band is 6, 4, 3, and 3, respectively, the hierarchical divider 17 outputs a code of a total of 16 bits of the first to fourth code data. It shows an example of which bit in the data is applied to which hierarchy. The number in each frame in FIG. 3 is a number indicating which layer. Note that bands 1 to 4 shown in FIG. 3 are the lowest frequency bands in band 1 and become higher frequency bands as they go to band 4 in order. In FIG. 3, the first
Is 4-bit data of 4 bits on the MSB side of the first code data, and the second hierarchy data is 1 bit of the second LBS of the first code data and the MSB of the second code data.
The 3rd side data is a total of 4 bits data of 3 bits on the side,
A total of 4-bit data of 2 bits on the MSB side of the third code data and 2 bits on the MSB side of the fourth code data, and the fourth hierarchical data is the 1st LSB 1 bit of the first code data and the 2nd code data of the second code data. The first LSB1 bit and the first LSB1 bit of the third code data and the first LSB of the fourth code data
This is a hierarchical structure such as a total of 4 bits of B1 bits. Performing the above hierarchical division
It is based on the idea that the information on the lower frequency band and the information on the MSB side in each band are more important. That is, it is only necessary to perform the hierarchical division in the order of the importance of the code data. Therefore, the hierarchical division is not necessarily required.

FIG. 4 shows that when the number of bits to be allocated to each band is 6, 5, 3, and 2, respectively, the hierarchical divider 17 outputs a code of a total of 16 bits of the first to fourth code data. It shows an example of which bit in the data is applied to which hierarchy. The number in each frame in FIG. 4 is a number indicating the hierarchy. In FIG. 4, the first hierarchical data is 4-bit data of 4 bits on the MSB side of the first code data, and the second hierarchical data is 1st bit of the second LBS of the first code data and the MSB of the second code data. The third hierarchical data is the MSB of the third code data.
The fourth hierarchical data is a total of 4-bit data of 2 bits on the MSB side and 2 bits on the MSB side of the fourth code data. The first LSB of the coded data is a 4-bit data of a total of 4 bits. Similar to the above-described example, the hierarchical division described above is based on the idea that the information in the low frequency band and the information on the MSB side in each band are more important. That is, it is only necessary to perform the hierarchical division in the order of the importance of the code data. Therefore, the hierarchical division is not necessarily required.

FIG. 15 shows an example in which information indicating a bit allocation pattern at predetermined time intervals is stored in the auxiliary information storage area.

The operation of the digital signal recording apparatus configured as described above will now be described with reference to FIGS.
This will be described with reference to FIGS. 14, 15, 3, and 4.

In FIG. 12, first, an analog audio input signal is converted by an A / D converter 21 into a 16-bit digital signal. The digital signal is supplied to a band divider 2
2, the band is divided into four bands from a first band signal to a fourth band signal. The above processing is the same as that shown in the first embodiment.

Next, the adaptive bit allocator 30 divides the four band signals output from the band divider 22 at predetermined time intervals, and determines the power ratio of the four band signals at each time interval. Then, the number of bits for quantizing each band signal is calculated according to the power ratio. In the present embodiment, as a method of adaptively allocating bits, allocation is simply performed in accordance with the power ratio of each band. Alternatively, a method using a psychoacoustic model using a method may be used (see ISO / IEC 11172-3: 1993).

Next, the first quantizer 23 quantizes the first band signal with the number of bits allocated to the first band by the adaptive bit allocator 30, and outputs first code data. , The second quantizer 24 quantizes the second band signal with the number of bits allocated to the second band by the adaptive bit allocator 30, outputs second code data, and outputs the third code data. The quantizer 25 quantizes the third band signal by the number of bits allocated to the third band by the adaptive bit allocator 30, and
The fourth quantizer 26 quantizes the fourth band signal with the number of bits allocated to the fourth band by the adaptive bit allocator 30, and outputs fourth code data. I do.

In the hierarchical divider 27, the adaptive bit allocator 3
The code data quantized by the first to fourth quantizers is hierarchically divided into four layers while the hierarchical division method is adaptively changed according to the number of bits assigned to each band at 0.

FIG. 13 shows an adaptive bit allocator 30 in which the first
And the number of bits allocated to the fourth band is 5
Bits, 6 bits, 2 bits, and 3 bits, the hierarchical divider 27 outputs a total of 1 to 4 code data.
It shows an example of which bit in the 6-bit code data is applied to which hierarchy. FIG.
Is a number indicating which layer the number in each frame is. In FIG. 13, the first hierarchical data is 4-bit data of 4 bits on the MSB side of the first code data, and the second hierarchical data is a 4-bit data of 4 bits on the MSB side of the second code data. The third hierarchical data is a total of 4-bit data of the MSB side 2 bits of the third code data and the MSB side 2 bits of the fourth code data, and the fourth hierarchical data is the first LSB1 bit of the first code data. L of the second code data
The hierarchical structure is such that the SB side 2 bits and the first LSB 1 bit of the fourth code data are a total of 4 bit data.

FIG. 3 shows an adaptive bit allocator 30. When the number of bits allocated to the first to fourth bands is 6, 4, 3, and 3, respectively, the hierarchical divider 17 The total of the first to fourth code data is 1
It shows an example of which bit in the 6-bit code data is applied to which hierarchy. The number in each frame in FIG. 3 is a number indicating which layer. In FIG. 3, the first hierarchical data is 4-bit data of 4 bits on the MSB side of the first code data, and the second hierarchical data is 1 second LBS bit of the first code data and the MSB of the second code data. The third hierarchical data is a total of 4-bit data of the MSB side 2 bits of the third code data and the MSB side 2 bits of the fourth code data, and the fourth hierarchical data is The first of the first code data
The hierarchical structure has a total of 4 bits of 1 LSB of LSB, 1 LSB of 1st LSB of the second code data, 1 LSB of 1st LSB of the 3rd code data, and 1 LSB of 1st LSB.

FIG. 4 shows an adaptive bit allocator 30. When the number of bits allocated to the first to fourth bands is 6, 5, 3, and 2, respectively, the hierarchical divider 17 The total of the first to fourth code data is 1
It shows an example of which bit in the 6-bit code data is applied to which hierarchy. The number in each frame in FIG. 4 is a number indicating the hierarchy. In FIG. 4, the first hierarchical data is 4-bit data of 4 bits on the MSB side of the first code data, and the second hierarchical data is 1st bit of the second LBS of the first code data and the MSB of the second code data. The third hierarchical data is a total of 4-bit data of the MSB side 2 bits of the third code data and the MSB side 2 bits of the fourth code data, and the fourth hierarchical data is The first of the first code data
This has a hierarchical structure of LSB 1 bit, LSB side 2 bits of the second code data and first LSB 1 bit of the third code data, that is, a total of 4 bits data.

As described above, the hierarchy divider 17 changes which bit is assigned to which hierarchy according to the number of bits of each band assigned by the adaptive bit assigner 30. Which bit is assigned to which hierarchy may be determined in advance for each bit pattern assigned as described above, or may be determined sequentially according to a predetermined ranking rule.

The write controller 29 stores the hierarchical data output as described above together with the auxiliary information in the solid-state memory 28. This process is the same as in the first embodiment.
However, the second embodiment is different from the first embodiment in that information indicating a bit allocation pattern is also stored in the auxiliary information storage area at every predetermined time interval for calculating the bit allocation amount. FIG. 15 shows an example of a state in which information indicating a bit allocation pattern for each predetermined time interval is stored in the auxiliary information storage area.

FIG. 15 shows that in the first time interval, 6 bits are allocated to the first band, 4 bits are allocated to the second band, 3 bits are allocated to the third band, and 3 bits are allocated to the fourth band. Similarly, in the second time interval, 6 bits are assigned to the first band, 5 bits are assigned to the second band, 3 bits are assigned to the third band, and 2 bits are assigned to the fourth band.
The time interval indicates that 5 bits are assigned to the first band, 5 bits are assigned to the second band, 3 bits are assigned to the third band, and 3 bits are assigned to the fourth band.

As described above, according to this embodiment, an A / D converter for converting an analog audio input signal into a 16-bit digital signal, and M digital signals (M ≧ 1)
A band divider that divides each band signal, and an adaptive bit allocator that distributes the number of bits for quantizing each band signal according to the power distribution or the frequency spectrum distribution of each band signal at predetermined time intervals. , M divided by the band divider
M quantizers for quantizing each of the band signals with the number of bits determined by the adaptive bit allocator;
In response to the quantization code of a total of Q bits quantized by the number of quantizers, the quantization code is divided into N (N> N) in accordance with the bit allocation pattern allocated by the adaptive bit allocator.
(1) a hierarchical divider for hierarchically dividing into layers, a data storage area for storing data hierarchically divided by the hierarchical divider, and an auxiliary information storage area for storing auxiliary information indicating attributes of the stored data. And when the writable area of the solid-state memory is insufficient, at least the first hierarchical data among the hierarchical data stored in the solid-state memory is retained, and the hierarchy of any other hierarchy is retained. Release at least part of the data area of the data,
Storing in the data storage area in the storage area corresponding to the released data area any number of hierarchical data of at most N layers including at least the first hierarchical data,
A write controller for storing auxiliary information representing the attribute of the stored data in the auxiliary information storage area, wherein each time the data storage area becomes full, at least While retaining the first hierarchical data, at least a part of the data area of the hierarchical data of any other layer is opened, and the opened area newly includes at least the first hierarchical data. By storing N or less layers of arbitrary layer data, the recording time can be efficiently extended, and the first layer data, which is the most important encoded data, must be retained. Thus, large quality degradation can be prevented when decoding. In addition, since the hierarchical division method is changed based on the frequency distribution of the input signal, even if the hierarchical data of the lower hierarchy is lost, it is possible to reduce the deterioration of the coding quality.

Hereinafter, a third embodiment of the present invention will be described with reference to the drawings. FIG. 16 is a block diagram showing a configuration of a digital signal recording device according to the third embodiment of the present invention. In FIG. 16, reference numeral 31 denotes an A which converts an analog audio input signal into a 16-bit digital signal, for example.
A / D converter 32 is a band divider for dividing the 16-bit digital signal of the A / D converter 31 into four bands from a first band signal to a fourth band signal, and 38 is hierarchically coded. A solid-state memory having a data storage area for storing data and an auxiliary information storage area for storing auxiliary information indicating the attribute of the stored data. Among the hierarchical data stored in the first hierarchical data, at least the first hierarchical data is retained, and at least a part of the data area of the hierarchical data of any other hierarchical level is released, which corresponds to the released data area. In the storage area, at least the first
Is a write controller for storing the hierarchical data of an arbitrary number of layers of four or less including the hierarchical data of (i), and the hierarchical divider 37 controls the adaptive bit allocator 40 in accordance with the number of bits allocated to each band. Is a hierarchical divider for hierarchically dividing the code data quantized by the first to fourth quantizers into four layers while adaptively changing the hierarchical division method.
This is the same as that shown in the embodiment.

The difference of the third embodiment from the second embodiment is that the adaptive bit allocator 40 divides the four band signals output from the band divider 32 at predetermined time intervals,
The power ratio of the signals of the four bands is obtained for each time interval,
Adaptive bit allocation for allocating the number of bits for quantizing each band signal in accordance with the power ratio, at least assigning the number of bits equal to or more than the number of bits previously allocated to each band (hereinafter, referred to as core bits) A first quantizer 33 quantizes the first band signal with the number of bits allocated to the first band by the adaptive bit allocator 40, and outputs first code data. Vessel, the second
Is a quantizer that quantizes the second band signal with the number of bits allocated to the second band by the adaptive bit allocator 40 and outputs second code data.
Is a quantizer that quantizes the third band signal with the number of bits allocated to the third band by the adaptive bit allocator 40, and outputs third code data.
Is a quantizer that quantizes the fourth band signal with the number of bits allocated to the fourth band by the adaptive bit allocator 40 and outputs fourth code data. Is a quantizer of the Embedded-ADPCM system. Embedded-ADP
In the CM system, the coded signal fed back to the predictor in the ADPCM system is made up of only the upper bits of a predetermined number of bits, and other bits are used in the prediction loop on the encoder side and the prediction loop on the decoder side. This is a coding scheme that is configured so that it is not used even if the
I Vol. J72-BI No.12 pp.1199-1209 December 1989 "). With such a configuration, even if the lower bits are discarded, there is no mismatch between the predicted signals on the encoder side and the decoder side, so that quality deterioration is reduced. In the present embodiment, the above-described Embedded-ADPCM
In (2), the bit to be fed back to the predictor is the core bit.

The operation of the digital signal recording apparatus configured as described above will now be described with reference to FIGS.
This will be described with reference to FIGS.

In FIG. 16, first, an analog audio input signal is converted by an A / D converter 31 into a 16-bit digital signal. The digital signal is supplied to a band divider 3
2, the band is divided into four bands from a first band signal to a fourth band signal. The above processing is the same as that shown in the second embodiment.

Next, the adaptive bit allocator 40 divides the four band signals output from the band divider 32 into predetermined time intervals, and calculates the power ratio of the four band signals at each time interval. The number of bits for quantizing each band signal is allocated according to the power ratio. At this time, at least the number of bits greater than the number of bits previously allocated to each band (hereinafter, referred to as core bits) is assigned. assign. In this embodiment, it is assumed that the core bits in the first band are 4 bits, the core bits in the second band are 3 bits, the core bits in the third band are 2 bits, and the core bits in the fourth band are 2 bits.

Next, the first quantizer 33 quantizes the first band signal by Embedded ADPCM with the number of bits allocated to the first band by the adaptive bit allocator 40, and converts the first code data. The second quantizer 34 outputs the second band signal with the number of bits allocated to the second band by the adaptive bit allocator 40.
The third coder quantizes by ADPCM and outputs the second code data, and the third quantizer 35 quantizes the third band signal by Embedded ADPCM with the number of bits allocated to the third band by the adaptive bit allocator 40. And outputs the third code data. The fourth quantizer 36 quantizes the fourth band signal with the number of bits allocated to the fourth band by the adaptive bit allocator 40 by using Embedded-ADPCM. And outputs fourth code data. At this time, the number of bits used for the prediction loop in the embedded-ADPCM of each band is the core bit.

In the hierarchical divider 37, the adaptive bit allocator 4
The code data quantized by the first to fourth quantizers is hierarchically divided into four layers while the hierarchical division method is adaptively changed according to the number of bits assigned to each band at 0.

FIG. 13 shows an adaptive bit allocator 30 in which the first
And the number of bits allocated to the fourth band is 5
Bits, 6 bits, 2 bits, and 3 bits, the hierarchical divider 27 outputs a total of 1 to 4 code data.
It shows an example of which bit in the 6-bit code data is applied to which hierarchy. FIG.
Is a number indicating which layer the number in each frame is. It is assumed that bands 1 to 4 shown in FIG. 13 are the lowest frequency bands in band 1 and become higher frequency bands in order as band 4 is reached.

In FIG. 13, the first hierarchical data is 4-bit data of 4 bits on the MSB side of the first code data,
Is the total 4-bit data of the 4 bits on the MSB side of the second code data, and the third layer data is the 2 bits on the MSB side of the third code data and the MSB of the fourth code data.
A total of 4-bit data of 2 bits on the side, and the fourth hierarchical data are:
The first LSB1 bit of the first code data, the LSB side 2 bits of the second code data, and the first LS of the fourth code data
This is a hierarchical structure such as a total of 4 bits of B1 bits. It should be noted here that the core bits of each band must be divided into the same layer for each band.
For example, in FIG. 13, the core bits of the first band are all 4 bits in the first layer, and the core bits of the second band are 3 bits.
The bits are all in the second layer, the core bits in the third band are all in the third layer, and the core bits in the fourth band are all in the third layer. In this way, even if specific lower layer data is lost, there is no mismatch between predicted signals on the encoder side and the decoder side, so that quality deterioration is reduced.

FIG. 3 shows an adaptive bit allocator 30. When the number of bits allocated to the first to fourth bands is 6, 4, 3, and 3, respectively, The total of the first to fourth code data is 1
It shows an example of which bit in the 6-bit code data is applied to which hierarchy. The number in each frame in FIG. 3 is a number indicating which layer. In FIG. 3, the first hierarchical data is 4-bit data of 4 bits on the MSB side of the first code data, and the second hierarchical data is 1 second bit of the second LSB of the first code data and the MSB of the second code data. The third hierarchical data is a total of 4-bit data of the MSB side 2 bits of the third code data and the MSB side 2 bits of the fourth code data, and the fourth hierarchical data is The first of the first code data
The hierarchical structure has a total of 4 bits of 1 LSB of LSB, 1 LSB of 1st LSB of the second code data, 1 LSB of 1st LSB of the 3rd code data, and 1 LSB of 1st LSB. In this way, even if specific lower layer data is lost, there is no mismatch between predicted signals on the encoder side and the decoder side,
This means that quality degradation is reduced.

FIG. 4 shows an adaptive bit allocator 30. When the number of bits allocated to the first to fourth bands is 6, 5, 3, and 2, respectively, the hierarchical divider 17 The total of the first to fourth code data is 1
It shows an example of which bit in the 6-bit code data is applied to which hierarchy. The number in each frame in FIG. 4 is a number indicating the hierarchy. In FIG. 4, the first hierarchical data is 4-bit data of 4 bits on the MSB side of the first code data, and the second hierarchical data is 1st bit of the second LBS of the first code data and the MSB of the second code data. The third hierarchical data is a total of 4-bit data of the MSB side 2 bits of the third code data and the MSB side 2 bits of the fourth code data, and the fourth hierarchical data is The first of the first code data
This has a hierarchical structure of LSB 1 bit, LSB side 2 bits of the second code data and first LSB 1 bit of the third code data, that is, a total of 4 bits data. In this way, even if specific lower layer data is lost, there is no mismatch between predicted signals on the encoder side and the decoder side, so that quality deterioration is reduced.

As described above, the hierarchical divider 17 changes which bit is assigned to which hierarchy according to the number of bits of each band assigned by the adaptive bit assigner 30. Which bit is assigned to which hierarchy may be determined in advance for each bit pattern assigned as described above, or may be determined sequentially according to a predetermined ranking rule.

The write controller 29 stores the hierarchical data output as described above together with the auxiliary information in the solid-state memory 28. This process is the same as in the second embodiment.

As described above, according to this embodiment, an A / D converter for converting an analog audio input signal into a 16-bit digital signal, and M digital signals (M ≧ 1)
A band divider that divides each band signal, and an adaptive bit allocator that distributes the number of bits for quantizing each band signal according to the power distribution or the frequency spectrum distribution of each band signal at predetermined time intervals. , M divided by the band divider
M quantizers for quantizing each of the band signals with the number of bits determined by the adaptive bit allocator;
In response to the quantization code of a total of Q bits quantized by the number of quantizers, the quantization code is divided into N (N> N) in accordance with the bit allocation pattern allocated by the adaptive bit allocator.
(1) a hierarchical divider for hierarchically dividing into layers, a data storage area for storing data hierarchically divided by the hierarchical divider, and an auxiliary information storage area for storing auxiliary information indicating attributes of the stored data. And when the writable area of the solid-state memory is insufficient, at least the first hierarchical data among the hierarchical data stored in the solid-state memory is retained, and the hierarchy of any other hierarchy is retained. Release at least part of the data area of the data,
Storing in the data storage area in the storage area corresponding to the released data area any number of hierarchical data of at most N layers including at least the first hierarchical data,
A write controller for storing auxiliary information indicating an attribute of the stored data in the auxiliary information storage area, wherein the adaptive bit allocator has a bit number equal to or more than a predetermined bit number (core bit) for each band. , And the quantizer of each band uses an embedded-ADP using only the core bits in a prediction loop.
Each time the data storage area is full of memory, at least one of the hierarchical data of any other layers is retained while retaining the first hierarchical data among the stored hierarchical data. By releasing the data area of the part and newly storing, in the released area, any number of hierarchical data of N or less, including at least the first hierarchical data, the recording time can be efficiently reduced. Extensions can be made. In addition, since the first layer data, which is the most important encoded data, is always held, large quality degradation can be prevented when decoding, and the quantizers for each band are lower-order. This is an embedded-ADPCM that is resistant to discarding lower layer data, and the layer division method is changed based on the frequency distribution of the input signal. Therefore, even if lower layer layer data is lost, deterioration in coding quality is reduced. be able to.

Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 17 is a block diagram showing a configuration of a digital signal recording device according to the fourth embodiment of the present invention. In FIG. 17, reference numeral 41 denotes an A for converting an analog audio input signal into a 16-bit digital signal, for example.
A / D converter 45 is a solid-state memory having a data storage area for storing hierarchically encoded data, and an auxiliary information storage area for storing auxiliary information indicating an attribute of the stored data. It is the same as that shown in the embodiment.

The fourth embodiment differs from the first embodiment in that, in the first embodiment, an encoding unit for generating code data to be input to a hierarchical divider includes a band divider and a second divider. In contrast to the first to fourth quantizers, in the present embodiment, the encoding unit that generates encoded data to be input to the hierarchical divider uses a driving source Np for the synthesizer in the analysis / synthesis system. The configuration of the multi-pulse encoder 42 expressed by the number of pulses and the write controller 44 have the same functions as those shown in the first embodiment, and the output from the multi-pulse encoder 42 A write controller for storing the coefficient of the LPC synthesis filter to be performed in the auxiliary information storage area,
The hierarchical divider 43 converts the Np pulses into at least one
The point is a hierarchical divider that divides each book into N groups or more and sets each group as N hierarchical data.

The multi-pulse coding method is a method in which a driving sound source of a synthesizer in an analysis / synthesis system is represented by a plurality of pulses and a decoded sound is generated by driving an LPC synthesis filter. This is a compression coding method that can perform voice compression coding at a lower bit rate than the compression coding method based on sub-band coding shown in the third embodiment from the example (“Digital Signals” edited by the Institute of Electronics, Information and Communication Engineers). Processing Handbook, pp. 343, 1993 ”, or Ozawa et al.,“ Study of Multipulse-Driven Speech Coding ”, IEICE Communications System Study Group, CS82-161, 1992-3).

FIG. 18 shows the input and output of the multi-pulse encoder 42, and shows a state in which the input speech data is compression-encoded into eight pulses and the coefficients of the LPC synthesis filter at predetermined time intervals. Represents.

FIG. 19 shows how the hierarchical divider 43 divides the eight pulses of the multi-pulse encoder 42 shown in FIG. 18 into four-layer data by grouping two pulses at a time. ing.

The operation of the digital signal recording apparatus configured as described above will now be described with reference to FIGS.
This will be described with reference to FIG.

In FIG. 17, first, an analog audio input signal is converted by an A / D converter 41 into, for example, a 16-bit digital signal. The digital signal is shown in FIG.
As shown in FIG. 8, the multi-pulse encoder 42 divides the data into predetermined time intervals, and encodes the LPC synthesis filter coefficients and eight pulses at each time interval. As shown in FIG. 19, the eight pulses are grouped two by two by a hierarchical divider 43, and are hierarchically divided into four hierarchical data.

In this embodiment, the first hierarchical data is data obtained by encoding the position and amplitude of the pulse having the largest amplitude and the pulse having the second largest amplitude, and the second hierarchical data is the data having the third largest amplitude. The position and the amplitude of the pulse having the largest amplitude and the pulse having the fourth largest amplitude are coded data. The fourth hierarchical data includes a pulse having the smallest amplitude and 2
The position and amplitude of the pulse with the second smallest amplitude are encoded data.

Here, the hierarchical division method is not as described above, but the first hierarchical data is data obtained by coding the positions and amplitudes of the first and fifth pulses, and the second hierarchical data is The position and amplitude of the second and sixth pulses are encoded data, the third hierarchical data is the encoded position and amplitude of third and seventh pulses, and the fourth hierarchical data is For example, the position and amplitude of the fourth and eighth pulses may be coded data, which may be determined simply by the position order, or may be determined by combining them.

The write controller 44 stores the hierarchical data output as described above together with the auxiliary information in the solid-state memory 45. This process is the same as in the first embodiment.
However, the write controller 44 also stores the coefficient of the LPC synthesis filter output from the multi-pulse encoder 42 as auxiliary information in the auxiliary information storage area in the solid-state memory.

As described above, according to this embodiment, the A / D converter for converting an analog audio input signal into a 16-bit digital signal and the driving sound source of the synthesizer in the analysis / synthesis system are composed of Np pulses. And a multi-pass encoder represented by the following formula:
Divided into N groups, each group having N pieces of hierarchical data, a data storage area for storing hierarchically encoded data, and auxiliary information indicating attributes of the stored data. A storage device having an auxiliary information storage area for storing, and when the writable area of the storage device is insufficient, at least the first hierarchical data among the hierarchical data stored in the storage device is retained,
At least a part of the data area of the hierarchical data of any other layer is released, and a storage area corresponding to the released data area has at least N arbitrary layers including at least the first hierarchical data. A write controller for storing the number of hierarchical data in the data storage area, and storing auxiliary information representing the attribute of the stored data in the auxiliary information storage area, wherein the synthesis output from the multi-pulse encoder is provided. The filter coefficient of the filter is stored in the auxiliary information storage area, and each time the data storage area becomes full, at least the first hierarchical data of the stored hierarchical data is retained and stored. At least a part of the data area of the hierarchical data of any hierarchy other than the above is released, and the released area newly includes at least the first hierarchical data. By storing the hierarchical data of an arbitrary number equal to or less than the number of layers, the recording time can be efficiently extended, and the first hierarchical data, which is the most important encoded data, is always retained. Therefore, when decoding, large quality degradation can be prevented. In addition, since the multi-pulse encoding method is used, the above-described operation can be performed at a low bit rate.

Hereinafter, a fifth embodiment of the present invention will be described with reference to the drawings. FIG.
7 shows a data storage area of a solid-state memory (storage device) in which hierarchical data hierarchically encoded by the hierarchical encoder constituting the digital signal reproducing device according to claim 7 is stored. In this embodiment, the number of hierarchies divided by the hierarchical divider is two.
Is shown. The data storage area comprises a first data storage area from address A to address B. The write controller writes hierarchical data to this data storage area according to the following procedure.

First, from time t1, the first hierarchical data is stored in the direction from address A to address B, and the second hierarchical data is stored in the direction from address B to address A. As shown in FIG. 20B, when the entire hierarchical data storage area becomes full at time t2, when data is written at the next time, the area where the second hierarchical data is to be written is The writing of the second hierarchical data is stopped because the first hierarchical data, which is higher in the hierarchy, has already been written. On the other hand, in the area where the first hierarchical data is to be written, since the second hierarchical data lower than the hierarchical order is written, the area is continuously stored in the area where the second hierarchical data has been written. .

As a result, when recording in a limited data area, even after the data area is full, the writing of the lower layer data is stopped, and the upper layer data is sequentially written on the already written lower layer data. By continuing the writing process of the hierarchical data, the recording time can be automatically extended.
Furthermore, when the recording time is short, high-quality recording can be performed, and a limited data area can be effectively used.

In this embodiment, the number of hierarchies is two. However, the number of hierarchies is not limited to two as long as it controls writing based on the above rules. Further, the capacity of the data write area for writing each hierarchical data does not need to be determined in advance. Further, each hierarchical data does not need to be an equal length code.

Hereinafter, a sixth embodiment of the present invention will be described with reference to the drawings. FIG. 21 (a) shows claim 1.
7 shows a data storage area of a solid-state memory (storage device) in which hierarchical data hierarchically encoded by the hierarchical encoder constituting the digital signal reproducing device according to claim 7 is stored. In this embodiment, the number of hierarchies divided by the hierarchical divider is two.
Is shown. The bit rate of the first hierarchical data is a [bps], and the bit rate of the second hierarchical data is b
[Bps]. The data storage area is from address A to address B, and the capacity is D. Address A 'where write processing of each hierarchical data is stopped first
The address is set in advance. Here, assuming that the recordable time when all the hierarchical data is stored is t, the capacity D of the recordable data storage area is represented by Expression (1).

D = a × t + b × t (1) The capacity of the data storage area from the address A to the address A ′ is a × t, and the data storage from the address A ′ to the address B is performed. The address A ′ is calculated in advance so that the capacity of the area is b × t. The write controller writes hierarchical data to the data storage area according to the following procedure.

The first hierarchical data is stored sequentially from the address A to the address B, and the second hierarchical data is stored sequentially from the address B to the address A.
After t, the write addresses of the first hierarchical data and the second hierarchical data reach the address A ′. Since the address A ′ is a write processing stop address calculated in advance for the second hierarchical data, the write processing of the second hierarchical data is stopped. Even if the write address of the first hierarchical data reaches the address A ', the area where the first hierarchical data is written at the next time stores the second hierarchical data lower than the hierarchical order. Since this is a data area, the first hierarchical data is continuously stored in the direction of address B.

By calculating the address at which the writing process of each hierarchical data is stopped in advance, the rules for storing each hierarchical data can be freely set. As a result, when the write address of each hierarchical data reaches a previously calculated address, the write processing of the lower hierarchical data is stopped, and only the upper hierarchical data is stored in the data storage area where the lower hierarchical data is stored. , The recording can be performed for a long time, and the recording can be performed with high quality in the case of a short recording, and the limited data area can be effectively used.

The writing direction of each second hierarchical data is not particularly limited. Further, each hierarchical data does not need to be an equal length code.

Hereinafter, a seventh embodiment of the present invention will be described. FIG. 22A shows a data storage area in the present embodiment. 8. A data storage area having a capacity D of a solid-state memory (storage device) for storing hierarchical data hierarchically encoded by a hierarchical encoder constituting the digital signal reproducing apparatus according to claim 1. And address A
From address to address B. This embodiment shows a case where the number of layers divided by the hierarchical divider is two. The data storage area includes a data write-inhibited area of the capacity D1. First, addresses A 'and B' of the data write-inhibited area are set. It is assumed that the bit rate of the first hierarchical data is a [bps] and the bit rate of the second hierarchical data is b [bps]. Assuming that the recordable time when all the hierarchical data is stored is t, the capacity D-D1 of the recordable data storage area is represented by the following equation (2).

D−D1 = a × t + b × t (2) The capacity of the data storage area from the address A to the address A ′ is a × t, and the data from the address B ′ to the address B Addresses A ′ and B ′ are calculated in advance so that the storage area 113 has a capacity of b × t. The write controller writes hierarchical data to the data area according to the following procedure.

The first layer data is in the direction from address A to address B, and the second layer data is in address B.
The data is stored in the direction from address to address A. T after the start of recording, the write address of the first hierarchical data reaches the address A ', and the write address of the second hierarchical data reaches the address B'. At the next time, the first
The second hierarchical data lower than the hierarchical order is stored in the data area to which the hierarchical data of the first hierarchical data is to be written. , And data is stored in the direction from address B ′ to address B. On the other hand, in the area where the second hierarchical data is to be written, the writing is stopped because the first hierarchical data higher than the hierarchical order is already stored.

As a result, when recording in the limited data area, even after the data area is full, writing of the lower layer data is stopped, and the data is sequentially written on the already written lower layer data. By continuing the recording of the data in the upper layer, the recording time can be automatically extended. When the recording time is short, high-quality recording can be performed, and when the recording time is extended, high-quality recording can be performed at the beginning of data, so that a limited data area can be effectively used.

Note that the data write-inhibited area may not be provided, and each hierarchical data does not need to have the same length code.

Hereinafter, an eighth embodiment of the present invention will be described. FIG. 23A shows a data storage area in the present embodiment. The data storage area is a data storage area having a capacity D of a storage device for storing hierarchical data hierarchically encoded by the hierarchical encoder constituting the digital signal reproducing apparatus according to claim 1. From address to address B. This embodiment shows a case where the number of layers divided by the hierarchical divider is two. The data storage area includes a data write-inhibited area of the capacity D1. First,
Addresses A 'and B' of the data write-inhibited area are set. The bit rate of the first hierarchical data is a
[Bps], the bit rate of the second hierarchical data is b [b
ps]. Assuming that the recordable time when all the hierarchical data is stored is t, the capacity D-D1 of the recordable data storage area is represented by Expression (3).

D−D1 = a × t + b × t (3) The capacity of the data storage area from the address A to the address A ′ is a × t, and the data from the address B ′ to the address B An address A 'and an address B' are calculated in advance so that the capacity of the storage area is b × t. The write controller writes hierarchical data to the data area according to the following procedure.

The first hierarchical data is stored in the direction from address A to address B. The second hierarchical data is stored in the direction from the address B ′ to the address B, and a rule is established in advance that the writing is stopped when the write address of the second hierarchical data reaches the address B.

At time t after the start of recording, the write address of the first hierarchical data reaches address A ', and the second data write address reaches address B. At the next time, the second hierarchical data reaches the write processing stop address B, so that the write is stopped. Since the area where the first hierarchical data is to be written stores the second hierarchical data having a lower hierarchical order than the hierarchical order, the first hierarchical data is stored in the area.
The write processing of the hierarchical data of is continued.

As a result, when the write address of the lower hierarchical data reaches a preset address, the write processing is stopped, and the upper hierarchical data is stored in the data area of the lower hierarchical level in which the data has already been written. By continuing the recording only in the upper layer, the recording time can be automatically extended. During long-time recording, data can be recorded with high quality at the end of data, and during short-time recording, all data can be recorded with high quality, and a limited data area can be effectively used.

The writing direction of the second hierarchical data is not particularly limited. Further, there may be no write-protected area, or a plurality of write-protected areas may exist.

Hereinafter, a ninth embodiment of the present invention will be described. FIG. 24A shows a data storage area in the present embodiment. The data storage area includes a first data storage area from address A to address B and a second data storage area from address C to address D. Further, information of addresses A, B, C, D and write time is stored in an auxiliary information storage area (not shown). The write controller writes hierarchical data to the data storage area according to the following procedure.

The first hierarchical data is stored in the direction from address A to address B. When the address reaches address B, the data is stored in the direction from address D to address C. The second hierarchical data is address C
The data is stored in the direction from address to address D. Also,
The third hierarchical data is stored alternately in the direction from address B to address A and in the direction from address D to address C as shown in the figure. In addition, the second
With respect to each of the third layers, a rule is set that the writing is stopped when data of the upper layer has already been written in the area to be written next.

Now, assuming that the entire data area is full of the first to third hierarchical data, when writing the next data, the writing of the third hierarchical data is stopped, and FIG.
As shown in (b), the first and second hierarchical data are the third hierarchical data.
Data is written to the area where the data of the hierarchy has been written.

Further, assuming that the entire data area is filled with the first and second hierarchical data, when writing the next data, the writing of the second hierarchical data is stopped, and FIG.
As shown in (c), the data of the first hierarchy is written from the address D to the address C in the area where the data of the second hierarchy has been written. Finally Figure 2
As shown in FIG. 4D, when the entire data area is filled with the first hierarchical data, the writing is completed.

As a result, even during long-time recording, recording can be continued with only upper-layer data while sequentially discarding lower-layer data, and high-quality recording can be performed during short-time recording. Recording is possible, and a limited data area can be used effectively.

Note that if a rule is established that the writing of the third hierarchical data is stopped when the entire data area becomes full, the writing direction of the third hierarchical data is not particularly limited. When the number of bits allocated to each layer is fixed, the data storage area in which each layer data is to be written may be determined in advance, and there is no need to provide a rule for stopping the writing of the lower layer provided in the present embodiment. .

Hereinafter, a tenth embodiment of the present invention will be described. FIG. 25A shows a data storage area in this embodiment. The data storage area includes a first address space from address A to address B and a second address space from address C to address D. The write controller writes hierarchical data to this data storage area according to the following procedure.

The first hierarchical data is stored in the direction from address A to address B. When the address reaches address B, the data is stored in the direction from address D to address C. The second hierarchical data is address C
The data is stored in the direction from address to address D. Also,
The third hierarchical data is alternately stored in the data area between the address B and the address A 'and in the data area between the address D and the address C'. Here, the addresses A 'and C' are set in advance between the address A and the address B and between the address C and the address D, respectively.

Now, assuming that the data area for storing the third hierarchy is full, the writing of the data of the third hierarchy is stopped when the next data is written, and as shown in FIG. The first and second hierarchical data are written to the area where the third hierarchical data has been written.

Further, assuming that the entire data area is filled with the first and second hierarchical data, the writing of the second hierarchical data is stopped when the next data is written, and FIG.
As shown in (c), the data of the first hierarchy is written into the area where the data of the second hierarchy has been written. Finally, as shown in FIG.
When the layer data is full, the writing is completed.

In this embodiment, the case where the bit length of each layer is equal is shown, but this is not always necessary. For example, the first layer has 4 bits, the second layer has 2 bits, the third layer has
When the hierarchy is 4 bits, as shown in FIG. 25E, the size of the data area of the first hierarchy is different from the size of the data area of the second hierarchy. In this case, if the data of the third hierarchy is stored alternately in the data area between the address B and the address A 'and in the data area between the address D and the address C' as described above, an empty area is obtained. Will happen. In this case, as shown in FIG. 25 (e), the data is stored in the direction from the address A 'to the address B. When the address B is reached, the data is stored in the direction from the address D to the address C'. Just go. Of course, the writing direction of the third hierarchical data is not particularly limited.

As a result, even during long-time recording, it is possible to continue recording with only upper-layer data while sequentially discarding lower-layer data, and to obtain high-quality data during short-time recording. Recording is possible, and a limited data area can be used effectively.

Hereinafter, an eleventh embodiment of the present invention will be described. FIG. 26A shows a data storage area in this embodiment. The data storage area includes a first data storage area from address A to address B and a second data storage area from address C to address D. The write controller writes hierarchical data to this data storage area according to the following procedure.

The first hierarchical data is stored in the direction from address A to address B. When the address reaches address B, the data is stored in the direction from address D to address C. The second hierarchical data is address C
The data is stored in the direction from address to address D. Also,
The third hierarchical data is stored alternately in the direction from address B to address A and in the direction from address D to address C. Further, the fourth hierarchical data is stored alternately in the direction from address A 'to address A and in the direction from address C' to address C.

The addresses A 'and C' are set in advance between the addresses A and B, and between the addresses C and D, respectively. In addition, the second to fourth
For each layer, there is a rule that if the data of the upper layer has already been written in the area to be written next, the writing is stopped.

Now, assuming that the entire data area is full of the first to fourth hierarchical data, when writing the next data, the writing of the fourth hierarchical data is stopped, and FIG.
As shown in (b), the first to third hierarchical data are the fourth hierarchical data.
Data is written to the area where the data of the hierarchy has been written.

Next, assuming that the entire data area is full of the first to third hierarchy data, the writing of the third hierarchy data is stopped when the next data is written, and FIG.
As shown in (c), the first and second hierarchical data are the third hierarchical data.
Data is written to the area where the data of the hierarchy has been written.

Further, assuming that the entire data area is filled with the first and second hierarchical data, the writing of the second hierarchical data is stopped when the next data is written, and FIG.
As shown in (d), the data of the first hierarchy is written from the address D to the address C in the area where the data of the second hierarchy has been written. Finally Figure 2
As shown in FIG. 6E, when the entire data area is filled with the first hierarchical data, the writing is completed.

As a result, even during long-time recording, recording can be continued with only upper-layer data while sequentially discarding lower-layer data, and high-quality recording can be performed during short-time recording. Recording is possible, and a limited data area can be used effectively.

The writing direction of the fourth hierarchical data is not particularly limited. If the number of bits allocated to each hierarchical layer is fixed, a data storage area for writing each hierarchical data is set in advance. It is only necessary to decide, and it is not necessary to provide a rule for stopping the writing of the lower hierarchy provided in the present embodiment.

Hereinafter, a twelfth embodiment of the present invention will be described. FIG. 27A shows a data storage area in the present embodiment. The data storage area includes a first address space from address A to address B and a second address space from address C to address D. The write controller writes hierarchical data to this data storage area according to the following procedure.

The first hierarchical data is stored in the direction from address A to address B. When the address reaches address B, the data is stored in the direction from address D to address C. The second hierarchical data is address C
The data is stored in the direction from address to address D. Also,
The third hierarchical data is stored alternately in the data area between the address B and the address A "and in the data area between the address D and the address C". Here, the addresses A "and C" are set in advance between the address A and the address B and between the address C and the address D, respectively. Further, the fourth hierarchical data is alternately stored in the data areas between the addresses A 'and B' and between the addresses C 'and D'.

Here, the addresses A 'and C' are set in advance between the address A and the address A ", the address C and the address C", respectively, and the addresses B 'and D' are the addresses respectively. A "address and address B
The address is set in advance between address "C" and address D.

Now, assuming that the data area for storing the fourth hierarchy is full, the writing of the data of the fourth hierarchy is stopped when the next data is written, and as shown in FIG. The first to third hierarchical data are written to the area where the fourth hierarchical data has been written.

Next, assuming that the data area for storing the third hierarchy is full, the third data is written when the next data is written.
Writing of the data of the hierarchy is stopped, and as shown in FIG. 27C, the first and second hierarchy data are written to the area where the data of the third hierarchy has been written.

Further, assuming that the entire data area is full of the first and second hierarchical data, the writing of the second hierarchical data is stopped when the next data is written.
As shown in (d), the data of the first hierarchy is written into the area where the data of the second hierarchy has been written. Finally, as shown in FIG. 27E, the entire data area is the first data area.
When the layer data is full, the writing is completed.

As a result, even during long-time recording, recording can be continued with only upper-layer data while sequentially discarding lower-layer data, and high-quality recording can be performed during short-time recording. Recording is possible, and a limited data area can be used effectively.

The writing direction of the fourth hierarchical data is not particularly limited.

Hereinafter, a thirteenth embodiment of the present invention will be described. FIG. 28A shows a data storage area in this embodiment. The data storage area includes a first data storage area from address A to address B, a second data storage area from address C to address D, and a third data storage area from address E to address F. Data storage area. The write controller writes hierarchical data to this data storage area according to the following procedure.

The first hierarchical data is stored in the direction from address A to address B. Address B
When the address is reached, the data is stored in the direction from address D to address C. When the address reaches address C, the data is stored in the direction from address E to address F.
The second hierarchical data is stored in the direction from address E to address F. When the address reaches address F, the data is stored in the direction from address C to address D. The third hierarchical data is from address C to address D
Stored in the direction of the address. The fourth hierarchical data is stored alternately in the direction from address B to address A, in the direction from address D to address C, and in the direction from address F to address E. Further, the fifth hierarchical data is stored alternately in the direction from address B 'to address A, in the direction from address D' to address C, and in the direction from address F 'to address E.

The addresses B ', D', and F 'are set in advance between addresses A and B, addresses C and D, and addresses E and F, respectively. In addition, for each of the second to fifth hierarchies, a rule is set such that if the data of the upper hierarchy has already been written in the area to be written next, the writing is stopped.

Now, assuming that the entire data area is full of the first to fifth hierarchical data, the writing of the fifth hierarchical data is stopped when the next data is written.
As shown in (b), the first to fourth hierarchical data are the fifth hierarchical data.
Data is written to the area where the data of the hierarchy has been written.

Next, assuming that the entire data area is full of the first to fourth hierarchical data, the writing of the fourth hierarchical data is stopped when the next data is written, and FIG.
As shown in (c), the first to third hierarchical data are the fourth hierarchical data.
Data is written to the area where the data of the hierarchy has been written.

Further, assuming that the entire data area is filled with the first to third hierarchical data, the writing of the third hierarchical data is stopped when the next data is written, and FIG.
As shown in (d), the first and second hierarchical data are the third hierarchical data.
Data is written to the area where the data of the hierarchy has been written. Finally, assuming that the entire data area is filled with the first and second hierarchical data, when writing the next data, the writing of the second hierarchical data is stopped, and as shown in FIG. , The first layer of data is written to the area where the second layer of data has been written.

As a result, even during long-time recording, it is possible to continue recording with only upper-layer data while sequentially discarding lower-layer data, and to obtain high-quality data during short-time recording. Recording is possible, and a limited data area can be used effectively.

The writing direction of the fifth hierarchical data is not particularly limited. When the number of bits allocated to each hierarchical data is fixed, the data storage area for writing each hierarchical data is set in advance. It suffices to decide, and it is not necessary to provide a rule for stopping the writing of the lower hierarchy provided in the present embodiment.

Hereinafter, a fourteenth embodiment of the present invention will be described. FIG. 29A shows a data storage area in this embodiment. The data storage area includes a first data storage area from address A to address B, a second data storage area from address C to address D,
It comprises a third data storage area from address E to address F. The write controller writes hierarchical data to this data storage area according to the following procedure.

The first hierarchical data is stored in the direction from address A to address B. Address B
When the address is reached, the data is stored in the direction from address D to address C. When the address reaches address C, the data is stored in the direction from address E to address F.
The second hierarchical data is stored in the direction from address E to address F. When the address reaches address F, the data is stored in the direction from address C to address D. The third hierarchical data is from address C to address D
Stored in the direction of the address. The fourth hierarchical data is stored alternately between address B and address A ", between address D and address C", and between address F and address E ". The addresses A ", C", and E "are preset between addresses A and B, addresses C and D, and addresses E and F, respectively.

Further, the fifth hierarchical data alternates between address A 'and address B', between address C 'and address D', and between address E 'and address F'. To be stored.

Here, the addresses A ', C' and E 'are preset between addresses A and A ", addresses C and C", and addresses E and E ", respectively. And addresses B ', D',
F 'is preset between address A "and address B, address C" and address D, and address E "and address F, respectively.

Now, assuming that the data area for storing the fifth hierarchical level is full, the writing of the data of the fifth hierarchical level is stopped when the next data is written, and as shown in FIG. The first to fourth hierarchical data are written in the area where the fifth hierarchical data has been written.

Next, assuming that the data area for storing the fourth hierarchy is full, the fourth data is written when the next data is written.
Writing of hierarchical data is stopped, and as shown in FIG. 29C, the first to third hierarchical data are written to the area where the fourth hierarchical data has been written.

Next, assuming that the data area for storing the third hierarchy is full, the third data is written when the next data is written.
The writing of the hierarchical data is stopped, and the first and second hierarchical data are written to the area where the third hierarchical data has been written, as shown in FIG. 29D.

Further, assuming that the entire data area is filled with the first and second hierarchical data, the writing of the second hierarchical data is stopped when the next data is written.
As shown in (e), the data of the first hierarchy is written into the area where the data of the second hierarchy has been written.

As a result, even during long-time recording, recording can be continued with only upper-layer data while sequentially discarding lower-layer data, and high-quality recording can be performed during short-time recording. Recording is possible, and a limited data area can be used effectively.

The writing directions of the fourth and fifth hierarchical data are not particularly limited.

Hereinafter, a digital signal recording apparatus according to a fifteenth embodiment of the present invention will be described with reference to the drawings.

FIG. 30 is a block diagram showing the structure of a digital signal recording apparatus according to the fifteenth embodiment of the present invention.
In FIG. 30, reference numeral 300 denotes a hierarchical encoder for encoding a digital signal from first hierarchical data to Nth hierarchical data, and 301 denotes a hierarchical encoder from the first hierarchical data of the hierarchical encoder 300. A write controller 302 for controlling the writing to the solid-state memory in response to the Nth hierarchical data at the maximum, receives the hierarchical data and the auxiliary information data from the write controller 301, and stores the data. It is a solid-state memory. FIG. 31 is a flowchart showing the flow of the operation of the write controller.

The operation of the digital signal recording apparatus configured as described above will now be described with reference to FIGS.
This will be described with reference to FIG.

In FIG. 30, first, an input digital signal is encoded by the hierarchical encoder 300 from the first hierarchical data to the Nth maximum hierarchical data, and the write controller 3
01 is sent. The write controller 301 receives the maximum Nth hierarchical data from the first hierarchical data and controls the writing to the solid-state memory 302 as shown in the first to fourteenth embodiments. Here, the point different from the first to fourteenth embodiments is that not all the N hierarchical data output from the hierarchical encoder 300 are stored in the solid-state memory 302, but N hierarchical data. N '(N' ≤
When the original digital signal can be decoded with high accuracy by the N) hierarchical data, the hierarchical data other than the N 'hierarchical data is not written in the solid-state memory 302.

This will be described in more detail with reference to the flowchart shown in FIG. In step 310, N ′ is initialized to zero. In step 311, N 'is incremented by one, and in step 312, it is determined whether the value of N' is less than N.
If the value of N 'is smaller than N, the upper N' hierarchical data is selected from the N hierarchical data in step 313, and the N 'hierarchical data is selected in step 314. In step 315, the degree of coincidence between the decoded signal and the original digital signal is determined. If the degree of coincidence is larger than a preset value, the N 'hierarchical data is determined in step 316. Is stored in the solid-state memory 302. If step 315
If the coincidence is smaller than the preset value, the process returns to step 311 and repeats the above steps. In step 312, if the value of N 'is equal to N,
The process jumps to step 316, where all the N hierarchical data are stored in the solid-state memory 302.

In the above description, the operation of the write controller was performed according to the flowchart of FIG. 31, but another method may be used as shown in FIG. FIG. 32 is a flowchart showing the flow of the second operation of the write controller. In FIG. 32, step 320
Initializes N ′ to N. In step 321, N ′ is decremented by one, and in step 322, it is determined whether the value of N ′ is greater than zero. If the value of N7 is larger than zero, in step 323, the upper N 'hierarchical data is selected from the N hierarchical data, and in step 324, N' is selected.
The signal decoded with the hierarchical data and the original digital signal are compared, and the degree of coincidence between them is determined in step 325. If the degree of coincidence is smaller than a preset value, step 32
In step 6, the value of N 'is incremented by one, and the value of N' is returned to the previous value. In step 327, the N 'hierarchical data
The data is stored in the solid-state memory 302. If step 32
If the degree of coincidence is larger than the preset value in step 5, the process returns to step 321 and repeats the above steps. If the value of N 'is equal to zero in step 322, the process jumps to step 326, where all the N hierarchical data are stored in the solid-state memory 302.

As described above, according to the present embodiment, only N ′ (N ′ ≦ N) hierarchical data of the N hierarchical data output from the hierarchical encoder are used as the original data. When a digital signal can be decoded, hierarchical data other than the N 'hierarchical data is not written to the solid-state memory (storage device), so that data of lower hierarchy is stored in the storage device less frequently. Therefore, the time required for the lower hierarchical data to be overwritten by the upper hierarchical data is extended, so that the deterioration of the decoding quality due to the overwriting of the upper hierarchical data can be minimized.

Hereinafter, a digital signal recording apparatus according to a sixteenth embodiment of the present invention will be described with reference to the drawings.

FIG. 33 is a block diagram showing a configuration of a digital signal recording apparatus according to the sixteenth embodiment of the present invention.
In FIG. 33, reference numeral 330 denotes a layer encoder for encoding a digital signal from the first layer data to the Nth layer data at maximum, and 331 denotes a layer encoder from the first layer data of the layer encoder 330. A layer number selector for selecting N ′ (N ′ ≦ N) layer data from an upper layer in response to a maximum N-th layer data;
A decoder 32 receives the N'th layer data from the first layer data and combines them, and 333 receives the output of the decoder 332 and the original digital signal and evaluates the difference signal between them. The difference signal evaluator 334 instructs the number-of-layers selector 331 to select the number of layers, and sends the control signal to the write controller 334. The difference signal evaluator 334 outputs the first layer data as the output of the layer encoder 330. Receiving the Nth hierarchical data from the write controller 335 for controlling the writing of each hierarchical data of 335 to the solid-state memory in accordance with the output of the difference signal evaluator 333; A solid-state memory which receives data and auxiliary information data and stores the data.

The operation of the digital signal recording apparatus configured as described above will be described below with reference to FIG.

In FIG. 33, first, the input digital signal is encoded by the hierarchical encoder 300 from the first hierarchical data to the Nth maximum hierarchical data, and the hierarchical number selector 33
1 and the write controller 301. The hierarchy number selector 331 receives the signal from the difference signal evaluator 333 and selects the hierarchy number. The decoder 332 receives the N'th layer data from the first layer data which is the output of the layer number selector 331, combines the data, and sends the output to the difference signal evaluator 333. The difference signal evaluator 333 receives the output of the decoder 332 and the original digital signal, evaluates the difference signal between them, instructs the number-of-layers selector 331 to select the number of layers, and instructs the write controller 334 to control the number of layers. Send a signal. The write controller 334 receives the Nth hierarchical data from the first hierarchical data output from the hierarchical encoder 330, and receives the difference signal evaluator 33.
According to the output of (3), writing of each hierarchical data to the solid-state memory 335 is controlled. The write controller 334 controls the number of the solid-state memories 335 from N 'to N' (N ').
.Ltoreq.N) and auxiliary information data. Here, the number of layers is selected in the same procedure as described in the fifteenth embodiment.

As described above, according to the present embodiment, a decoder for decoding a digital signal by using N ′ (N ′ ≦ N) hierarchical data, the decrypted digital signal and the original digital signal And a difference signal evaluator for calculating the magnitude of the difference signal from the signal. If the value of the difference signal estimator is smaller than a preset value, the layer data other than the N ′ layers is: By not writing to solid state memory (storage device),
The frequency of storing the data of the lower hierarchy in the storage device is reduced, and therefore the data of the lower hierarchy is stored in the upper hierarchy data.
Since the time until the data is overwritten is extended, the quality degradation at the time of decoding due to the overwriting of the upper layer can be minimized. According to the present embodiment, the same effect can be obtained regardless of the configuration of the hierarchical encoder.

Hereinafter, a digital signal recording apparatus according to a seventeenth embodiment of the present invention will be described with reference to the drawings.

FIG. 34 is a block diagram showing the structure of a digital signal recording apparatus according to the seventeenth embodiment of the present invention.
In FIG. 34, reference numeral 340 denotes a band division type hierarchical encoder for encoding a digital signal from the first frequency band data to the Nth maximum frequency band data, and 341 denotes the first frequency band data. A first band data for evaluating whether the quality is not greatly damaged even if the data is omitted during decoding.
Evaluators, also 342 and 343, respectively,
A second band data evaluator for evaluating whether the quality is not significantly damaged even if the data is omitted upon decoding after receiving the frequency band data, and an Nth frequency band data. This is an N-th band data evaluator that evaluates whether the quality is not significantly damaged even if the data is omitted at the time of decoding upon receipt of the data. Reference numeral 344 denotes a layer number selection unit that receives output signals of the first band data evaluator 341, the second band data evaluator 342, and the Nth band data evaluator 343 and selects the number of layers. 345 receives the Nth frequency band data from the first layer data which is the output of the layer encoder 340, and outputs each frequency band to the solid-state memory 346 according to the output of the layer number selector 344. A write controller 346 for controlling the writing of data is a solid-state memory which receives the frequency band data and the auxiliary information data from the write controller 345 and stores the data.

The operation of the digital signal recording apparatus configured as described above will be described below with reference to FIG.

In FIG. 34, first, an input digital signal is encoded from a first hierarchical data to a maximum Nth hierarchical data by a band division type hierarchical encoder 340, and a write controller 345, And a first band data evaluator 341;
The data is sent to the second band data evaluator 342 and the Nth band data evaluator 343. First band data evaluator 341
Receives the first frequency band data, evaluates whether or not the data will not be greatly damaged even if the data is omitted during decoding, and outputs the result to the number-of-layers selector 344. Similarly, the second band data evaluator 342 receives the second frequency band data and evaluates whether the omission of the data at the time of decoding will not significantly damage the quality. Output to the number selector 344. The N-th band data evaluator 343 receives the N-th frequency band data, evaluates whether or not the data is omitted at the time of decoding without significantly damaging the quality. 3
44. The number-of-layers selector 344 outputs the first band data.
In response to the output signals of the data evaluator 341, the second band data evaluator 342, and the Nth band data evaluator 343, the number of layers is selected. The procedure is the same as in the fifteenth embodiment. The write controller 345 receives the Nth frequency band data from the first frequency band data output from the band division type hierarchical encoder 340, and
The writing of each frequency band data to the solid-state memory 346 is controlled in accordance with the output of. The solid-state memory 346 stores the first to N '(N'≤N) frequency band data and auxiliary information data by the write controller 345.

As described above, according to the present embodiment, the N ′ (N ′ ≦ N) hierarchical data is hierarchical data that encodes only a signal in a specific frequency band. If the magnitude of the signal in the frequency band not encoded with the N ′ hierarchical data is smaller than a preset value, the hierarchical data other than the N ′ hierarchical data should not be written to the storage device. By doing so, the frequency of storing the data of the lower hierarchy in the storage device is reduced, and the time until the lower hierarchy data is overwritten by the upper hierarchy data is extended. Deterioration of quality at the time of decoding due to overwriting of the hierarchy can be minimized. According to the present embodiment, the above effects can be realized by a simple method.

Hereinafter, a digital signal reproducing apparatus according to an eighteenth embodiment of the present invention will be described with reference to the drawings.

FIG. 35 is a block diagram showing the structure of a digital signal reproducing apparatus according to the eighteenth embodiment of the present invention.
In FIG. 35, reference numeral 191 denotes a solid-state memory having a data storage area for storing hierarchically encoded hierarchical data, and an auxiliary information storage area for storing auxiliary information indicating an attribute of the stored data. Hierarchical data and auxiliary information representing attributes of the hierarchical data are solid-state memories recorded by the digital signal recording device of the present invention. Particularly, in the present embodiment, an example will be described in which the digital signal recording apparatus described in the first embodiment is a solid-state memory in which hierarchical data and auxiliary information indicating attributes of the hierarchical data are recorded.

A readout 192 reads the hierarchical data stored in the solid-state memory 191 and auxiliary information indicating the attribute of the stored hierarchical data, and sequentially reads out each hierarchical data in order of the time at which the hierarchical data is stored. It is a controller. Numeral 193 denotes a quantization code decompressor for receiving the respective hierarchical data output from the read controller 192 and restoring the original first to fourth code data. It is a quantized code decompressor for restoring a quantized code while allocating a predetermined value to hierarchical data not read from the device 192 according to the missing hierarchical data.

194 is a first inverse quantizer for receiving the first code data output from the quantized code decompressor 193 and restoring the first band signal, and 195 is a quantized code decompressor 193. The first inverse quantizer 196 that receives the second code data output from and restores the second band signal,
The third inverse quantizer 197 that receives the third code data output from the quantized code decompressor 193 and restores the third band signal includes the fourth dequantizer 197 output from the quantized code decompressor 193. Is a fourth inverse quantizer which receives the code data of the fourth band and restores the fourth band signal.

Reference numeral 198 denotes a band synthesizer that receives each band signal and synthesizes the original digital signal. A D / A converter 199 receives the output of the band synthesizer 198 and converts the digital signal into an analog signal.

FIG. 36 shows that when the number of bits allocated to each band is 6, 4, 3, and 3, respectively, the quantization code decompressor 193 converts the first to fourth hierarchical data into each band. FIG. 9 shows a state of restoring to the code data of FIG. The number in each frame in FIG. 36 is a number indicating which layer, and indicates the first code data, the second code data, the third code data, and the fourth code data in order from the left column. ing. In FIG. 36, the first hierarchical data is 4-bit data of 4 bits on the MSB side of the first code data, and the second hierarchical data is the second L of the first code data.
The BS1 bit and the MSB side 3 bits of the second code data are a total of 4 bit data. The third hierarchical data is the MSB side 2 bits of the third code data and the MSB side 2 of the fourth code data.
A total of four bits of data, and the fourth hierarchical data are a first LSB1 bit of the first code data, a first LSB1 bit of the second code data, and a first LSB1 of the third code data.
A total of 4 bits and the first LSB1 bit of the fourth code data
Bit data is restored to code data.

FIG. 37 shows that when the number of bits allocated to each band is 6, 4, 3, and 3, respectively, the quantization code decompressor 193 converts the first to fourth hierarchical data into This figure shows a state of restoring to band code data, but shows a process when the read controller 192 does not read the fourth hierarchical data. The numeral in each frame in FIG. 37 is a numeral indicating which layer, and the first code data and the second code data are arranged in order from the left column.
, The third code data, and the fourth code data. Here, since the fourth hierarchical data has not been read, the value “L”, that is, the logical value 0 is assigned.

Similarly, FIG. 38 shows that when the number of bits allocated to each band is 6 bits, 4 bits, 3 bits, and 3 bits, respectively, the quantization code decompressor 193 operates in the first to fourth layers. The figure shows a state in which data is restored to coded data of each band.
This shows a process when the fourth hierarchical data and the third hierarchical data are not read. The number in each frame in FIG. 38 is a number indicating which layer, and represents the first code data, the second code data, the third code data, and the fourth code data in order from the left column. ing. Here, since the fourth hierarchical data and the third hierarchical data have not been read, the value “L”, that is, the logical value 0 is assigned.

Similarly, FIG. 39 shows that when the number of bits allocated to each band is 6 bits, 4 bits, 3 bits, and 3 bits, respectively, the quantization code decompressor 193 operates in the first to fourth layers. The figure shows a state in which data is restored to coded data of each band.
It shows a process when the fourth hierarchical data, the third hierarchical data, and the second hierarchical data are not read.
The number in each frame in FIG. 39 is a number indicating which layer, and indicates the first code data, the second code data, the third code data, and the fourth code data in order from the left column. ing. Here, since the fourth hierarchical data, the third hierarchical data, and the second hierarchical data have not been read, values other than the second LSB of the first code data are values “L”, that is, logical values 0.
Is assigned. The second LSB of the first code data is assigned a value “H”, that is, a logical value 1, which is
In the code data of each band, if two or more bits on the LSB side are discarded and at least one MSB bit of the code data is stored, the most significant bit of the discarded bits is a logical value 1 Is assigned in advance. Such a rule is provided in order to obtain a decoded signal in an intermediate case from a case where all the bits discarded in the band are logical values 0 to a case where all the bits are logical values 1, As a result, even when the lower layer data is discarded, the deterioration of the decoding quality can be reduced.

FIG. 40 shows the band synthesizer 198 shown in FIG.
FIG. 3 is a block diagram illustrating a configuration example of FIG. As shown in FIG. 40, the band synthesizer 198 is formed of a QMF filter bank and is a band splitter that has been widely used in the past (“Digital Signal Processing Handbook, edited by IEICE, pp.135-137”). 1993 "). In the present embodiment, the QMF filter bank as described above is used as an example of the band splitter. In addition, a polyphase filter bank or a hybrid polyphase filter bank performed by the MPEG audio coding algorithm or the like is used. Phase / MDC
The one using a T filter bank (ISO / IEC
11172-3: 1993).

FIG. 41 is a diagram showing a state of a data storage area in which hierarchical data is recorded. This is the first of the present invention.
FIG. 11 is the same as FIG. 10 showing the state of the data storage area recorded by the digital signal recording device according to the embodiment.

FIG. 42 is a diagram showing the contents of auxiliary information for hierarchical data. This is the same as FIG. 11 showing the state of the auxiliary information storage area recorded by the digital signal recording device according to the first embodiment of the present invention.

The operation of the digital signal reproducing apparatus configured as described above will now be described with reference to FIGS.
This will be described with reference to FIG.

In FIG. 35, first, the reading controller 1
Reference numeral 92 reads the auxiliary information stored in the auxiliary information storage area and analyzes how each layer data is stored in the data storage area. For example, FIG.
When the auxiliary information as shown in (1) is read, it is analyzed as follows.

At the time of data recording, first, first hierarchical data is stored in an area from address 0000 to address 0FFF, second hierarchical data is stored in an area from address 1000 to address 1FFF, and is stored in an area from address 2000 to address 2FFF. The third hierarchical data is stored, the fourth hierarchical data is stored in the area from address 3000 to address 3FFF, and when the data storage area becomes full, the area from address 2000 to address 2FFF is stored. And address 3000 to address 3
The FFF area is opened, the first hierarchical data is stored in the area from address 2000 to address 2FFF, the second hierarchical data is stored in the area from address 3000 to address 3FFF, and the data storage area is full memory. , The area from address 3000 to address 3FFF is released, and the first hierarchical data is stored in the area from address 3000 to address 3FFF.
In this state, it is confirmed that the recording process has been completed.

Therefore, the reading controller 192 first
The data stored in the area from address 0000 to address 0FFF is sequentially read as the first hierarchical data, and the data stored in the area from address 1000 to address 1FFF is sequentially read as the second hierarchical data. The first hierarchical data and the second hierarchical data are output to the encoding / decoding device 193. Quantization code decoder 193
Since the third layer data and the fourth layer data are missing from the received layer data, the code data of each band is restored according to FIG.

Next, the first dequantizer 194 to the fourth dequantizer 197 dequantize the code data of each band, respectively, and convert the first band signal to the fourth band signal. A band signal is generated and sent to band synthesizer 198. The band synthesizer 198 decodes the band signal combination from the first band signal to the fourth band signal into an original digital signal, and the D / A converter 199 converts the signal into an analog signal and outputs the analog signal.

When all data stored in the area from address 0000 to address 1FFF has been read,
Next, the data stored in the area from address 2000 to address 2FFF is sequentially read as first hierarchical data, and the first hierarchical data is output to the quantization code decoder 193. Since the second layer data, the third layer data, and the fourth layer data are missing from the received layer data, the quantization code decoder 193 converts the code data of each band according to FIG. Restore.

Next, the code data of each band is inversely quantized by the first inverse quantizer 194 to the fourth inverse quantizer 197, and the first to fourth band signals from the first band signal to the fourth band signal are dequantized. A band signal is generated and sent to band synthesizer 198. The band synthesizer 198 decodes the band signal combination from the first band signal to the fourth band signal into an original digital signal, and the D / A converter 199 converts the signal into an analog signal and outputs the analog signal.

When all data stored in the area of address 2FFF from address 2000 has been read,
Next, data stored in the area from address 3000 to address 3FFF is sequentially read as first hierarchical data, and the first hierarchical data is output to the quantization code decoder 193. Since the second hierarchical data, the third hierarchical data, and the fourth hierarchical data are missing from the received hierarchical data, the quantization encoder / decoder 193 obtains, according to FIG.
The code data of each band is restored.

Next, the first dequantizer 194 to the fourth dequantizer 197 dequantize the code data of each band, respectively, and convert the first band signal to the fourth band signal. A band signal is generated and sent to band synthesizer 198. The band synthesizer 198 decodes the band signal combination from the first band signal to the fourth band signal into an original digital signal, and the D / A converter 199 converts the signal into an analog signal and outputs the analog signal.

As described above, according to this embodiment, the data storage area for storing the hierarchically encoded hierarchical data and the auxiliary information storage area for storing the auxiliary information indicating the attribute of the stored data are provided. The solid-state memory and the hierarchical data stored in the solid-state memory, wherein the hierarchical data and the auxiliary information indicating the attribute of the hierarchical data are recorded by the digital signal recording device of the present invention. A hierarchical decoder for reading auxiliary information representing an attribute of the hierarchical data and decoding the original digital signal in accordance with the hierarchical level of the hierarchical data; and an auxiliary information in the solid-state memory inside the hierarchical decoder. A reading controller for reading auxiliary information stored in the storage area and sequentially reading hierarchical data stored in the data storage area in the solid-state memory based on the auxiliary information; Therefore, the data recorded by the digital signal recording apparatus of the present invention, it is possible to decode read efficiently.

[0191]

As described above , according to the digital signal recording apparatus of the first aspect , if there is a margin in the memory capacity with respect to the recording time length , all the hierarchical data are retained, so that high sound quality can be obtained. Recording can be performed, and even if the memory becomes full, writing is automatically stopped from the lower level,
Since the data in the upper layer is overwritten, the recording time can be efficiently extended by extremely simple processing.
That is, while maintaining the recording quality as much as possible, the recording time can be efficiently extended, and the data is effectively stored in the solid-state memory, so that the solid-state memory can be effectively used. The digital signal recording device according to the second aspect corresponds to the case where N is 2 in the first aspect, and both the first hierarchical data and the second hierarchical data are stored in the memory by extremely simple address control. Writing can be performed, and based on a very simple criterion of whether or not the write address of the second hierarchical data matches the write address of the first hierarchical data, the lower hierarchical (in this case, the second hierarchical) data is determined. The recording time can be extended by disposal processing. Further, the digital signal recording device according to the third aspect corresponds to the case where N is 3 in the first aspect. Even when the number of layers is three, the first, second, and
Writing to the memory can be performed with very simple address control for the third hierarchical data, and whether or not the write address of the third hierarchical data matches the write address of the first or second hierarchical data is determined. The recording time can be extended by discarding the lower hierarchical data by a very simple criterion of whether or not the write address of the hierarchical data of the first hierarchical data coincides with the write address of the first hierarchical data. The digital signal recording apparatus according to claim 4 corresponds to the case where N is 4 in claim 1, and even if the number of layers is 4, the first, second, third, and fourth layers The data can be written to the memory by extremely simple address control, and the write address of the fourth hierarchical data is the first, second, or third address.
Whether the write address of the third hierarchical data matches the write address of the first or second hierarchical data.
The discard processing of the lower hierarchical data is performed based on a very simple criterion of whether the write address of the second hierarchical data matches the write address of the second hierarchical data or not. Can extend the recording time. Further, in the digital signal recording apparatus according to the fifth aspect, N is 5 in the first aspect.
In the case where the hierarchical level is 5, even the first, second, third, fourth, and fifth hierarchical data can be written into the memory with very simple address control. Whether the write address of the fifth hierarchical data matches the write address of the first, second, third, or fourth hierarchical data, whether the write address of the fourth hierarchical data is the first, second, or third Whether the write address of the hierarchical data matches the write address of the third hierarchical data, whether the write address of the third hierarchical data matches the write address of the first or second hierarchical data, and whether the write address of the second hierarchical data is the first When recording by discarding lower layer data, it is based on a very simple criterion of whether or not it matches the write address of the lower layer data.
Can be extended . According to the digital signal recording device of the present invention , the recording time can be efficiently extended while the recording quality is maintained as much as possible in the multi-pulse encoding method, and the data is effectively stored in the solid-state memory. Therefore, the solid-state memory can be effectively used.

In the digital signal recording apparatus according to the second aspect of the present invention, if hierarchical data higher than itself has already been written in the write controller at the next address to be written, the write processing is performed at that time. When the memory is full, the writing is automatically stopped from the lower hierarchy, and the recording time can be efficiently extended by extremely simple processing.

In the digital signal recording apparatus according to the third aspect of the present invention, the address at which the writing of the hierarchical data is stopped is determined in advance, so that the writing process can be stopped in an arbitrary order regardless of the number of layers. it can.

Further, according to the digital signal reproducing apparatus of the present invention, a data storage area for storing hierarchically encoded hierarchical data, and an auxiliary information storage area for storing auxiliary information indicating an attribute of the stored data. Wherein the hierarchical data and the auxiliary information indicating the attribute of the hierarchical data are respectively stored in a solid-state memory recorded by the digital signal recording device of the present invention, the hierarchical data stored in the solid-state memory, and And a hierarchical decoder for reading auxiliary information representing the attribute of the hierarchical data and decoding the original digital signal in accordance with the hierarchy of the hierarchical data. The auxiliary decoder in the solid-state memory is provided inside the hierarchical decoder. Reading control for reading auxiliary information stored in the information storage area and sequentially reading hierarchical data stored in the data storage area in the solid-state memory based on the auxiliary information By providing the data recorded by the digital signal recording apparatus of the present invention,
It is possible to read and decode efficiently.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a digital signal recording device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a configuration of a band splitter according to the embodiment.

FIG. 3 is a diagram showing a first example of hierarchical division;

FIG. 4 is a diagram showing a second example of hierarchical division;

FIG. 5 is a flowchart illustrating the operation of the write controller according to the embodiment;

FIG. 6 is a diagram showing a state of the data storage area when the data storage area becomes a memory full state for the first time during data recording;

FIG. 7 is a diagram showing the contents of auxiliary information when the data storage area becomes full in memory for the first time during data recording;

FIG. 8 is a diagram showing a state of the data storage area when the data storage area becomes the memory full state for the second time during data recording.

FIG. 9 is a diagram showing the contents of auxiliary information when the data storage area is full of memory for the second time during data recording.

FIG. 10 is a diagram showing a state of a data storage area at the end of data recording.

FIG. 11 is a diagram showing the contents of auxiliary information at the end of data recording.

FIG. 12 is a block diagram illustrating a configuration of a digital signal recording device according to a second embodiment of the present invention.

FIG. 13 is a diagram showing a third example of hierarchical division;

FIG. 14 is a diagram showing a fourth example of hierarchical division;

FIG. 15 is a diagram showing an example of a state in which information indicating a bit allocation pattern for each predetermined time interval is stored in an auxiliary information storage area;

FIG. 16 is a block diagram illustrating a configuration of a digital signal recording device according to a third embodiment of the present invention.

FIG. 17 is a block diagram showing a configuration of a digital signal recording device according to a fourth embodiment of the present invention.

FIG. 18 is a diagram showing input and output of the multi-pulse encoder according to the embodiment.

FIG. 19 is a diagram illustrating a state in which the output of the multi-pulse encoder is hierarchically divided.

20A is a diagram showing a data storage area in the fifth embodiment. FIG. 20B is a diagram showing a data writing process after the data storage area is full in the fifth embodiment.

21A is a diagram showing a data storage area in the sixth embodiment. FIG. 21B is a diagram showing a data writing process after the data storage area is full in the sixth embodiment.

22A is a diagram showing a data storage area in the seventh embodiment. FIG. 22B is a diagram showing a data writing process after the data storage area is full in the seventh embodiment.

23A is a diagram showing a data storage area in the eighth embodiment. FIG. 23B is a diagram showing a data writing process after the data storage area is full in the eighth embodiment.

FIG. 24A is a diagram showing a data storage area in the ninth embodiment. FIG. 24B is a view showing data after the entire data area is filled with first to third hierarchical data in the ninth embodiment. (C) shows the data writing process after the entire data area is filled with the first and second hierarchical data in the ninth embodiment. (D) shows the ninth embodiment. FIG. 7 is a diagram showing a state in which an entire data area is full of first hierarchical data in an example

FIG. 25A is a diagram showing a data storage area in the tenth embodiment. FIG. 25B is a diagram showing a data writing process after the data area storing the third hierarchy in the tenth embodiment becomes full. FIG. 14C shows that all the data areas in the tenth embodiment are first to first.
FIG. 11D shows a data writing process after the second hierarchical data is full. FIG. 10D shows a state where the entire data area is full of the first hierarchical data in the tenth embodiment. () Shows a process of writing the first to third hierarchical data in the tenth embodiment when the bit lengths of the respective hierarchies are not equal.

FIG. 26A is a diagram showing a data storage area according to the eleventh embodiment. FIG. 26B is a diagram showing all data areas in the eleventh embodiment.
FIG. 13C shows a data writing process after the fourth hierarchical data is full. In the eleventh embodiment, FIG.
FIG. 11D shows a data writing process after the third hierarchical data is full. FIG.
FIG. 11E shows a data writing process after the second hierarchical data is full. FIG. 11E shows a state where the entire data area is full of the first hierarchical data in the eleventh embodiment.

FIG. 27A is a diagram showing a data storage area in the twelfth embodiment. FIG. 27B is a diagram showing a data writing process after the data area for storing the fourth hierarchy is full in the twelfth embodiment. FIG. 12C shows a data writing process after the data area storing the third hierarchy in the twelfth embodiment is full. FIG. 10D shows all data areas in the twelfth embodiment having the first data area. ~
FIG. 11E shows a data writing process after the second hierarchical data is full. FIG. 10E shows a state in which the entire data area is full of the first hierarchical data in the twelfth embodiment.

FIG. 28A is a diagram showing a data storage area in the thirteenth embodiment. FIG. 28B is a diagram showing all data areas in the thirteenth embodiment.
FIG. 13C shows a data writing process after data is filled with the fifth hierarchical data. FIG.
FIG. 12D shows a data writing process after the fourth hierarchical data is full. FIG.
FIG. 14E shows a data writing process after the third hierarchical data is full. FIG.
FIG. 7 is a diagram showing a data writing process after the second hierarchical data is full.

FIG. 29A is a diagram showing a data storage area in the fourteenth embodiment. FIG. 29B is a diagram showing a data writing process after the data area for storing the fifth hierarchy is full in the fourteenth embodiment. FIG. 14C shows the data writing process after the data area storing the fourth hierarchy in the fourteenth embodiment is full. FIG. 14D shows the third hierarchy stored in the fourteenth embodiment. FIG. 14E shows a data writing process after the data area is full. FIG.
FIG. 7 is a diagram showing a data writing process after the second hierarchical data is full.

FIG. 30 is a block diagram showing a configuration of a digital signal recording device according to a fifteenth embodiment.

FIG. 31 is a flowchart showing the flow of the operation of the write controller.

FIG. 32 is a flowchart showing a flow of a second operation of the write controller.

FIG. 33 is a block diagram illustrating a configuration of a digital signal recording device according to a sixteenth embodiment.

FIG. 34 is a block diagram showing a configuration of a digital signal recording device according to a seventeenth embodiment.

FIG. 35 is a block diagram showing a configuration of a digital signal reproducing apparatus according to an eighteenth embodiment.

FIG. 36 is a diagram showing a state in which hierarchically divided data is restored to the original quantization code.

FIG. 37 is a diagram illustrating a state where hierarchical data is restored to a quantized code when fourth hierarchical data is missing;

FIG. 38 is a diagram showing a state in which hierarchical data is restored to a quantized code when third and fourth hierarchical data are missing.

FIG. 39 is a diagram illustrating a state where hierarchical data is restored to a quantized code when second, third, and fourth hierarchical data are missing;

FIG. 40 is a block diagram showing the configuration of a band combiner according to the embodiment.

FIG. 41 is a diagram showing a state of a data storage area in which hierarchical data is recorded.

FIG. 42 is a diagram showing the contents of auxiliary information for hierarchical data

[Explanation of symbols]

11, 21, 31, 41 A / D converter 12, 22, 32 Band splitter 13, 23, 33 First quantizer 14, 24, 34 Second quantizer 15, 25, 35 Third Quantizers 16, 26, 36 Fourth quantizers 17, 27, 37, 43 Hierarchical dividers 18, 28, 38, 45, 191, 302, 335, 3
46 solid-state memory 19, 29, 39, 44, 301, 334, 345 write controller 30, 40 adaptive bit allocator 42 multipulse encoder 192 read controller 193 quantization code decompressor 194 first inverse quantization 195 Second inverse quantizer 196 Third inverse quantizer 197 Fourth inverse quantizer 198 Band combiner 199 D / A converter 300, 330 Layer encoder 331, 344 Layer number selector 332 Decoder 333 Difference signal evaluator 340 Band division hierarchical encoder 341 First band data evaluator 343 Nth band data evaluator 342 Second band data evaluator

Continuing on the front page (72) Inventor Tsuneo Tanaka 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. References JP-A-2-282799 (JP, A) JP-A-5-35295 (JP, A) JP-A-64-53642 (JP, A) JP-A-2-305053 (JP, A) 7-93892 (JP, A) JP-A-6-164409 (JP, A) JP-A-7-131357 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G10L 9/18 G10L 7/04 G10L 9/14 G11B 20/10 301

Claims (6)

(57) [Claims] 1. A hierarchical encoder (12-17), a recording device (18),
A digital signal recording device comprising a writing controller (19).
Thus, the hierarchical encoder (12-17) converts the input digital signal into
Signs are assigned to the hierarchical data divided from the first to the Nth hierarchical order.
The recording device (18) has a data storage area and an auxiliary information storage area.
And the data storage area is encoded by the hierarchical encoder (12-17)
Hierarchical data is stored, and the auxiliary information storage area
Displays the data storage area in which the layer data was stored.
The auxiliary controller stores the auxiliary information, and the write controller (19) operates in a predetermined address order.
Write each hierarchical data and its auxiliary information to the recording device (18)
Only, the write address of hierarchical data with lower hierarchical order is
When it matches the hierarchical data with the higher hierarchical rank,
Stop writing hierarchical data, and
Digital signal recording device that releases a part of the area of the lower hierarchical data . 2. A predetermined address of a write controller (19).
The dress order is such that the first hierarchical data is transferred from address A to address B.
And store the second hierarchical data from address B to address A.
The digital signal recording device according to claim 1, which is stored in the ground . 3. A predetermined address of a write controller (19).
The dress order is such that the first hierarchical data is transferred from address A to address B.
When address B is reached, address D
From the address C to the address A from the address C to the second hierarchical data.
And address D to address C are stored alternately.
Digital signal recording apparatus according to claim 1 that. However, A <B, C <D (A> B, C> D) 4. A predetermined address of a write controller (19).
The dress order is such that the first hierarchical data is transferred from address A to address B.
When address B is reached, address D
From the address C to the address D from the address C to the address D.
And store the third hierarchical data from address B to address A
Location, address D to address C alternately stored
Then, the fourth hierarchical data is transferred from address A 'to address A.
Address or address B, address C '
2. The digital signal recording apparatus according to claim 1, wherein the digital signal is stored alternately at an address C or an address D. However, A <A '<B, C <C'<D(A> A '> B, C>C'> D) 5. A predetermined address of a write controller (19).
The dress order is such that the first hierarchical data is transferred from address A to address B.
When address B is reached, address D
To address C, and when address C is reached,
From the address E to the address F, the second hierarchical data is stored from the address E to the address F.
When address F is reached, address C
From the address C to the address D from the address C to the address D.
And store the fourth hierarchical data from address B to address A.
Address, address D to address C, address F
From the address A 'to the address A , and the fifth hierarchical data is stored alternately from the address A' to the address A.
Address or address B, address C '
Address from address C or D, address E '
2. The digital signal recording apparatus according to claim 1, wherein the digital signal is stored in an address E or an address F alternately . Where A <A ′ <B, C <C ′ <D, E <E ′ <F (A> A ′> B, C> C ′> D, E> E ′> F) 6. The hierarchical encoder (12-17), wherein an LPC synthesis filter is provided.
Outputs pulse information divided into filter coefficients and hierarchical data
To a multi-pulse coder (42), pulse information consists amplitude value and position of the pulse, hierarchical order, a request that is determined based on the amplitude value of the pulse
Item 6. The digital signal recording device according to any one of Items 1 to 5 .