JPH07253564A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To provide a liquid crystal display device adopting power source level shift drive and realizing safe operation insurance, potential shift interval reduction and power consumption reduction in a signal line drive circuit. CONSTITUTION:This device is provided with plural pixel electrodes arranged on a substrate, signal lines D and gate lines G arranged between the pixel electrodes, switches arranged between the pixel electrodes and the signal lines and on/off controlled by the gate lines, a signal line drive means 1 for applying a signal voltage to the signal lines, a gate line drive means 4 for driving the switch by the gate line, a power source potential control means 6 for shifting respective potentials of a first power source and a second power source, whose potential is lower than the first power source, supplied to the signal line drive means by a fixed value according to the signal voltage applied on the pixel electrode, a power source supply control means 5 for separating at least one side of the first power source and the second power source from the signal line drive means when the potentials of the first power source and the second power source are shifted and a capacitor C inserted between the first power source and the second power source.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type display device, and more particularly to a liquid crystal display device having an improved drive circuit.

[0002]

2. Description of the Related Art With the development of a highly information-oriented society in recent years, the role of a display for displaying the information is also increasing, and the display has high definition, multi-gradation, downsizing, low power consumption, and low cost. Became strongly desired. Under such circumstances, many types of displays are currently proposed and put into practical use. Among them, the active matrix type liquid crystal display device has been attracting attention as a display satisfying the above requirements.

As a method of driving an active matrix type liquid crystal display device, a method of driving a counter electrode by direct current using an integrated circuit (IC) of a medium breakdown voltage process in a signal line driving circuit portion,
A method of alternating-current driving the counter electrode by using an IC having a low withstand voltage process in the signal line driving circuit section, and a proposal by the present inventors (Kano, Tsuchida, Suzuki, Okumura, Suzuki, “Signal line inversion driving by 5V driver IC Review, "1993 Television Society Annual Conference Proceedings, pp. 37-38, 199.
July 3rd. ) Described above, there is a method (hereinafter referred to as power supply level shift drive) of using a low withstand voltage process IC in the signal line drive circuit unit to direct-current drive the counter electrode to shift the power supply potential of the signal line drive circuit unit. In particular, the power supply level shift driving has recently attracted attention as a driving method for realizing low cost and low power consumption of an active matrix type liquid crystal display device.

In this power supply level shift drive, an IC of a low withstand voltage process can be used in the signal line drive circuit portion, and although there is an advantage that the counter electrode can be driven by direct current, the power supply potential of the signal line drive circuit portion is shifted. At this time, depending on the timing of the shift of the power supply potential, a voltage higher than the withstand voltage may be applied to the IC of the signal line drive circuit portion, and the IC may be destroyed. Moreover, since the power supply potential is shifted, the power supply is easily affected by noise. Therefore, a bypass capacitor is inserted between the first power supply and the second power supply (between V _{DD and} V _SS ) supplied to the signal line drive circuit unit to absorb potential fluctuations in the signal line drive circuit unit. At the same time, when shifting the power supply potential, the first power supply V _DD and the second power supply V _{SS of the} signal line drive circuit section
Is devised so that a voltage higher than the breakdown voltage is not applied with V _DD = V _SS .

[0005]

However, in the conventional power supply level shift drive, there is a problem that power consumption increases because the bypass capacitor is charged and discharged.
In addition, it takes a long time to charge and discharge, which causes an increase in the power supply potential shift period.

The present invention has been made in consideration of the above circumstances, and is a liquid crystal display device to which power level shift driving is applied, in which a safe operation of a signal line drive circuit section is ensured and a power potential shift period is shortened. An object of the present invention is to provide a liquid crystal display device that realizes low power consumption.

[0007]

In a liquid crystal display device according to the present invention (claim 1), a plurality of pixel electrodes arranged on a substrate, signal lines respectively arranged between these pixel electrodes, and Between the pixel electrodes, gate lines respectively arranged in a direction orthogonal to the signal lines, and switching elements respectively arranged between the pixel electrodes and the signal lines and on / off controlled by the gate lines, A signal line driving unit that applies a signal voltage to the signal line, a gate line driving unit that drives the switching element using the gate line, and the signal line driving unit according to a signal voltage to be written to the pixel electrode. Connected to the power supply potential control means for shifting the potential of the first power supply and the potential of the second power supply lower than this potential by a constant value, respectively. Serial power supply voltage control means of the potential and the second power supply potential of said first power source when each is shifted by a predetermined value, the first power source and the second
Power supply control means for disconnecting at least one of the power supplies from the signal line drive means, and a capacitor inserted between the first power supply and the second power supply output from the power supply control means. It is characterized by being done.

In a liquid crystal display device according to the present invention (claim 2), a plurality of pixel electrodes arranged on a substrate, signal lines respectively arranged between the pixel electrodes, and the pixel electrodes are arranged between the pixel electrodes. A gate line arranged in a direction orthogonal to the signal line, a switching element arranged between the pixel electrode and the signal line and turned on / off by the gate line, and a signal voltage applied to the signal line. A signal line driving means for applying a voltage, a gate line driving means for driving the switching element using the gate line, and a first line supplied to the signal line driving means according to a signal voltage to be written to the pixel electrode. A first operation of shifting the potential of the power supply by a constant value, or disconnecting the first power supply from the signal line driving means for a predetermined time according to the signal voltage,
After the potential of the first power source is shifted by a certain value or at the same time, the potential of the first power source is shifted, and at the same time, one of the second operations for connecting the first power source to the signal line driving means is performed. Means and a third operation of shifting the potential of a second power supply lower than the first power supply supplied to the signal line driving means by a constant value in accordance with a signal voltage to be written to the pixel electrode, or The second power source is disconnected from the signal line driving means for a predetermined time according to the signal voltage, and the potential of the second power source is shifted by or after being shifted by a constant value. Second power supply control means for performing one of the fourth operations connected to the signal line drive means, the first power supply and the second power supply output from the first power supply control means. Control means And a capacitor inserted between the second power source output from the second power source, and the first power source control means and the second power source control means cooperate with each other to perform the second operation. Further, at least one of the fourth operation and the operation of shifting the potential by a constant value are performed after the power supply is once disconnected from the signal line driving means.

[0009]

In the present invention (claim 1), when the power supply potential control means shifts the potentials of the first power supply and the second power supply supplied to the signal line driving means, the power supply control means makes the first power supply control means Since at least one of the power source and the second power source is separated from the signal line driving means and the bypass capacitor, it is stored in the bypass capacitor inserted between the first power source and the second power source supplied to the signal line driving means. It is possible to shift the power supply potential of the signal line driving means while keeping the electric charges substantially constant.

In the present invention (claim 2), the first power supply control means shifts the potential of the first power supply supplied to the signal line driving means, and the second power supply control means operates the second power supply.
When the potential of the power source is shifted, the first power source control unit disconnects the first power source from the signal line driving unit and the bypass capacitor, and the second power source control unit sets the second power source to the signal line driving unit. Since at least one of the operation of disconnecting from the bypass capacitor is performed, the electric charge accumulated in the bypass capacitor inserted between the first power supply and the second power supply supplied to the signal line driving means is kept substantially constant. The power supply potential of the signal line driving means can be shifted as it is.

Therefore, according to the present invention, when shifting the potentials of the first power supply and the second power supply supplied to the signal line driving means, it is possible to suppress the generation of the charge / discharge current of the bypass capacitor. Therefore, power consumption can be reduced.

Further, since the electric charge of the bypass capacitor is kept substantially constant, the period required to shift the power supply potential can be extremely shortened, and furthermore, the first power supply and the second power supply can be used when the power supply potential is shifted. Since at least one of the power supplies is disconnected from the signal line driving means, stable power supply level shift driving can be performed without applying a voltage higher than the withstand voltage to the signal line driving means. Therefore, it is possible to obtain a liquid crystal display device that realizes high image quality, low power consumption, and stable power supply level shift driving.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing a main configuration of a liquid crystal display device according to a first embodiment of the present invention. This liquid crystal display device is an active matrix type liquid crystal display device to which power level shift driving is applied, and includes a signal line driving unit 1 (1 ₁ to 1 _n ), a control unit 2, a matrix substrate unit 3, a gate line driving unit 4 ( 4 ₁ to 4 _L ), the power supply control unit 5,
The power supply potential shift unit 6 is provided. Each component, for example, the signal line drive unit 1 and the gate line drive unit 4 may be configured as a dedicated IC.

The matrix substrate section 3 includes pixel electrodes (not shown) arranged two-dimensionally on a glass substrate (not shown) and signal lines D (D ₁ ) arranged between the pixel electrodes.
~ D _m ), the gate lines G respectively arranged between the pixel electrodes
(G _{1 to} G _k ).

The signal line driving unit 1 is a circuit for outputting display data to the signal line, and includes a sampling pulse generating circuit using a multiplexer, a level shifter, a sample hold circuit using an analog switch and a sampling capacitor, and an operational amplifier and a hold. -A known circuit configuration including an output circuit using a capacitor (for example, Nikkei B
P company: circuit configuration disclosed in flat panel display 91).

The gate line driver 4 turns on a switching element (not shown) connected to a pixel electrode (not shown) to be displayed by using the gate line, and applies the display data to the pixel electrode. It is a circuit for.

The control unit 2 is a circuit for performing power level shift driving, and includes a video signal Sig, a control signal CONT, and a clock signal C input from a personal computer or the like.
It has a function of shifting LK, the start pulse signal Din, etc. according to the level of the signal voltage to be written in the pixel electrode. The signals Sig, CONT, CLK, and Din are respectively shifted to obtain the signals Sig ', CONT', and C.
LK 'and Din'. The circuit configuration of the control unit 2 is a known circuit configuration including an exclusive OR circuit, a capacitor, a buffer amplifier, a resistor, and the like (for example, Konno, Tsuchida, Suzuki, Okumura, Suzuki, “Signal line inversion driving by 5V driver IC. Examination ”,“ Preliminary Proceedings of Annual Conference of the Television Society of 1993 ”, pp37-38, July 1993.).

The power supply potential shift section 6 is composed of the signal line driving section 1
(1 ₁ to 1 _n ) is a circuit that shifts the power supply potential of the control unit 2 by a constant value.
It is composed of 4. The switch SW3 is provided with a high-potential first power supply V _DD1 and a low-potential first power supply V _DD2 , and the switch SW4 is provided with a high-potential second power supply V _SS1 and a low-potential second power supply V _SS2. 2 and the control signal CNT3 and the control signal CNT4 respectively, as shown in FIG. 2, when the potential of the first power supply V _{DD and} the potential of the second power supply V _SS are odd frames, V _DD = V _DD1 and V _SS = V _SS1 and V _DD = in the case of an even frame
Obtain a waveform such that V _DD2 and V _SS = V _SS2 . Here, the first power source V _DD1 = 12v in the odd frame,
It is assumed that the first power source V _DD2 = 7v in the even frame, the second power source V _SS1 = 7v in the odd frame, and the second power source V _SS2 = 2v in the even frame.

The power supply control section 5 includes a signal line drive section 1 (1 ₁ ...
1 _n ) and the potential V of the first power supply supplied to the control unit 2
Either or both of the _DD and the power supply of the potential V _SS of the second power supply are disconnected from the signal line driving unit 1 ( ₁₁ to 1 _n ) and the control unit 2, and between the power supplies (between V _DD and V _SS ). It is a control circuit for keeping constant the electric charge charged in the bypass capacitor C ₁ inserted in, and has a switch SW1 and a switch SW2. Switch SW1 and switch S
W2 is a control signal CNT1 and a control signal CN, respectively.
It is a switch controlled by T2. Signal line driver 1 (1
₁ to 1 _n ) and the power supply potential of the control unit 2 are constant (when not shifted), the switch SW1 and the switch S
Each W2 is on (short).

FIG. 3 shows specific examples of the switches SW1 and SW2. FIG. 3A shows an N channel MO.
This is an example using an S transistor, and FIG. 3B is an example using a P channel MOS transistor.
(C) is an example using a transmission gate. In addition to the above, the switches SW1 and SW2 of the power supply control unit 5 may be mechanical switches as well as electronic switches such as a clocked inverter circuit, and their control methods can be appropriately changed.

Signal lines D _{1 to} D _{m of the} matrix substrate section 3
Of these, the odd-numbered ones are the upper signal line driving units 1 ₁ to 1 _n-1 ,
The even-numbered ones are connected to the lower signal line drive units 1 ₂ to 1 _n . The signal line drive unit of the upper _{1 1 ~1 n-1} power (V _DD,
V _SS ) and various signals (Sig ', CONT', CLK
′, D _in ′) are collectively connected to the control unit 2. Further, V _DD , V _SS , the control signal CNT1 and the control signal CNT2 are connected to the power supply controller 5, and V _DD1 ,
The V _DD2 , V _SS1 , V _SS2 , the control signal CNT3, and the control signal CNT4 are connected to the power supply potential shift unit 6. Although the lower signal line drive units 1 ₂ to 1 _n are omitted in the figure, they are grouped together as in the upper unit, and a control unit 2 ′ (not shown).
Is connected to the lower power supply controller 5 '(not shown)
The power supply potential shift unit 6 '(not shown) is also connected in the same manner as the upper portion.

In addition, the gate line G of the matrix substrate portion 3
_{1 to} G _k are connected to the gate line driving units 4 ₁ to 4 _L. As a concrete example of the liquid crystal display device of the present embodiment, the XGA compatible device has 1024 signal lines and 768 gate lines.
There are four and three drive ICs with 256 outputs, respectively. In the case of HDTV-compatible ones, if the number of signal lines is 1920 and the number of gate lines is 1024, the number of drive ICs with 256 outputs is 8 and 4, respectively.

In the active matrix type liquid crystal display device having the above-mentioned structure, it is assumed that a positive voltage is written in the liquid crystal in odd frames and a negative voltage is written in the liquid crystals in even frames by using power level shift driving. In this case, the potentials of the power supplies V _DD and V _ss supplied to the signal line driving unit 1 (1 ₁ to 1 _n ) and the control unit 2 have a waveform as shown in FIG. However, as described above, V _DD = 1 in odd frames
2 v and V _SS = 7 _v, and V _DD = 7 _v and V _ss = 2 _{v for} even frames. The signal Sig input from the personal computer or the like by the control unit 2 is transmitted to the signal line drive unit 1 (1 ₁ to
1 _n ) and the voltage levels of the power supplies V _DD and V _SS of the control unit 2 are changed according to the signal Sig ′ shown in FIG. Further, the other various signals CONT, CLK, D _in are similarly changed according to the voltage level.

In the power supply level shift driving as described above, in this embodiment, the potentials of the power supplies V _DD and V _SS of the signal line driving unit 1 (1 ₁ to 1 _n ) and the control unit 2 are shown in FIG. As described above, when shifting from an even frame to an odd frame or from an odd frame to an even frame, one or both of the switch SW1 and the switch SW2 of the power control unit 5 are turned off (open). As a result, the charge charged in the bypass capacitor C ₁ inserted between the signal line driving unit 1 (1 ₁ to 1 _n ) and the power source of the control unit 2 (between V _DD and V _SS ) becomes the power source V _DD , It is also kept constant when V _SS shifts from the even frame to the odd frame or from the odd frame to the even frame. The switch SW1 and the switch SW2 of the power supply controller 5 are connected to the signal line driver 1 (1
After the potential shift of the power supply (V _DD , V _SS ) of the control unit 2 is completed ( ₁ to 1 _n ), the control unit 2 is turned on (short-circuited) again.

As described above, according to this embodiment, when shifting the potentials of the power supplies V _DD and V _SS of the signal line drive unit 1 and the control unit 2, the bypass capacitor C inserted between the power supplies V _DD and V _{SS. Since} the charge charged to ₁ is kept constant, the power supply potential shift period can be shortened and the power consumption of the signal line driving unit can be reduced. Further, when the potentials of the power supplies V _DD and V _SS are shifted, either one or both of the power supplies V _DD and V _SS is disconnected from the signal line drive unit 1 and the control unit 2, so that the power supply potential shift is prevented. At this time, a stable power supply level shift drive can be performed without applying a voltage higher than the withstand voltage to the signal line drive unit 1 and the control unit 2.

Moreover, even if either or both of the power supplies V _DD and V _SS are disconnected from the signal line driving unit 1 and the control unit 2, the electric charge of the bypass capacitor C ₁ inserted between the power supplies is not completely discharged. Since a certain potential difference is generated between V _DD and V _SS , the data stored in the signal line driving unit 1 and the control unit 2 can be held.

As a result, it becomes possible to stably carry out the power supply level shift driving with high image quality and low power consumption.
The present invention is not limited to the above embodiment. A signal line drive unit 1, a control unit 2, a matrix substrate unit 3 of a liquid crystal display device, a gate line drive unit 4, a power supply control unit 5,
The configuration of the power supply potential shift unit 6 can be changed as appropriate. Further, the present invention can be applied to a display device other than the active matrix type display device, for example, an electrostatic printer or the like that can display an image on the screen by changing the toner adsorption amount according to the pixel potential.

(Second Embodiment) Next, a liquid crystal display device according to a second embodiment of the present invention will be described. FIG. 4 is a diagram of an active matrix type liquid crystal display device according to the same embodiment, and this active matrix type liquid crystal display device is applied with power supply level shift driving as in the first embodiment. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The liquid crystal display device shown in FIG. 4 has a structure in which a power supply potential shift control unit 7 is provided instead of the power supply control unit 5 and the power supply potential shift unit 6 of the liquid crystal display device shown in FIG. The power supply potential shift control unit 7 includes switches SW5,
The switch SW6, the switch SW7, and the switch SW8 are configured, and the four switches SW5 to 8 are controlled by the control signals CNT5 to 8, respectively.

The power supply potential shift control section 7 shifts the power supply potentials of the signal line driving section 1 (1 ₁ to 1 _n ) and the control section 2 by a constant value, and at that time, the signal line driving section 1 (1 ₁ to 1 _n ). 1 _n )
One or both of the power supply (V _DD , V _SS ) of the control unit 2 and the control unit 2 are disconnected from the signal line drive unit 1 (1 ₁ to 1 _n ) and the control unit 2, and between the power supplies (between V _DD and V _SS ). It is a circuit that keeps the electric charge charged in the bypass capacitor C ₁ inserted in the constant. That is, the power supply potential shift control unit 7 has both the functions of the power supply control unit 5 and the power supply potential shift unit 6 of FIG.

FIG. 5 shows a concrete circuit configuration example of the power supply potential shift control section 7. As shown in FIG. 5, the P-channel MOS transistor 2 is turned on / off by the control signal CNT5.
4 and the N-channel MOS transistor 25 controlled by the control signal CNT6 are connected in series to correspond to the first power supply V _DD (first power supply control circuit), and controlled by the control signal CNT7. P-channel MOS transistor 26 and N-channel MOS transistor 27 controlled by control signal CNT8 are connected in series, and a circuit portion (second power supply control circuit) corresponding to second power supply V _SS is formed.

Here, an example of the control method of the circuit shown in FIG. 5 will be described. Here, an example in which the power supply V _DD is separated from the signal line driving unit 1 (1 ₁ to 1 _n ) and the control unit 2 during the power supply potential shift will be described.

First, V _DD1 , V _DD2 , V _SS1 and V shown in FIG.
_{SS2 is connected} to V _DD1 = 12v, V _DD2 = 7v, V
_SS1 = an 7v ,, V _SS2 = 2v, control signals CNT5 shown in FIG. 6, the control signal CNT6, control signals CNT7, and inputs a control signal CNT8 in the circuit of FIG. Then, as shown in FIG.
As is clear from the operation of the four MOS transistors forming the circuit of FIG. 6, the waveforms of the power supplies V _DD and V _SS of the signal line driving unit 1 (1 ₁ to 1 _n ) and the control unit 2 are as shown in FIG. Like

The high impedance state of V _DD shown in FIG. 6 is generated by turning off (opening) both MOS transistors 24 and 25 in FIG. 5 before shifting the potential of V _DD . That is, in this high impedance state, V _DD is disconnected from the signal line driving unit 1 ( ₁₁ to 1 _n ) and the control unit 2. Actually, since electric charges are stored in the bypass capacitor C ₁ of FIG. 4, even if V _DD is in a high impedance state, the potential difference between V _DD and V _SS is V = Q / C ₁ . Occurs. Here, Q is the amount of charge stored in the bypass capacitor C _1, V is a potential difference generated across the bypass capacitor C _1.

Therefore, the value of the bypass capacitor C ₁ is appropriately selected, and a sufficient potential difference for driving the signal line driving unit 1 (1 ₁ to 1 _n ) and the control unit 2 is provided across the bypass capacitor C _1. in Sasere occurs, the signal line drive unit 1 also be separated off power (1 ₁ to 1 _n) and the control unit 2 operates normally.

The value of the bypass capacitor C1 inserted between the power supplies of the signal line driving unit 1 is such that the signal line driving unit operates normally during the power supply potential shift period of the signal line driving unit 1.
One of the power supplies of the signal line driving unit 1 or both are separated from the signal line driving unit 1 by T ′, the maximum current consumption of the signal line driving unit 1 by I ′, image quality deterioration such as flicker and signal line driving. When the drop voltage of the power supply voltage of the signal line driving unit 1 which does not cause the malfunction of the IC is ΔV, the formula of C1> (I ′ * T ′) / ΔV must be satisfied. For example, when T ′ = 5 μsec I ′ = 100 mA ΔV = 500 mV, C1> 1 μF.

In the above example, V _{DD is set} to the signal line driving unit 1 (1
₁ to 1 _n ) and the control unit 2 are separated, but V _SS
Only, or V _DD, both the signal line drive unit of the V _{SS 1} (1 1
~ 1 _n ) and the control unit 2 may be separated. In such a case, CNT5, CNT6, CNT7, CNT
8 and waveforms of V _SS and V _DD are shown in FIGS.

Only V _SS is applied to the signal line driving unit 1 (1 ₁ to 1 _n )
And CNT5, CNT6, C when separated from the control unit 2
The waveforms of NT7, CNT8, V _SS and V _DD are shown in FIG.
CNT5, CNT6, CNT when both V _DD and V _SS are separated from the signal line driving unit 1 ( ₁₁ to 1 _n ) and the control unit 2
Waveforms of 7, CNT8, V _SS and V _DD are shown in FIG. 9, respectively.

As described above, according to the present embodiment, the power supply potentials (V _DD , V _SS ) of the signal line driving unit 1 (1 ₁ to 1 _n ) and the control unit 2 are used.
Potential) of the signal line driving unit 1 (1 _1-
1 _n ) and the power supply (V _DD , V _SS ) of the control unit 2 or both of them are separated from the signal line drive unit 1 (1 ₁ to 1 _n ) and the control unit 2 by a relatively simple circuit. It can be realized with a configuration.

The configuration of the power supply potential shift control section 7 is not limited to the above-mentioned embodiment, and the circuit configuration and its control method can be changed as appropriate. Of course, according to this embodiment, the same effect as that of the above-described first embodiment can be obtained.

(Third Embodiment) Next, a liquid crystal display device according to a third embodiment of the present invention will be described. FIG. 7 is a block diagram showing a circuit configuration of the active matrix type liquid crystal display device of the embodiment. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The active matrix type liquid crystal display device shown in FIG. 7 has a structure in which a noise prevention unit 8 is added to the active matrix type liquid crystal display device shown in FIG. Further, it is assumed that the active matrix type liquid crystal display device of FIG. 7 also applies the power supply level shift drive.

In this embodiment, the noise prevention unit 8 is composed of two resistors 28 and 29. The circuit configuration of the noise prevention unit 8 can be changed as appropriate, and a Schmitt trigger circuit, a flip-flop circuit, or the like may be used.

In this embodiment, the signal line driver 1 (1 ₁ to 1)
_n ) and the power supply potential (potentials of V _DD and V _SS ) of the control unit 2 to keep the electric charge charged in the bypass capacitor C ₁ constant, either the switch SW1 or the switch SW2 of the power supply control unit 5 Turn one off (open) or both off (open). After that, after the power supply potentials of the signal line driving unit 1 (1 ₁ to 1 _n ) and the control unit 2 (the potentials of V _DD and V _SS ) are shifted, the switch SW of the power supply control unit 5 is switched.
1 and the switch SW2 are both turned on (shorted). At this time, noise such as chattering, overshoot, or linking may occur in V _DD and V _SS at the time of power source potential shift, which may increase the period of power source potential shift. However, the active matrix liquid crystal display device shown in FIG. Then, noise such as chattering, overshoot, and linking generated at the time of power supply potential shift is removed by the noise prevention unit 8, and the power supply potential shift period can be further shortened.

Of course, according to this embodiment, the same effect as that of the above-mentioned first embodiment can be obtained. Here, in each of the above-described embodiments, the value of the bypass capacitor C ₁ is 0.1 μF in consideration of the avoidance of EMI received from the two floating power supplies _DD and V _SS and the stable operation of the signal line driving unit 1.
It is preferable to set in the range of up to 300 μF. In addition, considering the noise shielding of the power supply that is likely to appear, 1 μF to
It is more preferable to set it in the range of 150 μF.

Further, when comparing the conventional power supply level shift drive and the power supply level shift drive using the present invention, the power supply potential shift period can be shortened from 300 μsec to 5 μsec, and the bypass inserted between the power supplies of the signal line drive circuit. It has become possible to eliminate the power consumption of about 250 mW required to charge and discharge the capacitor C ₁ . However, as a condition, the value of the bypass capacitor between the 10-inch class VGA and the power supply of the signal line drive circuit was C ₁ = 100 μF. Further, the present invention is not limited to the above-described embodiments, and various modifications can be carried out without departing from the scope of the invention.

[0047]

According to the present invention (claim 1), the power supply control means is the first when the potential is shifted by the power supply potential control means.
Since at least one of the power source and the second power source is disconnected from the bypass capacitor, it is possible to shift the power source potential of the signal line driving means while keeping the charges accumulated in the bypass capacitor substantially constant.

In the present invention (claim 2), the first power supply control means shifts the potential of the first power supply and the second power supply control means shifts the potential of the second power supply. Since the power supply control means and the second power supply control means cooperate to disconnect at least one of the first power supply and the second power supply from the bypass capacitor, the signal line with the electric charge stored in the bypass capacitor kept substantially constant. The power source potential of the driving means can be shifted.

Therefore, according to the present invention, when shifting the potentials of the first power supply and the second power supply supplied to the signal line driving means, it is possible to suppress the generation of the charge / discharge current of the bypass capacitor. Therefore, power consumption can be reduced.

Further, since the electric charge of the bypass capacitor is kept substantially constant, the period required to shift the power supply potential can be extremely shortened, and moreover, the first power supply and the second power supply can be used in shifting the power supply potential. Since at least one of the power supplies is disconnected from the signal line driving means, stable power supply level shift driving can be performed without applying a voltage higher than the withstand voltage to the signal line driving means. Therefore, it is possible to obtain a liquid crystal display device that realizes high image quality, low power consumption, and stable power supply level shift driving.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a signal waveform diagram for explaining the operation of the embodiment.

FIG. 3 is a diagram showing a specific example of a switch of a power supply control unit used in the embodiment.

FIG. 4 is a block diagram showing a circuit configuration of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a specific example of a power supply potential shift control unit used in the same embodiment.

FIG. 6 is a signal waveform diagram for explaining the operation of the embodiment.

FIG. 7 is a block diagram showing a circuit configuration of a liquid crystal display device according to a third embodiment of the present invention.

FIG. 8 is a signal waveform diagram for explaining the operation of the second embodiment of the present invention.

FIG. 9 is a signal waveform diagram for explaining the operation of the embodiment.

[Explanation of symbols]

1 (1 ₁ to 1 _n ) ... Signal line drive section, 2 ... Control section, 3 ... Matrix substrate section of liquid crystal display device, 4 (4 ₁ to 4 _L ) ...
Gate line drive unit, 5 ... Power supply control unit, 6 ... Power supply potential shift unit, 7 ... Power supply potential shift control unit, 8 ... Noise prevention unit, 2
1 ... N-channel MOS transistor, 22 ... P-channel MOS transistor, 23 ... Transmission gate, 24 ... P
Channel MOS transistor, 25 ... N channel MO
S transistor, 26 ... P-channel MOS transistor, 27 ... N-channel MOS transistor, 28 ...
Resistance, 29 ... Resistance, D (D _{1 to} D _m ) ... Signal line of matrix substrate section 3, G (G _{1 to} G _K ) ... Gate line of matrix substrate section 3

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kohei Suzuki, 33, Shinisogo-cho, Isogo-ku, Yokohama-shi, Kanagawa, Ltd.

Claims (2)

[Claims] 1. A plurality of pixel electrodes arranged on a substrate, signal lines respectively arranged between these pixel electrodes, and gates respectively arranged between the pixel electrodes in a direction orthogonal to the signal lines. A line, and arranged between the pixel electrode and the signal line,
A switching element that is on / off controlled by the gate line; a signal line driving unit that applies a signal voltage to the signal line; a gate line driving unit that drives the switching element using the gate line; and the pixel electrode Power supply potential control means for shifting the potential of the first power supply and the potential of the second power supply lower than this potential supplied to the signal line driving means by a constant value in accordance with the signal voltage to be written into When the power supply potential control means shifts the potential of the first power supply and the potential of the second power supply by a constant value, the power supply potential control means is connected to the potential control means. Power supply control means for disconnecting at least one from the signal line drive means, the first power supply and the second power supply output from the power supply control means A liquid crystal display device characterized by being provided with a capacitor which is inserted between. 2. A plurality of pixel electrodes arranged on a substrate, signal lines arranged between the pixel electrodes, and gates arranged between the pixel electrodes in a direction orthogonal to the signal lines. A line, and arranged between the pixel electrode and the signal line,
A switching element that is on / off controlled by the gate line; a signal line driving unit that applies a signal voltage to the signal line; a gate line driving unit that drives the switching element using the gate line; and the pixel electrode A first operation of shifting the potential of the first power supply supplied to the signal line driving means by a constant value in accordance with the signal voltage to be written to, or the first power supply for a predetermined time in accordance with the signal voltage. Any of the second operations of disconnecting the first power source from the signal line driving means and shifting or shifting the potential of the first power source by a constant value at the same time as connecting the first power source to the signal line driving means. One of the first power supply control means for performing one of the two, and a second power supply which is lower than the first power supply supplied to the signal line driving means according to a signal voltage to be written to the pixel electrode.
Third operation of shifting the potential of the power source by a constant value, or disconnecting the second power source from the signal line driving means for a predetermined time according to the signal voltage, and setting the potential of the second power source to a constant value. A second power supply control means for performing either one of a fourth operation of connecting the second power supply to the signal line driving means after or at the same time as shifting, and the first power supply control. And a capacitor inserted between the first power supply output from the means and the second power supply output from the second power supply control means, the first power supply control means The second power supply control means cooperates to perform at least one of the second operation and the fourth operation, and the operation of shifting the potential by a constant value is performed by the power supply driving the signal line. Means A liquid crystal display device comprising to performing after once disconnected.