JPH07249014A - Multiprocessor system and terminal controller - Google Patents

Abstract

PURPOSE:To employ the same constitution for respective abnormality monitor parts and thus to reduce the hardware cost and software cost by providing the abnormality monitor parts for each processor, and displaying the occurrence of the abnormality on either of the processors when an abnormality detection signal is received. CONSTITUTION:The respective processors 10-12 are provided with the abnormality monitor parts 20-22, one to one, and the abnormality monitor parts 20-22 when detecting abnormality of the corresponding processors 10-12 send abnormality detection signals to a system control part 30. Further, the system control part 30 when receiving one of the abnormality detection signal displays which processor becomes abnormal. Thus, the system control part 30 when receiving the abnormality detection signal decides that one of the processors becomes abnormal and makes an alarm display. The abnormality monitor parts 20-22 need not send information showing which of the processors 10-12 becomes abnormal, and may have the same constitution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system in which a plurality of processors share the processing and execute the same, and more particularly to failure detection thereof.

[0002]

2. Description of the Related Art There is a multiprocessor system in which a plurality of processors perform processing in order to improve the reliability of information processing and the processing capacity. Such a multiprocessor system is a system in which the functions are distributed or the loads are distributed among the processors by executing the processing with a plurality of processors. And in a conventional multiprocessor system, one processor becomes the master processor,
This master processor was performing the above-mentioned distributed control and abnormality monitoring as a system.

[0003]

However, in the multiprocessor system as described above, since one processor performs abnormality monitoring as a multiprocessor, when an abnormality occurs in this master processor,
There was a problem that the entire system would stop functioning even though the other processors were normal.

Further, since the master processor monitors the abnormality, the processing executed by the master processor and the processing executed by other processors are different in the abnormality monitoring processing.
Therefore, the abnormality monitoring program cannot be shared. As a result, there is a problem that the cost of hardware for abnormality monitoring or the development cost of software will increase, and there is a demand for a multiprocessor system that can realize such reliability improvement and cost reduction. It had been.

[0005]

In order to solve the above-mentioned problems, the multiprocessor system and the terminal controller of the present invention are provided with an abnormality monitoring unit for each processor,
Each abnormality monitoring unit is configured to send an abnormality detection signal to the system control unit when detecting an abnormality in the corresponding processor. When the system control unit receives any abnormality detection signal, the system control unit displays that any one of the processors has an abnormality.

[0006]

In the multiprocessor system and the terminal controller of the present invention, when an abnormality occurs in a certain processor, the abnormality monitoring unit for monitoring the processor is
The abnormality is detected and an abnormality detection signal is sent to the system controller. Upon receiving the abnormality detection signal, the system control unit determines that an abnormality has occurred in any of the processors and displays an alarm. Therefore, the abnormality monitoring unit does not need to transmit information such as which processor has an abnormality, and the configuration of each abnormality monitoring unit can be the same and the configuration can be simplified.

[0007]

Embodiments of the present invention will now be described in detail with reference to the drawings. << Embodiment 1 >> FIG. 1 is a block diagram showing a configuration of a multiprocessor system as Embodiment 1 of the present invention. The system shown in the figure includes processors 10, 11, and 12, abnormality monitoring units 20, 21, and 22, a system control unit 30, and a system bus 40.

The processors 10, 11 and 12 are processors that share and execute processing as a multiprocessor system, and are connected to each other via a system bus 40. Further, each of the processors 10, 11 and 12 has a master control unit 10
a, 11a, 12a are provided. These master control units 10a, 11a, 12a, 11a, and 12a check an abnormality flag (which will be described later) of an abnormality monitoring unit other than the abnormality monitoring unit that monitors its own processor, and set one of the abnormality flags. If so, it has the function of restarting the system.

The abnormality monitoring units 20, 21, 22 are for monitoring the abnormality of each of the processors 10, 11, 12 and are composed of a watchdog timer, a program executed by each of the processors 10, 11, 12 and the like. Processor 10,
When the abnormalities 11 and 12 are detected, the abnormality detection signal is
It is configured to be sent to the system control unit 30 via the abnormality notification signal lines 50, 51, 52. Further, each of the abnormality monitoring units 20, 21, 22 is configured to set the abnormality flags 20a, 21a, 22a when an abnormality is detected.

The system control unit 30 includes an OR circuit 31,
The fault notification unit 32 and the display unit 33 are provided. The OR circuit 31 has, on its input side, the respective abnormality monitoring units 20, 21, 22.
Is connected to the abnormality notification signal lines 50, 51, 52 from which the other abnormality detection signals are input, and the OR operation of the abnormality detection signals from these signal lines 50 to 53 is performed. is there.

When the output signal from the logical sum circuit 31 is input, the fault notifying section 32 sends a display signal to the display section 33 and also sends a fault occurrence notifying signal to the outside of the system. . The display unit 33 includes a display lamp and the like, and is used for any one of the processors 10, 11, 12
It has a function as an alarm notifying that an abnormality has occurred.

Next, the operation of the first embodiment will be described. The abnormality monitoring units 20, 21, 22 perform abnormality monitoring of the corresponding processors 10, 11, 12 during the operation of the system. Here, the corresponding processor 10, 1
If 1 and 12 are normal, the abnormality detection signal "0" is output. As a result, the system control unit 30 does not input the abnormality detection signal, and therefore does not give an instruction to the display unit 33 to display a failure occurrence.

On the other hand, when one of the processors (for example, the processor 10) becomes abnormal due to a program runaway or the like, the abnormality monitoring unit 20 detects the abnormality by the operation of the watchdog timer or the like. And the abnormality monitoring unit 2
0 sets the abnormality detection signal to "1" and the abnormality flag 2
Set 0a. Since the output from the OR circuit 31 is "1", the system control unit 30 instructs the display unit 33 to display an alarm and notifies the outside of the occurrence of a failure.

The master control units 10a, 11a and 12a of the processors 10, 11 and 12 are connected to the system bus 4
The health check between the processors is performed via 0 to monitor the occurrence of a fault in another processor. In this case, the master control units 11a and 12a detect that a fault has occurred in the processor 10.

As a result, the master control units 11a and 12a are
One of them performs the operation of the master processor as a system, saves the processing data and the like before the failure, and then restarts the system. It should be noted that the processors 11 and 12 to be the master processors are configured so as to be determined in a predetermined order, or when the processors 10, 11 and 12 are sequentially performing health checks, the failure occurrence is first detected. Detected processors 10, 11,
12 may be configured to perform operations as a master processor.

When the system is restarted, a failure due to a software factor such as a program runaway is resolved, and normal operation can be resumed. Further, if the processor 10 repeatedly fails even after restarting due to a program abnormality or hardware failure, an alarm display on the display unit 33 or an alarm display (not shown) provided outside is displayed. Repeated. In this case, the maintenance staff investigates the cause of the failure from the operation history of the processor 10 and the like.

As described above, in the first embodiment, the abnormality monitoring units 20, 21,
Since 22 is provided, the same configuration can be used for each abnormality monitoring unit 20, 21, 22. That is, the abnormality monitoring units 20, 21, and 22 do not need to identify whether the processor to be monitored is the master processor or not, and therefore the abnormality monitoring program is also included in the abnormality monitoring units 20, 21, and 22. The hardware cost and the program development cost can be remarkably reduced, such as being the same.

Moreover, the abnormality monitoring units 20, 21, 22 are
Since it is not necessary to send information such as which processor 10, 11, 12 the abnormality has occurred, the information amount of the abnormality detection signal can be small and the hardware configuration can be simplified.

In the first embodiment, the abnormality monitoring unit 20,
Abnormality notification signal line 5 independent from 21 and 22
Although the abnormality detection signal is transmitted at 0, 51, 52, this is used as one abnormality notification signal line, and each abnormality monitoring unit 2
The abnormality detection signals from 0, 21, 22 may be transmitted to the system control unit 30 in a time division manner. With this structure, the structure can be further simplified, and the cost of the system can be reduced.

Moreover, in the first embodiment, since it is not necessary to have the attributes of the master and the processors other than the master even in the recovery processing after the occurrence of the failure, the recovery processing at the time of the failure is performed by all the processors 10, 11, 12. Can be done in common. Further, with such a configuration, even if any of the processors 10 has a failure, another processor can perform restarting, so that reliability of the system can be improved.

Second Embodiment Next, a case where the multiprocessor system is applied to a terminal controller for controlling communication between a host and a terminal of a financial system will be described as a second embodiment.

FIG. 2 is a block diagram of a financial system including a terminal controller. The financial system shown in the figure includes a host 60, a terminal controller 100 provided in a sales office 70, a plurality of terminals 200-1 to 200-n, a monitoring system 80, and a public line 90.

The host 60 is a center that is connected to a plurality of business offices (only one business office 70 is shown in the figure) through a dedicated line and controls financial processing from each business office. The sales office 70 is provided with a terminal controller 100 connected to the host 60 via a dedicated line, and a plurality of terminals 200-1 to 200-n for which the terminal controller 100 controls communication. Here, what is included in the plurality of terminals 200-1 to 200-n is a window terminal where a bank employee performs data processing of the customer, an automated device directly operated by the customer, and the like.

The monitoring system 80 is a system installed in a business center of a financial institution or the like and connected to the terminal controller 100 via the public line 90. The terminal system 100 is monitored for failures and the terminal 200 is connected to the terminal 200.
-1 to 200-n monitor the operating state of the automated equipment.

Next, the details of the terminal controller 100 will be described. FIG. 3 is a configuration diagram showing details of the terminal controller 100. The illustrated terminal controller 100 includes processors 110 and 111, abnormality monitoring units 120 and 121, and a local memory (LM) 13
0, 131, I / O 140, 141, common memory (C
M) 150, system bus 160, system controller 17
0, equipped with a modem 180.

The processors 110 and 111 correspond to the processors 10, 11 and 12 of FIG. 1 described above, and have a function of mainly performing communication processing as the terminal controller 100. In addition, each processor 110, 11
1 is provided with master control units 110a and 111a,
Similar to the first embodiment, it has a function of checking the abnormality flags of the abnormality monitoring units other than the abnormality monitoring unit that monitors the own processor and restarting the system if any of the abnormality flags is set. ing.

The abnormality monitoring units 120 and 121 monitor the abnormality of the processors 110 and 111, and are composed of a watchdog timer and programs executed by the processors 110 and 111.
When the abnormality is detected, the abnormality detection signal is sent to the system control unit 170 via the abnormality notification signal lines 190 and 191. In addition, each abnormality monitoring unit 12
0 and 121 indicate an abnormality flag 120 when an abnormality is detected.
a, 121a are set.

The local memories 130 and 131 are memories having a function as a main memory of the processors 110 and 111, and store various data, programs and the like, and constitute a work area of the processors 110 and 111. Is. The I / O units 140 and 141 connect the host 60 and the terminals 200-1 to 200-n connected to the terminal controller 100, and are connected to the processors 110 and 111 via the system bus 160. Further, in this embodiment, the I / O unit 140
In addition, any one of the terminals 200-1 to 200-n is connected to the host 60, and the processor 110 takes charge of these controls, and the I / O unit 141 includes the terminals 200-1 to 200-20.
The processor 111 takes charge of these controls by connecting any one of 0-n.

In the second embodiment, the processor 11
0, 111, the abnormality monitoring units 120 and 121, the local memories 130 and 131, and the I / O units 140 and 141 have been described as two units, respectively, but the number is not limited to this.

The common memory 150 is for each processor 11
0, 111 is for storing data shared by the processor 110, the processor 110,
111 and I / O units 140 and 141 are connected. The system control unit 170 corresponds to the system control unit 30 in the first embodiment and includes a logical sum circuit 171, a failure notification unit 172, a console 173, and a relay 174. The OR circuit 171 has, on its input side, the abnormality notification signal lines 190 and 19 from the abnormality monitoring units 120 and 121.
1 is connected to the abnormality notification signal line 192 for inputting other abnormality detection signals, and the logical sum operation of the abnormality detection signals from these signal lines 190 to 192 is performed.

The fault notifying section 172, when the abnormality detection signal from the OR circuit 171 is inputted, the console 173.
To the monitoring system 80 via the modem 180, and also to the monitoring room in the sales office 70, etc. by sending an alarm display signal to the monitoring system 80 via the modem 180. To do.

Further, the console 173 is an operation panel on which a maintenance person or the like performs various operations, and a display section for displaying an alarm is provided on the console 173. The relay 174 is connected to the display section of the monitoring room provided in the sales office 70. The monitoring room is a room provided for maintenance personnel to monitor each device installed in the sales office 70. Although not shown, the terminal controller 100 is not included in the terminal 2 in the sales office 70.
00-1 to 200-n also have a database and the like for processing.

Next, the operation of the second embodiment will be described. The respective processors 110 and 111 perform communication control processing between the host 60 and the terminals 200-1 to 200-n, and the respective terminals 2.
Database processing and the like from 00-1 to 200-n are performed.

Further, the abnormality monitoring units 120 and 121 monitor the respective processors 110 and 111 for abnormalities while the processors 110 and 111 are operating. If the corresponding processors 110 and 111 are normal, the abnormality detection signal “0” is output. As a result, the system control unit 170 does not input an abnormality detection signal, and therefore does not give a fault occurrence display to the console 173 or give an instruction to the monitoring system 80 or the monitoring room in the sales office.

During the operation of the processors 110 and 111, if a failure due to software occurs in any of the processors, the corresponding abnormality monitoring unit 12
0 and 121 detect an abnormality. Now this is processor 1
If 10 is set, the abnormality monitoring unit 120 is used as in the first embodiment.
Detects the abnormality by the operation of the watchdog timer or the like. Then, the abnormality monitoring unit 120 sets the abnormality detection signal to "1" and sets the abnormality flag 121a.
As a result, the system control unit 170 causes the OR circuit 17
Since the output from 1 becomes "1", the alarm display is instructed to the console 173 and the modem 180
An alarm display signal is sent to the public line 90 via the relay line and the relay 174 is turned on.

On the other hand, the master control unit 1 of the processor 111
11a indicates that the processor 110
Detect that a failure has occurred. As a result, the master control unit 111a operates the master processor to save the processing data and the like stored in the local memories 130 and 131 before the failure, and then initializes the system to restart the system. I do. Alternatively, local memory 1
So-called warm start is performed without initializing 30, 131 and the like.

In the second embodiment, when there are three or more processors, the processor to be the master processor is configured to be determined in a predetermined order, as in the first embodiment, or When the processors are sequentially performing health checks, the processor that first detects a failure may be configured to perform the operation as the master processor.

When the system is restarted, a failure due to a software factor such as a program runaway is resolved, and normal operation can be resumed. Further, if the processor 110 repeatedly fails even after restarting due to a program abnormality or hardware failure, the alarm display on the console 173 and the alarm display in the monitoring room of the sales office 70 are repeated. Therefore, it can be determined that some kind of failure handling processing is necessary.

As described above, in the second embodiment, the same effect as in the first embodiment can be obtained, and the reliability of the financial system can be improved.

In each of the above embodiments, the abnormality monitoring unit 20,
Abnormality notification signal lines 50, 51, 52 (190, 19) that are independent of the abnormality detection signals from 21, 22 (120, 121)
Although the system control unit 30 (170) is configured to be sent to the system control unit 30 (170) via 1), the system control unit 30 (170) is connected to the system bus 40 (160).
The abnormality detection signal may be transmitted via (160).

[0041]

As described above, according to the multiprocessor system of the present invention, an abnormality monitoring unit is provided for each processor, and when the system control unit receives an abnormality detection signal from any of the abnormality monitoring units. Since the fact that an abnormality has occurred in any one of the processors is displayed, the abnormality monitoring units need only have the same configuration, and therefore the hardware cost and the software cost can be reduced.

Further, according to the terminal controller of the present invention, when the abnormality of each processor is detected, the system controller displays the occurrence of the abnormality, and the master controller restarts the system. Since the abnormality monitoring units have the same configuration, the hardware cost and the software cost can be reduced, and the reliability of the system can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a multiprocessor system of the present invention.

FIG. 2 is a configuration diagram of a financial system including the terminal controller of the present invention.

FIG. 3 is a configuration diagram of a terminal controller of the present invention.

[Explanation of symbols]

10, 11, 12, 110, 111 Processor 20, 21, 22, 120, 121 Abnormality monitoring unit 20a, 21a, 22a, 120a, 121a Abnormality flag 30, 170 System control unit 33 Display unit 173 Console (display unit)

Claims (4)

[Claims] 1. An abnormality monitoring unit, which is provided for each processor, monitors an abnormality of each processor and sends an abnormality detection signal when an abnormality is detected, and each processor is provided separately. A multiprocessor system comprising: a system control unit which, when an abnormality detection signal is received from any of the abnormality monitoring units, displays that an abnormality has occurred in any of the processors. 2. A processor is provided for each processor, which monitors the abnormality of each processor and detects the abnormality,
An abnormality monitoring unit that sends an abnormality detection signal and sets an abnormality flag is provided separately from each of the processors. When an abnormality detection signal is received from any of the abnormality monitoring units, an abnormality occurs in any of the processors. The system control unit that displays that an error has occurred and the error flags of the error monitoring units other than the error monitoring unit that is provided in each processor and monitors the own processor are checked, and if any of the error flags is set, A multiprocessor system including a master control unit that performs system restart processing. 3. A terminal controller for controlling communication between a host and a terminal, comprising: a plurality of processors that share and execute the communication control processing; and a plurality of processors provided for each of the plurality of processors, each of which is an abnormality of the processor. If an abnormality is detected, the abnormality detection signal is detected, and an abnormality monitoring unit that sets an abnormality flag is provided separately from each of the processors, and an abnormality detection signal is output from any of the abnormality monitoring units. If received, a system control unit that indicates that an abnormality has occurred in any of the processors, and each of the processors are provided separately, and if an abnormality detection signal is received from any of the abnormality monitoring units, System control unit that indicates that an abnormality has occurred in one of the processors, and an abnormality monitoring unit that is installed in each processor and monitors its own processor Examine the abnormality flag outside the abnormal condition monitoring section, the terminal controller if any abnormality flag is set, and a master control unit for re-startup process of the system. 4. The terminal controller according to claim 3, wherein the master control unit is determined such that the plurality of master control units perform a function as a master in a predetermined order.