JPH07248894A - Floating-point arithmetic unit - Google Patents

Abstract

PURPOSE:To speed up an arithmetic processing treating floating point data of an extension accuracy form by shortening the reading and processing time of data and advancing the start of the processing by an arithmetic unit. CONSTITUTION:This device is a floating point arithmetic unit having two pairs of floating point register(FPR) reading ports of an 8-byte (long precision) width and speeds up an arithmetic processing where the FPR reading of a 16-byte (extended accuracy) width is required for the only one side of the ports. In this case, the first half 8-byte FPR reading address is set to a FAR 102 from the port on the side which is normally used, and at the same time, the second half 8-byte FPR reading address is set to an FBR 101 from the port on the unused side (the side opposite to the side which is normally used). Thus, the 16-byte FPR reading data can be read one time. These set data are rightly imparted to the input of an arithmetic unit 500 by the control of an arithmetic unit input select signal generation circuit 400 and the data is calculated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating point arithmetic unit, and more particularly, to an extended precision data as an arithmetic input,
The present invention relates to a floating-point arithmetic unit suitable for use in high-speed execution of instructions for floating-point arithmetic processing that outputs long-precision data.

[0002]

2. Description of the Related Art Generally, in the field of scientific and technical computing, a floating point data format is used as a main data representation format.

FIG. 4 is a diagram for explaining an example of the data format of floating point data, and the floating point data will be described below with reference to FIG.

Floating point data is usually composed of a 1-bit sign part S, a 7-bit exponent part, and a mantissa part. The 1-bit sign part S represents the sign for the mantissa, and the 7-bit exponent part represents an exponent that is a multiple of 16 to the mantissa part represented by the hexadecimal number in the access64 representation. The mantissa part is a hexadecimal number with a decimal point to the left of the most significant digit.

As shown in FIG. 4, the floating-point number data format has three formats: short precision format, long precision format, and extended precision format.
There are two formats: short-precision floating-point data consists of a total of 4 bytes with a mantissa of 6 digits and 3 bytes, and long-precision floating-point data consists of a total of 8 bytes with a mantissa of 14 digits and 7 bytes. The extended precision floating point data is composed of a total of 16 bytes with a mantissa part having 28 digits and 14 bytes.

FIG. 5 is a block diagram showing the configuration of a floating point arithmetic unit to which the present invention is applied, which handles floating point data of such short precision format, long precision format and extended precision format. The operation of the conventional technique will be described with reference to FIG. 5, 100 is a floating point register (FPR), 101 is a first operand read register (FBR), 102 is a second operand read register (FAR), 103 is a first operand read save register (FBRH), and 104 is a first operand read save register (FBRH). Two-operand read save register (FARH), 110, 300 and 301 are selection circuits, 200 is an FPR read address generation circuit, 4
00 is an arithmetic unit input select signal generation circuit, and 500 is an arithmetic unit.

In the floating point arithmetic unit shown in FIG.
The FPR 100 has one write port to which the 8-byte width FPR data write path 9 is connected, and two read ports to which the FPR data read paths 11 and 12 each having an 8-byte width and a total of 16 bytes are connected. Equipped with. The selection circuit 110 uses the data from the memory and the FPR.
It is a selection circuit that selects data from 100,
In this example, it is not necessary to consider reading data from memory.

Reading data from the FPR 100 is
It is designated by the FPR read address (for the first operand) 26 and the FPR read address (for the second operand) 27 generated by the FPR read address generation circuit 200.

Read from FPR100, FBR10
Operand data set in 1, FAR102, FBRH103, and FARH104 is selected by the input selection circuits 300 and 301 for the arithmetic unit 500 according to the instruction of the select signals 41 to 46 from the arithmetic unit input select signal generation circuit 400. Is input to 500. The result of the arithmetic processing by the arithmetic unit 500 is written in the memory or is written in the FPR 100 via the 8-byte wide FPR write data path 9.

In the arithmetic processing for handling the floating-point data in the short-precision format and the long-precision format by the floating-point arithmetic unit shown in FIG. 5, each 8-byte data to be processed by one reading is the FPR data read path 11, After setting the data in the FBR 101 and FAR 102 through 12, selecting the data in the selection circuits 300 and 301 and supplying the data to the arithmetic unit 500, and causing the arithmetic unit 500 to perform the target arithmetic operation, the arithmetic result is stored in the FPR write data path 9. Through FPR10
This can be done by writing to 0.

On the other hand, the arithmetic processing for handling the floating-point data in the extended precision format needs to be read twice, and is performed as follows.

That is, first, the first 8 bytes of the first half of the data to be processed by the first reading are FBR 101, F
Set to AR102. Then, at the time of the second read, the FBR101 and FAR10 are read by the first read.
The first half 8 bytes of data set to 2, respectively,
Save to FBRH103, FARH104 and 2
The data of each 8 bytes in the latter half read out by the read-out operation is set in the FBR 101 and FAR 102.

FBR10 is obtained by reading data twice.
1, FAR102 and FBRH103, FARH104
After being selected by the selection circuits 300 and 301, the data set to No. 2 is subjected to the target operation by the operation unit 500, and the result is passed through the FPR write data path 9 twice in the first half 8 bytes and the second half 8 bytes. Divided into FPR100
Written in.

That is, when the processing device shown in FIG. 5 performs arithmetic processing for handling floating-point data of extended precision format,
This requires two read processes and two write processes.

An operation example in the case of causing a specific instruction processing to be performed by the above-described processing device will be described below by taking an LRDR (LOAD ROUNDED) instruction used in a known information processing device as an example.

This LRDR (LOAD ROUNDE
D) The spec of the instruction is that the operand designated by the second address (R2) is rounded and the first address (R2) is rounded.
It is loaded into the floating point register specified by 1). Rounding is 16 bytes wide to 8 bytes wide. ".

When the LRDR instruction is processed by the processing device shown in FIG. 5, the first 8 bytes of the data to be processed are set in the FAR 102 by the first reading. During the second reading, the first 8 bytes of the data set in the FAR 102 to be processed are saved in the FAR 104, and the latter 8 bytes of the data read by the second reading are set in the FAR 102.

Then, the FAR 102 and the FARH 104
After being selected by the selection circuits 300 and 301, the data set to is subjected to rounding processing by the arithmetic unit 500,
The result is 10 via the FPR write data path 9.
Written to zero.

The LRDR instruction is processed as described above. The points to be noted here are (A) that the FBR 101 is unused at the first read, and (B) that is processed by the second read. Two points are that the rounding process cannot be started by the computing unit 500 until the data to be set is set in the FAR 102.

In the above description, the LRDR instruction has been described as an example of the operation, but generally, for an instruction that reads 16 bytes only for one of the read ports of the FPR100 and writes 8 bytes for the operation result, The above two points (A) and (B) can be said.

As a prior art relating to this type of floating point arithmetic unit, for example, the technique described in Japanese Patent Laid-Open No. 59-43441 is known.

[0022]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
Should be processed by reading twice for LRDR instruction 1
The rounding process cannot be started by the computing unit 500 until 6-byte data is set in the FAR 102 and the FAR H104, and the processing of the LRDR instruction and the like is speeded up, that is, the arithmetic processing of floating-point data in the extended precision format. There is a problem that the processing speed cannot be increased.

An object of the present invention is to solve the above-mentioned problems of the prior art, shorten the data read processing time, and speed up the start of processing by the arithmetic unit, whereby the arithmetic processing of floating-point data in the extended precision format is performed. It is an object of the present invention to provide a floating point arithmetic unit capable of speeding up processing.

[0024]

According to the present invention, the above object is achieved in a floating point arithmetic unit having two sets of floating point register read ports each having a width of 8 bytes (long precision) and 16 bytes for only one of the ports. (Extended precision)
When performing arithmetic processing that requires reading the floating-point register of the width, the first half 8-byte FPR read address is given to the port that is normally used, and the second half 8-byte FPR read address is used on the other unused side ( The floating-point register read address generation circuit that enables to read 16 bytes of FPR read data at a time by giving it to the port on the side opposite to the side normally used, and the operation input data to be processed. This is achieved by providing a selecting circuit and an arithmetic unit input select signal generating circuit for changing the arithmetic unit input of the operand data as the holding register is changed by the address generating circuit.

[0025]

According to the present invention, by the above-mentioned means, 16 operations to be performed in the arithmetic processing which requires the reading of the floating point register of 16 bytes (extended precision) width such as the LRDR instruction.
The byte data 16 can be set by reading once, and the processing by the arithmetic unit can be started earlier and the processing can be speeded up.

Further, according to the present invention, even for an instruction to read 16 bytes of data for one of the read ports of the FPR and write 8 bytes of data for the operation result, the operation unit starts the intended operation earlier. As a result, processing speed can be increased.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a floating point arithmetic unit according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an FPR read address generating circuit used in a floating point arithmetic unit according to one embodiment of the present invention, and FIG. 2 is a diagram for explaining the operation of an instruction decoding circuit using an LRDR instruction as an example. FIG. 3 is a diagram for explaining the operation of the arithmetic unit input select signal generation circuit using the LRDR instruction as an example. The overall structure of the floating point arithmetic unit according to the embodiment of the present invention is the same as that shown in FIG. In FIG. 1, 205 is an instruction decode circuit, 206 and 207 are +
Two incrementers 208 and 209 are selection circuits.

In FIG. 1, when the arithmetic processing is started, the FPR
The numbers R1 and R2 are given to the FPR read address generation circuit 200 as FPR address data. And
In case of extended precision instruction, FPR indicated by R1 and R2
The number is given to the paths 51 and 53 as the FPR address of the first FPR read data. As the FPR address of the second FPR read data, the addresses of R1 + 2 and R2 + 2 incremented by the +2 incrementers 206 and 207 are given to the paths 52 and 54, respectively.

The paths 51 to 54 are provided for the instruction decode circuit 20.
Selected by the select signal from 5, the selection circuit 2
It is reflected in the FPR read address (for the first operand) 26 and the FPR read address (for the second operand) 27 output via 08 and 209.

Next, in the arithmetic processing unit having the FPR read address generating circuit having the above-mentioned configuration, the operation according to the prior art and one embodiment of the present invention will be described in detail by taking the case of performing the LRDR instruction processing as an example. Explained.

LRDR instruction processing according to the prior art is shown in FIG.
As described above, the first half 8 bytes of the data to be processed by the first read is set in the FAR 102,
At the time of the second read, the first 8 bytes of the data set in the FAR 102 to be processed are saved in the FAR 104, and the last 8 bytes of the data read by the second read are set in the FAR 102. Be seen.

The read address in this case is the FPR read address (for the second operand) 27 via the path 53 and the selection circuit 209 as the FPR address of the FPR read data for which the FPR number indicated by R2 in FIG. 1 is the first. What is reflected in is used. And 2
As the FPR address of the FPR read data for the second time,
The address R2 + 2 incremented by the +2 incrementer 207 is passed from the path 54 through the selection circuit 209,
The one reflected in the FPR read address (for the second operand) 27 is used.

In this case, the states of the select signal paths 21 to 24 of the instruction decode circuit 205 and the FPR read address output from the select circuit 209 (for the second operand).
The state of No. 27 is shown in FIG.

In one embodiment of the present invention, the FPR address R2 + 2 of the second FPR read data is passed from the path 54 through the selection circuit 209 to the FPR read address (second
(For operand) 27, the FPR address R2 of the first FPR read data is set to pass 5
3. At the same time, it is reflected on the FPR read address (for the second operand) 27 via the selection circuit 209, and at the same time, it is reflected on the FPR read address (for the first operand) 26 from the path 55 through the selection circuit 208.

Therefore, the select signal 25 for selecting the path 55 is generated by the instruction decode circuit 205. There are two select conditions for this purpose: (1) LRDR instruction and (2) first read, and the select signal 25 is generated by ANDing these two conditions. You can

In this case, the states of the select signal paths 21 to 25 of the instruction decoding circuit 205 and the selection circuits 208 and 20.
9, the state of the FPR read address (for the first operand) 26 and the FPR read address (for the second operand)
The state of (for operand) 27 is shown in FIG.

As can be seen from FIGS. 2 (a) and 2 (b),
Conventionally, the read address is set as the address R2 by the select signal 23 at the first time and is set as the address R2 + 2 by the select signal 24 at the second time, which is set by the operation of two times. In one embodiment, the addresses R2 and R2 + 2 can be set in one operation by the first select signals 23 and 25, respectively. Therefore, the one embodiment of the present invention can eliminate the need for the second read processing.

As described above, the embodiment of the present invention uses the path 26 as the FPR address in one operation in FIG.
Since the address R2 + 2 can be given to the path 27 and the address R2 can be given to the path 27, the operand data necessary for the arithmetic processing of the LRDR instruction can be supplied in one operation to the FBR101 and FAR1.
It can be set to 02.

Conventionally, the arithmetic processing is performed after the operand data required for the arithmetic processing is set in the FAR 102 and the FARH 104. However, as mentioned above,
In one embodiment of the present invention, the FPR address can be set by one operation, and the operand data required for the arithmetic processing is set in the different registers FBR101 and FAR102 which are different from those in the prior art. Therefore, it becomes necessary to change the method of inputting the operand data to the arithmetic unit 500.

Of course, this can be dealt with by changing the arithmetic processing of the arithmetic unit 500, but in one embodiment of the present invention, the select signal paths 41 to 46 of the input select signal generating circuit 400 for the arithmetic unit 500 are connected. I am trying to deal with it by changing the operation.

That is, in the operation of the select signal of the arithmetic unit input select signal generating circuit 400 shown in FIG. 3, in the case of the conventional technique, as shown in FIG. The FAR 102 data and the FAR H104 data are selected by the selection circuits 300 and 301 and given to the arithmetic unit.

In one embodiment of the present invention, as shown in FIG. 3 (b), the first selection signal 41 selects the data of the FBR 101 and the selection signal 44 selects the data of the FAR 102 by the selection circuits 300 and 301, respectively. And is given to the computing unit 500. In this case, there are two select conditions of the arithmetic unit input select signal generation circuit 400: (1) LRDR instruction and (2) first read, and these two conditions are ANDed. As a result, the select signals 41 and 44 can be generated, whereby the value of the operand data input to the arithmetic unit 500 can be guaranteed.

As described above, according to the embodiment of the present invention, the FPR read address R2 + 2 (for the latter 8 bytes of the second operand) which is usually used for the second read processing is used.
At the time of the first read, since it is placed on the unused first operand address, 16 bytes of data are read by one read process, and the read 16 bytes of data are read. Since the arithmetic unit input select signal generation circuit can be correctly input to the arithmetic unit by controlling the arithmetic unit input selection signal generation circuit, correct arithmetic processing can be performed at high speed.

Accordingly, one embodiment of the present invention is the LRD.
With respect to the R instruction, the setting of operand data to be operated can be accelerated, and as a result, the operation can be started earlier, and the processing speed of the LRDR instruction can be increased. Further, the present invention is not limited to the LRDR instruction,
Read 16 bytes of PR for only one port,
As a result, even for an instruction to write 8 bytes of data,
Similarly, the processing speed can be increased.

[0046]

As described above, according to the present invention, the data read processing time is shortened, and the processing by the arithmetic unit is started earlier, which enables high-speed arithmetic processing for handling floating-point data in extended precision format. Can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an FPR read address generation circuit used in a floating point arithmetic unit according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an operation of an instruction decoding circuit using an LRDR instruction as an example.

FIG. 3 is a diagram illustrating an operation of an arithmetic unit input select signal generation circuit using an LRDR instruction as an example.

FIG. 4 is a diagram illustrating an example of a data format of floating point data.

FIG. 5 is a block diagram showing a configuration of a floating point arithmetic unit to which the present invention is applied.

[Explanation of symbols]

100 Floating Point Register (FPR) 101 First Operand Read Register (FBR) 102 Second Operand Read Register (FAR) 103 First Operand Read Save Register (FBR)
H) 104 second operand read save register (FAR
H) 110, 208, 209, 300, 301 selection circuit 200 FPR read address generation circuit 205 instruction decode circuit 206, 207 +2 incrementer 400 arithmetic unit input select signal generation circuit 500 arithmetic unit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Makoto Takiguchi 1 Horiyamashita, Hadano City, Kanagawa Hitachi Computer Engineering Co., Ltd. (72) Inventor Chiaki Takahashi 1 Horiyamashita, Hadano City, Kanagawa Hitachi Computer Ta Engineering Co., Ltd.

Claims (1)

[Claims] 1. A floating-point arithmetic unit having two sets of floating-point register read ports of long-precision width, wherein arithmetic processing requiring floating-point register read of extended-precision width for only one of the ports is The floating-point register read address for the number of bytes is given to the normally used port, and the floating-point register read address for the number of bytes in the latter half of the half is given to the other port. A floating-point arithmetic unit characterized by reading data of the number of bytes corresponding to the width and executing the arithmetic.