JPH07248373A - Radar device - Google Patents

Abstract

PURPOSE:To provide a radar device to prevent the degradation of target performance by removing an unnecessary signal when the unnecessary signal of large electric power is contained in a received signal of a radar. CONSTITUTION:A radar device is composed of a sorting circuit 10 to sort a reference cell outputted from a memory circuit 9 in order of small electric power and a large electric power direction average value changing circuit 11 in which the reference cell is added in order from this reference having small electric power, and an average value is found every time, and every time the average value is found, the reference cell not less than preset electric power is searched, and when the reference cell not less than the preset electric power is detected, this is rejected as an unnecessary signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radar device for performing target detection processing from a radar reception signal.

[0002]

2. Description of the Related Art FIG. 20 shows a conventional CA-CFAR (Cell Average Coarse) for suppressing the false alarm probability of erroneously recognizing an unnecessary signal such as noise as a target in a signal processing unit of a radar.
It is a figure which shows the nstantFalse Alarm Rate) and its peripheral technology. In the figure, 2 is an RF (Radio) for transmission.
A transmitter for generating a frequency signal, 1 is a transmitting antenna that emits the radio waves generated by the transmitter 2 into space, 3 is a receiving antenna that receives radio waves from the space, and 4 is a receiving antenna 3.
A receiver that performs band limitation, phase detection, and amplification on the signal received at 5, 5 is an A / D converter that converts the signal output at receiver 4 from an analog signal to a digital signal, and 6 is A
To improve the signal-to-noise power ratio of the output signal of the / D converter 5,
A coherent integrator circuit for outputting to a plurality of frequency components (hereinafter referred to as cells), 7 is a square-law detection circuit for generating power in cell units from the output signal of the coherent integrator circuit 6,
Reference numeral 8 denotes a cell setting circuit for setting a target detection target cell (hereinafter referred to as a target cell) from the output of the square detection circuit 7 and a cell in the vicinity thereof (hereinafter referred to as a reference cell), and 9 denotes the square detection circuit 7. A memory circuit which stores an output signal and outputs a target cell and a reference cell set by the cell setting circuit 8, and 12 obtains an average value of the cells output from the cell setting circuit 8 and determines the average value in advance by calculation. A threshold calculation circuit for multiplying the calculated coefficient, 13 is an output signal from the threshold calculation circuit 12 and the cell setting circuit 8
It is an alarm circuit that compares the size of the target cell output from the device, determines the presence or absence of a target signal for the target cell, and outputs the determination result. FIG. 21 shows, for example, Artech House AIRBORNE P
ULSED DOPPLER RADAR p399 It is a block diagram of the target detection process shown in FIG. 17.4, 12 and 13 are the same as the code | symbol of FIG. FIG. 22 shows the configuration of the memory circuit 9. The signal input from the square detection circuit 7 is stored for each cell, and the cell of interest and the reference cell corresponding to the number designated by the cell setting circuit 8 are output.

Next, the operation will be described. This is a case where the velocity of a target object such as an enemy airplane is detected by a radar mounted on a friendly missile or the like. The target signal generated by the radio wave emitted by the transmitter 2 and the transmission antenna 1 reflected by the target object is
Not only the noise and the Doppler frequency corresponding to the relative velocity between the missile and the target object, but also unnecessary signals such as clutter and interference waves having the Doppler frequency corresponding to the velocity of the missile are superimposed, and this signal is received by the receiving antenna 3. .
The signal received by the receiving antenna 3 is band-limited, phase-detected and amplified by the receiver 4. The output of the receiver 4 is A
The / D converter 5 converts the analog signal into a digital signal. The digital signal output from the A / D converter 5 is transferred to the FFT (Fast F
Ourier Transform) etc., and a plurality of cells corresponding to the number of hits are output. When the target object is moving at a constant speed, the Doppler frequency is also uniquely determined.Therefore, a specific cell among the above multiple cells is multiplied by the number of hits due to the integration effect and has a large power value, and it rides on another cell. Since noise and the like are attenuated by the integration effect, the signal-to-noise power ratio can be improved as a result. The output signal of the coherent integration circuit 6 is converted into a power value for each cell by the square detection circuit 7, and then sent to the memory circuit 9. The memory circuit 9 stores this power value for each cell. A signal indicating that information has been set from the square detection circuit 7 to the memory circuit 9 is transmitted from the square detection circuit 7 to the cell setting circuit 8. In the cell setting circuit 8, when this signal is input from the square detection circuit 7, The target cell and the reference cell are set and are transmitted to the memory circuit 9. The memory circuit 9 stores the output signal of the square wave detection circuit and outputs the target cell and the reference cell set by the cell setting circuit 8.

The operation of setting the cell of interest and the reference cell in the cell setting circuit 8 will be described below.
The memory circuit 9 stores frequency components (cells) including the Doppler frequency corresponding to the target relative speed of the received signal. In order of increasing frequency, this is f ₁ , f ₂ , f
_{3 ····, f n (n} is a positive integer). In the first processing, f ₁ having the smallest Doppler frequency is selected as a cell of interest and is set as the processing target. Furthermore, an arbitrary number of cells that are closest to the cell of interest and that may partially overlap with the cell of interest (this is called a guard cell) are removed, and an arbitrary number of cells are referred to from the closer one of the remaining cells. Select as a cell. For example, the remaining f ₄ and f _{5 obtained by} removing two guard cells f ₂ and f ₃ closest to the target cell f ₁ are removed.
The reference cells f ₄ , f ₅ ... f _N (N is a positive integer satisfying N ≦ n) close to the target cell f ₁ are selected from among the f _n .

A reference cell is sent from the memory circuit 9 to a threshold calculation circuit 12, and the threshold level Th of this reference cell is calculated by the equation (1).
Calculate 1. Here, the number N of reference cells and the values of the threshold coefficient K1 are determined in advance so that the false alarm probability becomes a predetermined small value.

[0006]

[Equation 1]

The alarm circuit 13 compares the target cell S output from the memory circuit 9 with the threshold Th1 output from the threshold calculation circuit 12, and if Th1 <S, there is a target, and if Th1> S, there is no target. Is judged,
Output the judgment result. The result of this target presence / absence determination is stored in a memory circuit (not shown) at the next stage for each cell and then displayed on the screen for monitoring. Also, this alarm circuit 1
The signal of the judgment result of 3 is also sent to the cell setting circuit 8, and when the cell setting circuit 8 inputs this signal, the next cell is selected as the cell of interest, and the reference cell is selected from the other cells to the memory circuit 9. introduce. This operation is repeated up to the maximum value of the cell of interest.

[0008]

Since the conventional radar device is constructed as described above, a clutter or a target object outputs an interfering wave, or a bait that moves at a speed different from that of the target object. When there is an unnecessary signal such as an interference wave from an interference source such as, a reference cell having large power appears in the reference cell. In this case, since the average value calculated by the threshold calculation circuit 12 becomes large and the threshold level value also becomes large, there is a problem that the alarm circuit cannot determine the presence of the target even in the target cell having the target.

The present invention has been made in order to solve such a problem, and an object thereof is to be able to detect a target even if there is an unnecessary signal of high power.

[0010]

SUMMARY OF THE INVENTION A radar device according to the present invention includes a receiver for receiving a radio wave in which an unnecessary signal is superimposed on a target signal generated by reflecting on a target, and an output of the receiver. A / D converter that converts the signal into a digital signal and the output of this A / D converter are input, and multiple frequency components (cells) are input.
Of the coherent integrator circuit, a square detection circuit for obtaining electric power for each cell from the output signal of the coherent integrator circuit, and a cell targeted for target detection from the output signal of the square detection circuit (cell of interest) ), A cell setting circuit that sets cells (reference cells) in the vicinity thereof, a memory circuit that stores the output signal of the square wave detection circuit, and outputs the target cell and the reference cell set by the cell setting circuit. , A sort circuit that rearranges the reference cells output from the memory circuit in ascending order of power, and an output signal of the sort circuit calculates an average value in order from a reference cell group of low power, and a set power that is set each time the average value is calculated. By checking the presence or absence of the above reference cells, unnecessary signals are detected and discarded, and the remaining reference cells are output. A high power direction average value fluctuation detection circuit, a threshold calculation circuit for obtaining an average value of the reference cells output from the high power direction average value fluctuation detection circuit, and multiplying the average value by a coefficient, and the threshold calculation circuit And an alarm circuit that compares the output signal from the memory cell with the size of the target cell output from the memory circuit and determines the presence or absence of the target signal for the target cell.

Further, the radar device according to the present invention is a receiver for receiving a radio wave in which an unnecessary signal is superimposed on a target signal generated by reflecting on a target object, and the output of this receiver is converted into a digital signal. An A / D converter for conversion, a coherent integrator circuit that inputs the output of this A / D converter, and outputs a plurality of frequency components (cells), and each cell from the output signal of the coherent integrator circuit A square wave detection circuit that obtains power for each, a target cell that is the target of target detection from the output signal of this square wave detection circuit, a cell setting circuit that sets a reference cell in the vicinity thereof, and an output signal of the square wave detection circuit is stored. , A memory circuit that outputs the target cell and the reference cell set by the cell setting circuit, and a sort circuit that rearranges the reference cells output from the memory circuit in ascending order of power. For the output signals of the circuit and the sorting circuit, the reference cells with higher power are sequentially discarded one by one, and the average value is calculated each time, and each time the average value is calculated, it is checked whether there is a reference cell with a certain power or more. By detecting the unnecessary signal by, rejecting, a small power direction average value fluctuation detection circuit that outputs the remaining reference cells, and obtain the average value of the reference cells output from the small power direction average value fluctuation detection circuit, A threshold calculation circuit for multiplying the average value by a coefficient, an output signal from the threshold calculation circuit and the size of the target cell output from the memory circuit are compared, and an alarm for determining the presence or absence of a target signal for the target cell And a circuit.

Also, in the radar device according to the present invention, the large power direction average value fluctuation detection circuit is connected in parallel with the small power direction average value fluctuation detection circuit to the output of the sort circuit, A cell selection circuit for selecting and outputting the reference cell output from the power direction average value variation detection circuit and the reference cell output from the small power direction average value variation detection circuit is provided.

In the radar device according to the present invention, the reference cell output from the memory circuit is a cell rejected by the large power direction average value fluctuation detection circuit or the small power direction average value fluctuation detection circuit. This is the addition of a rejection cell recording circuit for recording.

Further, the radar apparatus according to the present invention is a receiver for receiving a radio wave in which an unnecessary signal is superimposed on a target signal generated by reflecting on a target object, and an output of this receiver is converted into a digital signal. A / D converter for conversion, a coherent integrator circuit that inputs the output of this A / D converter and outputs a plurality of cells, and power for each cell from the output signal of the coherent integrator circuit A square detection circuit to be obtained, a target cell that is a target of target detection from an output signal of this square detection circuit, and a cell setting circuit that sets a reference cell in the vicinity thereof,
A memory circuit that stores the output signal of the square-law detection circuit and outputs the cell of interest and the reference cell set by the cell setting circuit, and a sort that sorts the reference cells output from the memory circuit in ascending order of power. For the output signal of the circuit and the sort circuit, two signal power ratios that are adjacent to each other in order from the reference cell with the smaller power are calculated, and the reference cell to be rejected is determined based on the power ratio, and the remaining reference cells A peak value variation detection circuit for outputting a high power direction peak value, and a threshold calculation circuit for obtaining an average value of the reference cells output from the peak value variation detection circuit for a large power direction and multiplying the average value by a coefficient. And the output signal from the threshold calculation circuit and the large amount of the cell of interest output from the cell setting circuit. Compare, those provided with the determining alarm circuit whether the target signal for the target cell.

The radar device according to the present invention is a receiver for receiving a radio wave in which an unwanted signal is superimposed on a target signal generated by reflecting on a target object, and an output of this receiver is converted into a digital signal. A / D converter for conversion, a coherent integrator circuit that inputs the output of this A / D converter and outputs a plurality of cells, and power for each cell from the output signal of the coherent integrator circuit A square detection circuit to be obtained, a target cell that is a target of target detection from an output signal of this square detection circuit, and a cell setting circuit that sets a reference cell in the vicinity thereof,
A memory circuit that stores the output signal of the square-law detection circuit and outputs the cell of interest and the reference cell set by the cell setting circuit, and a sort that sorts the reference cells output from the memory circuit in ascending order of power. For the output signal of the circuit and the sort circuit, the two signal power ratios adjacent to each other in order from the reference cell with the higher power are calculated, the reference cell to be rejected is determined based on the power ratio, and the remaining reference cells are calculated. And a small power direction peak value fluctuation detection circuit, and an average value of the reference cells output from the small power direction peak value fluctuation detection circuit, and a threshold calculation circuit for multiplying the average value by a coefficient. , The output signal from the threshold calculation circuit and the size of the cell of interest output from the cell setting circuit And compare, those provided with the determining alarm circuit whether the target signal for the target cell.

Also, the radar device according to the present invention detects the peak value fluctuation detection in the high power direction by connecting the peak value fluctuation detection circuit in the small power direction in parallel to the output of the sort circuit. A circuit is added to select a cell to select and output from the reference cell output from the high power direction peak value fluctuation detection circuit and the reference cell output from the low power direction peak value fluctuation detection circuit. It is equipped with a circuit.

In the radar device according to the present invention, the reference cell output from the memory circuit is rejected by the large power direction average value fluctuation detection circuit or the small power direction average value fluctuation detection circuit. This is the addition of a rejection cell recording circuit for recording.

[0018]

In the radar apparatus according to the present invention, the reference cells are sorted in ascending order of power, and the reference cells having smaller power are sequentially added to obtain the average value each time, and the average value is obtained. Every time, a reference cell with a power equal to or higher than the set power is searched for, and if a reference cell with a power equal to or higher than the set power is detected, the reference cell is discarded as an unnecessary signal.

Further, in the radar device according to the present invention, the reference cells are sorted in the ascending order of power, and the reference cells having higher power are sequentially discarded and the average value is calculated each time. Every time when is calculated, a reference cell having a power equal to or higher than the set power is searched, and when a reference cell having a power equal to or higher than the set power is detected, the reference cell is discarded as an unnecessary signal. In addition, the number of reference cells that are higher than the power that is normally set is much smaller than the number of reference cells that are lower than the setting, so it is faster to process the reference cells with higher power than the reference cells with lower power. You can reach the boundary point.

Further, in the radar device according to the present invention, after the reference cells are sorted in ascending order, the reference cells are added one by one in order from the reference cell with the smaller power and one is added from the reference cell with the larger power. The average value is calculated from both directions by rejecting the reference cells one by one, searching for reference cells with power higher than the set power in each direction, and when detecting reference cells with power higher than the set power, this is regarded as an unnecessary signal. Reject.

Further, in the radar device according to the present invention, the reference cell which is once discarded is recorded so that when this reference cell is detected when the reference cell is detected in the subsequent processing. Exclude cells from the calculation.

Further, in the radar device according to the present invention, after the reference cells are sorted in ascending order, the power ratio of two adjacent reference cells is calculated in order from the reference cell with the smallest power, and the power is calculated as follows. If a suddenly large reference cell is detected, it is discarded as an unnecessary signal.

Further, in the radar device according to the present invention, after the reference cells are sorted in ascending order, the power ratio of two adjacent reference cells is calculated in order from the reference cell with the highest power, and the power is calculated as follows. When a reference cell with a suddenly small power is detected, all reference cells with a high power are discarded as unnecessary signals.

Further, in the radar device according to the present invention, after the reference cells are sorted in ascending order, the power ratios of two adjacent reference cells are changed from both directions of the low reference power cell and the high reference cell. When calculation is performed and a reference cell whose power is changing rapidly is detected, all reference cells with high power are discarded as unnecessary signals.

Further, in the radar device according to the present invention, the reference cell rejected in the above invention is recorded so that the reference cell is detected when the reference cell is detected in the subsequent processing. At this time, this reference cell is excluded from the calculation target.

[0026]

【Example】

Example 1. FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, reference numerals 1 to 9 and 12, 13 are the same as those in FIG. 10 is a memory circuit 9
It is a sort circuit that sorts the reference cells output from the cells in ascending order of power. Reference numeral 11 indicates an average value of reference cells sorted by the sort circuit 10 one by one from the reference cells with lower power, and obtains an average value. 2 is a high-power-direction average value fluctuation detection circuit that outputs the reference cell of FIG.

Next, the operation will be described. In FIG. 1, an unwanted signal such as an interference wave is superimposed on a target signal generated by the radio waves emitted by the transmitter 2 and the transmission antenna 1 being reflected by a target object such as an airplane, and this signal is received by the receiving antenna 3. Be received. The signal received by the receiving antenna 3 is band-limited, phase-detected and amplified by the receiver 4, and converted from an analog signal to a digital signal by the A / D converter 5. After being converted into a digital signal by the A / D converter 5, the coherent integrator circuit 6 improves the signal-to-noise power ratio and outputs a plurality of cells.
The output signal of the coherent integration circuit 6 is square-law detected by the square-law detection circuit 7 and converted into a power value, and then input to the cell setting circuit 8 and the memory circuit 9. When the signal from the square-law detection circuit 7 is input, the cell setting circuit 8 sets the first cell of interest and the reference cell and transmits them to the memory circuit 9. The memory circuit 9 stores the output signal of the square detection circuit 7 and outputs the target cell and the reference cell set by the cell setting circuit 8. The reference cells output from the memory circuit 9 are input to the sort circuit 10 and are sorted in ascending order of power.
And is input to the high power direction average value fluctuation detection circuit 11.

The operation of the high power direction average value fluctuation detection circuit 11 is shown in FIG. The reference cells input to the high power direction average value fluctuation detection circuit 11 are r (1), r (2), ...
.., r (N) (r (1) <r (2) <... <r (N) (N:
Reference cell number)). Initially, in step 15, the initial value 1 is set to the counter j. Next, in step 16, the threshold level Th2 (j) is calculated by the calculation formula (2).

[0029]

[Equation 2]

Next, in step 17, the value of the counter j is checked, and when the value of j is smaller than N, it is checked in step 18 whether r (j + 1)> Th2 (j). If this result is not r (j + 1)> Th2 (j), the value of j is incremented and the next step 16
Return to and form a loop. In step 18, r (j
+1)> Th2 (j), the high-power reference cells r (j + 1), r (j + 2), ..., R (N) are rejected as unnecessary signal components, and low power is consumed. Reference cell r
Only (1), r (2), ..., R (j) are output. Also,
When j = N in step 17, r (j + 1)> Th
It means that j which is 2 (j) does not exist between 1 and N−1. In this case, all the reference cells r (1), r (2), ... , R (N) are output. As described above, by the operations from step 16 to step 20, the high-power reference cell that is an unnecessary signal is rejected, and only the low-power reference cell corresponding to noise is output from the high-power direction average value fluctuation detection circuit 11.

Returning to FIG. 1, description will be made. The low power reference cell output from the high power direction average value variation detection circuit 11 is sent to the threshold calculation circuit 12. The threshold calculation circuit 12 calculates the threshold Th3 from these reference cells using the calculation formula (3).

[0032]

[Equation 3]

The alarm circuit 13 compares the target cell S output from the memory circuit 9 with the threshold Th3 output from the threshold calculation circuit 12, and if Th3 <S, there is a target, and if Th3> S, there is no target. Is judged,
Output the judgment result. The signal of the determination result is stored in the memory circuit (not shown) at the next stage and then displayed on the screen. The determination result signal is also sent to the cell setting circuit 8 and
When this signal is input, another arbitrary cell is selected as a target cell, and a series of cells in the vicinity of the remaining cells are selected as reference cells and transmitted to the memory circuit 9. This operation is repeated up to the maximum value of the cell of interest.

This makes it possible to prevent the deterioration of the target detection performance due to the unnecessary signal.

Example 2. FIG. 3 is a block diagram showing an embodiment of the present invention. In FIG. 3, 1 to 10 and 12,
Reference numeral 13 is the same as the reference numeral in FIG. Reference numeral 21 denotes reference cells sorted in ascending order by the sort circuit 10 and discards the reference cells in descending order of power to obtain an average value, and based on the average value, a reference cell having a power level higher than a certain set level. Is a small-power-direction average value fluctuation detection circuit that detects, rejects, and outputs the remaining reference cells.

Next, the operation will be described. In FIG. 3, the reception antenna 3 receives a signal in which an unnecessary signal such as an interference wave is superimposed on a target signal generated by the radio waves emitted by the transmitter 2 and the transmission antenna 1 being reflected by a target object such as an airplane. To be done. After that, the same operation as in Fig. 1,
The memory circuit 9 outputs the cell of interest and the reference cell. The reference cells output from the memory circuit 9 are input to the sort circuit 10, sorted in ascending order of power, and input to the small power direction average value fluctuation detection circuit 21.

The operation of the small-power-direction average value fluctuation detection circuit 21 is shown in FIG. The reference cells input to the small power direction average value fluctuation detection circuit 11 are r (1), r (2), ...
.., r (N) (r (1) <r (2) <... <r (N) (N:
Reference cell number)). Initially, in step 23, the initial value N-1 is set in the counter j. Next, in step 24, the threshold T is calculated by the formula (4).
Calculate h4 (j).

[0038]

[Equation 4]

Next, in step 25, r (j + 1)> T
Check whether h4 (j) or not and r (j + 1)> Th4
While the condition (j) holds, the counter j is determined in step 26.
= 1 is checked, and if j> 1, the counter j is decremented by 1 in step 27, and the process returns to step 24 again. In step 25, r (j + 1) ≤ Th4
At the stage of (j), the high power reference cells r (j), r (j + 1), ..., R (N) are rejected as unnecessary signal components in step 22, and the low power reference cell r (1),
Only r (2), ..., R (j) are output. When j = 1 in step 26, that is, r (j + 1)> Th4
If j that is (j) does not exist between 1 and N-1, all reference cells r (1), r (2), ..., R (N) are output without an unnecessary signal component. To be done. As described above, by the operations of steps 24 to 27, the high-power reference cells are discarded, and only the plurality of low-power reference cells are output from the low-power direction average value fluctuation detection circuit 21.

Next, returning to FIG. 3, description will be made. The plurality of small-power reference cells output from the small-power-direction average value fluctuation detection circuit 21 are input to the threshold calculation circuit 12 and operate in the same manner as in the first embodiment.

This makes it possible to prevent the deterioration of the target detection performance due to the unnecessary signal. Further, since the number of reference cells with power larger than the normal set value is overwhelmingly smaller than the number of reference cells with power smaller than the set value, calculation from the larger power is faster than that of the first embodiment and smaller than the large power reference cells. The calculation becomes faster because the boundary of the power reference cell can be found and the processing can be completed.

Example 3. FIG. 5 is a block diagram showing another embodiment of the present invention. In FIG. 5, 1 to 10 and 1
The reference numerals 2 and 13 are the same as those in FIG. Two
Reference numeral 9 denotes a reference cell output from the high power direction average value fluctuation detection circuit 11 and a low power direction average value fluctuation detection circuit 21.
This is a cell selection circuit that selects and outputs from the reference cells output from.

Next, the operation will be described. In FIG. 5, a reception antenna 3 receives a signal in which an unnecessary signal such as an interference wave is superimposed on a target signal generated by reflecting a radio wave emitted by a transmitter 2 and a transmission antenna 1 on a target object such as an airplane. To be done. After that, the same operation as in Fig. 1,
The memory circuit 9 outputs the cell of interest and the reference cell. The reference cells output from the memory circuit 9 are input to the sort circuit 10, sorted in ascending order of power, and input to the large power direction average value fluctuation detection circuit 11 and the small power direction average value fluctuation detection circuit 21. . The high-power-direction average value fluctuation detection circuit 11 operates in the same manner as in the first embodiment, and outputs the reference cells r (1), r (2), ..., R (N1). The small-power-direction average value fluctuation detection circuit 21 operates in the same manner as in the second embodiment, and the reference cells r (1), r (2), ..., R (N
2) is output. The reference cells output from the high power direction average value variation detection circuit 11 and the low power direction average value variation detection circuit 21 are input to the cell selection circuit 29.

The operation of the cell selection circuit 29 is shown in FIG. In FIG. 6, it is checked in step 30 whether N1 ≠ N2, and if N1 = N2, the power of the reference cell changes abruptly, but there is only one location. r (1),
Outputs r (2), ..., R (N1). Normally, such cases are few, so N1 <N2. In this case, the process jumps to step 33, where the intermediate value h of r (N1 + 1) and r (N2) is calculated. Next, in step 34, the counter j is set to N.
1 + 1 is set and it is checked in step 35 whether r (j) <h within the range of N1 <N2. r (j) <
During h, it is checked in the next step 36 whether j = N2. If j <N2, j is incremented in step 37 and the process returns to step 35. In this way, the counter j is incremented and step 3
If r (j) such that r (j) ≧ h is detected in step 5, step 3
In step 2 and step 38, only the low power reference cells r (1), r (2), ..., R (j-1) are output. When j = N2 in step 36, all reference cells r (1), r (2) are found in step 38.
,,, r (N2) is output.

Next, returning to FIG. 15, description will be made. The reference cell output from the cell selection circuit 29 is input to the threshold calculation circuit 12 and operates similarly to the case of the first embodiment.

As a result, it is possible to prevent deterioration of the target detection performance due to unnecessary signals. In addition, since both the method of sequentially processing the reference cells with low power and the method of sequentially processing the reference cells with high power are used, the accuracy is further improved.

Example 4. FIG. 7 is a block diagram showing an embodiment of the present invention. In FIG. 7, 1 to 29 are the same as the reference numerals in FIG. Reference numeral 71 is a reject cell recording circuit for recording the reference cell which was once rejected.

Next, the operation will be described. In FIG. 7, a reception antenna 3 receives a signal in which an unnecessary signal such as an interference wave is superimposed on a target signal generated by the radio waves emitted by the transmitter 2 and the transmission antenna 1 being reflected by a target object such as an airplane. To be done. After that, the memory circuit 9 outputs the target cell and the reference cell by the same processing as in the first embodiment. The reference cell output from the memory circuit 9 is input to the reject cell recording circuit 71. At first, the reject cell recording circuit 71 confirms the input reference cells and outputs all the reference cells. By the same processing as in the third embodiment, the reference cells that have not been rejected are output from the cell selection circuit 29. The reference cell output from the cell selection circuit 29 is input to the reject cell recording circuit 71. The rejected cell recording circuit 71 compares the reference cell output from the memory circuit 9 with the reference cell output from the cell selection circuit 29, and detects and records the rejected cell. After that, in the case where the reference cell output from the memory circuit 9 has a previously rejected reference cell, the reference cell is excluded from the processing target, and the remaining reference cells are confirmed and output. When the reference cell output from the rejected cell recording circuit 71 is processed by the cell selection circuit 29 and there is a further rejected cell, the reference cell is also recorded. The reference cell output from the rejected cell recording circuit 71 is input to the sort circuit 10, and the same processing as that in the first embodiment is performed.

As a result, it is possible to prevent the deterioration of the target detection performance due to the unnecessary signal. Further, by storing the once discarded reference cells, the calculation amount can be reduced because the reference cells can be excluded from the calculation target when the reference cells are detected in the subsequent processing. Therefore, the calculation becomes faster accordingly.

Example 5. FIG. 8 is a block diagram showing an embodiment of the present invention. In FIG. 8, 1 to 10 and 12,
Reference numeral 13 is the same as the reference numeral in FIG. Reference numeral 39 denotes dividing the reference cell row arranged in ascending order by the sort circuit 10 into two areas, calculating the signal power of each area, and comparing the signal power ratios. It is a high-power-direction power ratio variation detection circuit that determines reference cells to be rejected by sequentially moving and repeating reference cells with lower power.

Next, the operation will be described. The reception antenna 3 receives a signal in which an unnecessary signal such as an interference wave is superimposed on a target signal generated by the radio waves emitted by the transmitter 2 and the transmission antenna 1 being reflected by a target object such as an airplane. After that, the same operation as in the first embodiment is performed and the sort circuit 10
The sorted reference cells are output in the ascending order, and are input to the large power direction power ratio variation detection circuit 39.

The operation of the high power direction power ratio variation detection circuit 39 is shown in FIG. The reference cells input to the high power direction power ratio variation detection circuit 39 are r (1), r (2), ..., R
(N) (r (1) <r (2) <... <r (N) (N: number of reference cells)). Initially, in step 41, the initial value 1 is set to j. By the operation from step 42 to step 46, the high power reference cell is discarded.
In step 42, the reference cell is set to the region 1: r
(i) (1 ≦ i ≦ j), region 2: r (i) (j + 1 ≦ i ≦
N) divided into two areas. The average value h1 of the region 1 is calculated by the calculation formula 5, and the average value h2 of the region 2 is calculated by the calculation formula 6.

[0053]

[Equation 5]

[0054]

[Equation 6]

Next, at step 44, h2 <K5.
Whether h1 or not is checked, and while h2 ≧ K · h1 holds, the counter j is incremented in step 45.
Further, in step 46, it is checked whether the value of j is N or not, and j
Until the value of becomes N, the process returns to step 42. Step 4
Step 4 when h2 <K5 · h1 in step 4
7, where high power reference cells r (j), r
(j + 1), ..., r (N) are rejected as unnecessary signal components,
Low power reference cells r (1), r (2), ..., r
Only (j) is output. In step 46, j
= N, that is, when the boundary point j satisfying h2 <K5 · h1 does not exist between 1 and N-1, all reference cells r (1), r (1), r
(2), ..., R (N) are output.

The reference cell output from the high power direction power ratio variation detection circuit 39 is the threshold calculation circuit 1
2 and operates in the same manner as in the first embodiment.

As a result, it is possible to prevent the deterioration of the target detection performance due to the unnecessary signal.

Example 6. FIG. 10 is a block diagram showing an embodiment of the present invention. In FIG. 10, 1 to 10 and 1
The reference numerals 2 and 13 are the same as those in FIG. Four
Reference numeral 8 indicates that the reference cell array arranged in ascending order by the sort circuit 10 is divided into two areas, the signal power of each area is calculated, and the signal power ratio is compared. It is a high-power-direction power ratio variation detection circuit that determines reference cells to be rejected by sequentially moving and repeating reference cells with lower power.

Next, the operation will be described. The reception antenna 3 receives a signal in which an unnecessary signal such as an interference wave is superimposed on a target signal generated by the radio waves emitted by the transmitter 2 and the transmission antenna 1 being reflected by a target object such as an airplane. After that, the reference cells sorted in ascending order are output from the sort circuit 10 in the same manner as in the first embodiment, and are input to the small power direction power ratio variation detection circuit 48.

The operation of the small power direction power ratio variation detection circuit 48 is shown in FIG. The reference cells input to the small power direction power ratio variation detection circuit 48 are r (1), r (2), ..., R
(N) (r (1) <r (2) <... <r (N) (N: number of reference cells)). Initially, in step 50, an initial value N-1 is set in the counter j. By the operation from step 51 to step 55, the high power reference cell is discarded. Similar to the case of the third embodiment, the reference cell is divided into two areas, area 1 and area 2, unnecessary signal components are detected and rejected from the average values h1 and h2 of each area, and the remaining reference cells are output. . The reference cell output from the small power direction power ratio variation detection circuit 48 is input to the threshold calculation circuit 12 and operates in the same manner as in the first embodiment.

This makes it possible to prevent the deterioration of the target detection performance due to the unnecessary signal.

Example 7. FIG. 12 is a block diagram showing an embodiment of the present invention. 12, 1 to 29 are shown in FIG.
10 is the same as that of FIG. 8, 39 is the same as that of FIG.
The description is omitted because it is the same as the symbol.

Next, the operation will be described. In FIG. 12, a reception antenna 3 receives a signal in which an unnecessary signal such as an interference wave is superimposed on a target signal generated by reflecting a radio wave emitted by a transmitter 2 and a transmission antenna 1 on a target object such as an airplane. To be done. After that, the same operation as in Fig. 1,
The memory circuit 9 outputs the cell of interest and the reference cell. The reference cells output from the memory circuit 9 are input to the sort circuit 10 and are sorted in ascending order of power, and the sorted reference cells are the high power direction power ratio fluctuation detection circuit 39 and the low power direction power. Ratio fluctuation detection circuit 48
Is output to. The high power direction power ratio variation detection circuit 39 operates in the same manner as in the fourth embodiment, and the reference cells are r (1) and r (1).
(2) Outputs r (N1). The small power direction power ratio variation detection circuit 48 operates in the same manner as in the fifth embodiment, and the reference cells output r (1), r (2), ..., R (N2).
The reference cells output from the large power direction power ratio variation detection circuit 39 and the small power direction power ratio variation detection circuit 48 are
It is input to the cell selection circuit 29. The cell selection circuit 29 operates similarly to the third embodiment, and the reference cells are r (1) and r (1).
(2) Outputs r (j). The reference cell output from the cell selection circuit 29 is input to the threshold calculation circuit 12 and operates similarly to the case of the first embodiment.

As a result, it is possible to prevent deterioration of the target detection performance due to unnecessary signals.

Example 8. FIG. 13 is a block diagram showing an embodiment of the present invention. In FIG. 13, 1-29 and 7
1 is the same as the reference numeral of FIG. 7, 39 is the same as the reference numeral of FIG.
Are the same as those in FIG.

Next, the operation will be described. In FIG. 13, a reception antenna 3 receives a signal in which an unnecessary signal is superimposed on a target signal generated by the radio waves emitted by the transmitter 2 and the transmission antenna 1 being reflected by an airplane or the like.
After that, the reference cell and the cell of interest are output from the memory circuit 9 by the same processing as in the first embodiment. The reference cell output from the memory circuit 9 is input to the reject cell recording circuit 71. The reject cell recording circuit 71 operates in the same manner as in the fourth embodiment and outputs the reference cell. The reference cell output from the reject cell recording circuit 71 is input to the sort circuit 10 and operates as in the seventh embodiment.

As a result, it is possible to prevent the deterioration of the target detection performance due to the unnecessary signal.

Example 9. FIG. 14 is a block diagram showing an embodiment of the present invention. In FIG. 14, 1 to 10 and 1
The reference numerals 2 and 13 are the same as those in FIG. 5
Reference numeral 7 denotes a reference cell sorted in ascending order by the sort circuit 10 and calculates two signal power ratios adjacent to each other in order from a reference cell having a smaller power, and determines a reference cell to be rejected based on the power ratio. Then, the peak value fluctuation detection circuit in the high power direction outputs the remaining reference cells.

Next, the operation will be described. In FIG. 14, the reception antenna 3 receives a signal in which an unnecessary signal such as an interference wave is superimposed on a target signal generated by reflecting radio waves emitted by the transmitter 2 and the transmission antenna 1 on a target object such as an airplane. To be done. After that, the same operation as in the first embodiment is performed, and the sorted reference cells are output from the sort circuit 10 in the ascending order, and are input to the high power direction peak value variation detection circuit 57. High power direction peak value fluctuation detection circuit 57
The operation of is shown in FIG. The reference cells input to the high power direction peak value fluctuation detection circuit 57 are r (1), r (2) ,.
..., r (N) (r (1) <r (2) <... <r (N) (N: number of reference cells)). First, in step 59, the counter j is set to 1. Next, in step 60, it is checked whether j <N. If j <N, the process jumps to step 61, where r (j + 1)> K6 · r (j).
Check whether or not. r (j + 1)> K6 · r (j)
If not, j is incremented in step 62 and the process returns to step 60. If j = N in step 60, it means that j that satisfies r (j + 1)> K6 · r (j) did not exist between 1 and N−1, so that there is no unnecessary signal component. All reference cells r (1), r (2),
..., r (N) is output. In step 61, r
When a high power reference cell with (j + 1)> K6 · r (j) is detected, the process jumps to step 63 and high power reference cells r (j + 1), r (j + 2), ... , R (N) is rejected, and low power reference cells r (1), r (2), ...
Only r (j) is output. As described above, by the operations of Step 60 to Step 62, the high power reference cell is discarded.

Returning to FIG. 14, description will be made. High power direction peak
The reference cell output from the threshold value variation detection circuit 57 is input to the threshold calculation circuit 12 and operates in the same manner as in the first embodiment.

As a result, it is possible to prevent deterioration of the target detection performance due to unnecessary signals. Further, since the power ratios of two adjacent reference cells are only compared, the calculation can be performed faster than the comparison calculation of the average value as in the first embodiment.

Example 10. FIG. 16 is a block diagram showing an embodiment of the present invention. 16, reference numerals 1 to 10 and 12, 13 are the same as those in FIG.
Reference numeral 64 is a reference cell sorted in ascending order by the sort circuit 10, and calculates two signal power ratios adjacent to each other in order from the reference cell with the highest power, and the reference cell to be rejected is dropped based on the power ratio. This is a peak value fluctuation detection circuit for low power direction which determines and outputs the remaining reference cells.

Next, the operation will be described. An unnecessary signal such as an interference wave is superimposed on a target signal generated by the radio waves emitted by the transmitter 2 and the transmission antenna 1 being reflected by a target object such as an airplane, and this signal is received by the receiving antenna 3. After that, the sort circuit 1 operates in the same manner as in the first embodiment.
The reference cells sorted from 0 in ascending order are output and input to the small power direction peak value variation detection circuit 64. The operation of the small power direction peak value variation detection circuit 64 is shown in FIG.
7 shows. The reference cells input to the small power direction peak value fluctuation detection circuit 64 are r (1), r (2), ..., R (N).
(r (1) <r (2) <... <r (N) (N: number of reference cells)). First, in step 66, an initial value N-1 is set in the counter j. Next, the high-power reference cell is discarded by the operations from step 67 to step 69. That is, in step 67, r (j +
1) Check whether or not> K6 · r (j), and r (j + 1)>
While K6 · r (j) is established, the routine jumps to step 68, where it is checked whether j = 1 and if j> 1, the counter j is decremented in step 69 and the routine returns to step 67. When r (j + 1) ≦ K6 · r (j) in step 67, the process jumps to step 70, and high power reference cells r (j), r (j + 1), ..., R (N ) Is rejected as an unnecessary signal, and low power reference cells r (1), r (2),
..., only r (j) is output. Also, step 68
In the case where j = 1, that is, r (j + 1)> K6 · r (j) does not exist between 1 and N−1, all reference cells r (1) are regarded as having no unnecessary signal component. , R
(2), ..., R (N) are output.

Next, returning to FIG. 16, description will be made. The reference cell output from the small power direction peak value variation detection circuit 64 is input to the threshold calculation circuit 12, and the first embodiment is executed.
It operates in the same manner as in.

As a result, it is possible to prevent the deterioration of the target detection performance due to the unnecessary signal. Moreover, since the power ratio of two adjacent reference cells is calculated, the calculation can be performed faster than in the first embodiment. Further, since the number of reference cells with power larger than the normal set value is overwhelmingly smaller than the number of reference cells with power smaller than the set value, calculation from the larger power is faster than that of the first embodiment and smaller than the large power reference cells. The calculation becomes faster because the boundary of the power reference cell can be found and the processing can be completed.

Example 11. FIG. 18 is a block diagram showing an embodiment of the present invention. 18, reference numerals 1 to 29 are the same as those in FIG. 7, 57 is the same as the reference numeral in FIG. 14, and 64 is the same as the reference numeral in FIG.

Next, the operation will be described. The reception antenna 3 receives a signal in which an unnecessary signal such as an interference wave is superimposed on a target signal generated by the radio waves emitted by the transmitter 2 and the transmission antenna 1 being reflected by a target object such as an airplane. Thereafter, the same operation as in the first embodiment is performed, and the sorted reference cells are output from the sort circuit 10 in the ascending order, and the peak value fluctuation detection circuit 57 for the large power direction and the peak value fluctuation detection for the small power direction are detected. Input to the circuit 64. High power direction peak
The threshold value variation detection circuit 57 operates similarly to the fifth embodiment, and outputs the reference cells r (1), r (2), ..., R (N1). The small power direction peak value variation detection circuit 64 operates in the same manner as in the sixth embodiment, and the reference cells r (1), r (2), ...
., R (N2) is output. The signals output from the peak value fluctuation detection circuit 57 for high power direction and the peak value fluctuation detection circuit 64 for low power direction are input to the cell selection circuit 29. The cell selection circuit 29 operates similarly to the third embodiment, and outputs the reference cells r (1), r (2), ..., R (j). The reference cell output from the cell selection circuit 29 is input to the threshold calculation circuit 12 and operates similarly to the case of the first embodiment.

As a result, it is possible to prevent deterioration of the target detection performance due to unnecessary signals. In addition, since the power ratio of two adjacent reference cells is calculated from both directions of the reference cell with low power and the reference cell with high power, Embodiments 9 and 1
It can be calculated faster than 0 and with high accuracy.

Example 12. FIG. 19 is a block diagram showing an embodiment of the present invention. In FIG. 19, 1 to 64 are the same as the reference numerals in FIGS. 13 and 18, and the description will be omitted.

Next, the operation will be described. The reception antenna 3 receives a signal in which an unnecessary signal such as an interference wave is superimposed on a target signal generated by the radio waves emitted by the transmitter 2 and the transmission antenna 1 being reflected by a target object such as an airplane. Thereafter, the memory circuit 9 is processed in the same manner as in the first embodiment.
Outputs a reference cell and a cell of interest. The reference cell output from the memory circuit 9 is input to the reject cell recording circuit 71. The reject cell recording circuit 71 is the fourth embodiment.
It operates in the same way as and outputs the reference cell. The reference cell output from the reject cell recording circuit 71 is a source cell.
Input to the input circuit 10 and operates as in the seventh embodiment.

As a result, it is possible to prevent the deterioration of the target detection performance due to the unnecessary signal. Further, by recording the once discarded reference cells, it is possible to exclude the reference cells from the calculation target when the reference cells are detected in the subsequent processing, so that the calculation amount can be reduced. Therefore, the calculation is faster than in the twelfth embodiment.

By the way, in the above description, the case where the target detection processing is performed in the Doppler frequency direction with respect to the radar reception signal has been described, but it can also be used in the case where the target detection processing is performed in the distance direction. In this case, the coherent integrator circuit becomes unnecessary.

[0083]

As described above, according to the present invention, after the reference cells are sorted in ascending order, the reference cells are added one by one in order from the reference cell with the smaller power, and the average value is calculated each time. Then, every time the average value is obtained, a cell having a power equal to or higher than the set power is searched, and an unnecessary signal component is detected and discarded. Therefore, it is possible to prevent deterioration of the target detection performance due to the unnecessary signal.

Further, according to the present invention, after the reference cells are sorted in ascending order, the reference cells having higher power are sequentially rejected and the average value is calculated each time.
Each time the average value is obtained, a reference cell having a power equal to or higher than the set power is searched for, and an unnecessary signal component is detected and discarded. Therefore, it is possible to prevent the target detection performance from being deteriorated by the unnecessary signal. Moreover, there is an effect that the calculation becomes faster.

Further, according to the present invention, after the reference cells are sorted in the ascending order, cells are added one by one in order from the cell with the smallest power, and cells are discarded one by one from the cells with the largest power. Obtain the average value from both directions,
Since a cell having a power equal to or higher than the set power is searched for in each direction and unnecessary signal components are detected and discarded, it is possible to prevent the target detection performance from being deteriorated by the unnecessary signal. Further, since both the method of processing the reference cells in the order of low power and the method of processing the reference cells in the order of high power are used, the calculation accuracy is improved.

Further, according to the present invention, by recording the rejected cells, it is possible to reduce the calculation when the rejected cells are detected, which has the effect of speeding up the calculation.

Further, according to the present invention, after the reference cells are sorted in ascending order, the power ratio of two adjacent cells is calculated in order from the cell with the smallest power, and the cell with the power rapidly increasing. Is detected, and unnecessary signal components are detected and rejected. Therefore, it is possible to prevent deterioration of the target detection performance due to unnecessary signals.

Further, according to the present invention, after the reference cells are sorted in ascending order, the power ratio of two adjacent cells is calculated in order from the cell having the highest power, and the cell having the power rapidly decreasing. Is detected, and unnecessary signal components are detected and rejected. Therefore, it is possible to prevent deterioration of the target detection performance due to unnecessary signals. Moreover, there is an effect that the calculation becomes faster.

Further, according to the present invention, after the reference cells are sorted in the ascending order, the power ratio of two adjacent cells is calculated from both directions of the cell having the smaller power and the cell having the larger power, and the power is rapidly changed. Since an unnecessary signal component is detected and rejected by detecting the cell that is performing the operation, there is an effect that the deterioration of the target detection performance due to the unnecessary signal can be prevented. Further, since the power ratio of two adjacent reference cells is calculated from both directions of the low reference power reference cell and the high reference power cell, the calculation can be performed quickly and with high accuracy.

Further, according to the present invention, by further recording the rejected reference cells, it is possible to reduce the calculation when the rejected reference cells are detected, which has the effect of speeding up the calculation.

[Brief description of drawings]

FIG. 1 is a diagram showing the configuration of a radar device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a flow chart when performing a target detection process according to an embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a radar device according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a flow chart when performing target detection processing according to a second embodiment of the present invention.

FIG. 5 is a diagram showing the configuration of a radar device according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a flow chart when performing target detection processing according to a third embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a radar device according to a fourth embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a radar device according to a fifth embodiment of the present invention.

FIG. 9 is a diagram showing a flow chart when performing target detection processing according to a fifth embodiment of the present invention.

FIG. 10 is a diagram showing the configuration of a radar device according to a sixth embodiment of the present invention.

FIG. 11 is a flowchart showing a target detection process according to the sixth embodiment of the present invention.

FIG. 12 is a diagram showing the configuration of a radar device according to a seventh embodiment of the present invention.

FIG. 13 is a diagram showing a flow chart when performing target detection processing according to a seventh embodiment of the present invention.

FIG. 14 is a diagram showing the configuration of a radar device according to an eighth embodiment of the present invention.

FIG. 15 is a diagram showing the configuration of a radar device according to a ninth embodiment of the present invention.

FIG. 16 is a diagram showing a flow chart when performing target detection processing according to embodiment 9 of the present invention.

FIG. 17 is a diagram showing the structure of a radar device according to embodiment 10 of the present invention.

FIG. 18 is a diagram showing the structure of a radar device according to an eleventh embodiment of the present invention.

FIG. 19 is a diagram showing the configuration of a radar device according to Embodiment 12 of the present invention.

FIG. 20 is a diagram showing a configuration of a conventional radar device.

FIG. 21 is a diagram showing a configuration of a conventional apparatus for performing target detection processing.

FIG. 22 is a diagram showing a configuration of a memory circuit.

[Explanation of symbols]

 1 Transmitting Antenna 2 Transmitter 3 Receiving Antenna 4 Receiver 5 A / D Converter 6 Coherent Integrating Circuit 7 Square Detection Circuit 8 Cell Setting Circuit 9 Memory Circuit 10 Sort Circuit 11 High Power Direction Average Value Fluctuation Detection Circuit 12 Threshold calculation circuit 13 Alarm circuit 21 Small power direction average value fluctuation detection circuit 29 Cell selection circuit 39 Large power direction power ratio fluctuation detection circuit 48 Small power direction power ratio fluctuation detection circuit 57 Large power direction peak value fluctuation detection circuit 64 Small Power direction peak value fluctuation detection circuit 71 Rejected cell recording circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tomomasa Kondo 5-1, 1-1 Ofuna, Kamakura-shi Electronic Systems Research Center, Mitsubishi Electric Corporation

Claims (8)

[Claims] 1. A receiver for receiving a radio wave in which an unnecessary signal is superimposed on a target signal generated by reflecting on a target object, an A / D converter for converting the output of the receiver into a digital signal, and A coherent integrator circuit that inputs the output of the A / D converter and outputs a plurality of frequency components (cells); and a square detection circuit that obtains power for each cell from the output signal of the coherent integrator circuit, A cell setting circuit that sets a cell (target cell) targeted for target detection from the output signal of the square detection circuit and a cell (reference cell) in the vicinity thereof, and stores the output signal of the square detection circuit to set the cell setting. A memory circuit for outputting the cell of interest and the reference cell set by the circuit; a sort circuit for rearranging the reference cells output from the memory circuit in ascending order of power; For the output signal of the road, the average value is calculated in order from the reference cell group with the lowest power, and each time the average value is calculated, unnecessary signals are detected and rejected by checking for the presence or absence of reference cells above a certain set power, and the remaining reference cells are High power direction average value fluctuation detection circuit for outputting, a threshold value calculation circuit for obtaining an average value of the reference cells output from the high power direction average value fluctuation detection circuit, and multiplying the average value by a coefficient, and the threshold value calculation A radar device comprising: an alarm circuit for comparing the output signal from the circuit with the size of the target cell output from the memory circuit to determine the presence or absence of the target signal for the target cell. 2. A receiver for receiving a radio wave in which an unnecessary signal is superimposed on a target signal generated by reflecting on a target object, an A / D converter for converting the output of the receiver into a digital signal, and A coherent integrator circuit that inputs the output of the A / D converter and outputs a plurality of frequency components (cells); and a square detection circuit that obtains power for each cell from the output signal of the coherent integrator circuit, From the output signal of this square detection circuit, the cell of interest that is the target of target detection, a cell setting circuit that sets a reference cell in the vicinity thereof, the output signal of the square detection circuit is stored, and the cell setting circuit set A memory circuit that outputs the cell of interest and the reference cell, a sort circuit that sorts the reference cells output from the memory circuit in ascending order of power, and an output signal of the sort circuit. Then, the reference cells with higher power are rejected one by one, and the average value is calculated each time.Every time the average value is determined, unnecessary signals are detected and rejected by checking whether there are reference cells with a certain power or more. Then, a small power direction average value fluctuation detection circuit that outputs the remaining reference cells and an average value of the reference cells output from the small power direction average value fluctuation detection circuit are obtained, and a threshold value that multiplies the average value by a coefficient A calculation circuit, and an alarm circuit for comparing the output signal from the threshold calculation circuit and the size of the target cell output from the memory circuit and determining the presence or absence of a target signal for the target cell. Rader device. 3. The output of the sort circuit is connected to the small-power-direction average-value fluctuation detection circuit in parallel with the large-power-direction average-value fluctuation detection circuit, and is output from the large-power-direction average-value fluctuation detection circuit. 3. The radar device according to claim 2, further comprising: a cell selection circuit that selects and outputs the reference cell and the reference cell output from the small power direction average value variation detection circuit. 4. A reference cell output from the memory circuit is provided with a reject cell recording circuit for recording cells rejected by the high power direction average value fluctuation detection circuit or the low power direction average value fluctuation detection circuit. The radar device according to claim 1, 2, or 3. 5. A receiver for receiving a radio wave in which an unnecessary signal is superimposed on a target signal generated by reflecting on a target object, an A / D converter for converting the output of the receiver into a digital signal, and A coherent integrator circuit that inputs the output of the A / D converter and outputs a plurality of cells, a square-law detector circuit that obtains power for each cell from the output signal of the coherent integrator circuit, and this square-law detect circuit Cell of interest to be the target of the target detection from the output signal of the cell, the cell setting circuit for setting the reference cell in the vicinity thereof, the output signal of the square wave detection circuit is stored, and the cell of interest and the cell of interest set by the cell setting circuit A memory circuit that outputs a reference cell, a sort circuit that sorts the reference cells output from the memory circuit in ascending order of power, and an output signal of the sort circuit, Of two adjacent signal power ratios in order from a smaller reference cell, determine the reference cell to be rejected based on the power ratio, and a large power direction peak value fluctuation detection circuit that outputs the remaining reference cells , A threshold value calculating circuit for obtaining an average value of the reference cells output from the high power direction peak value variation detecting circuit and multiplying the average value by a coefficient, an output signal from the threshold value calculating circuit and the cell setting A radar device comprising: an alarm circuit for comparing the size of the target cell output from the circuit and determining the presence or absence of a target signal for the target cell. 6. A receiver for receiving a radio wave in which an unnecessary signal is superimposed on a target signal generated by reflecting on a target, an A / D converter for converting the output of the receiver into a digital signal, and A coherent integrator circuit that inputs the output of the A / D converter and outputs a plurality of cells, a square-law detector circuit that obtains power for each cell from the output signal of the coherent integrator circuit, and this square-law detect circuit Cell of interest to be the target of the target detection from the output signal of the cell, the cell setting circuit for setting the reference cell in the vicinity thereof, the output signal of the square wave detection circuit is stored, and the cell of interest and the cell of interest set by the cell setting circuit A memory circuit that outputs a reference cell, a sort circuit that sorts the reference cells output from the memory circuit in ascending order of power, and an output signal of the sort circuit, Of two adjacent signal power ratios in order from the larger reference cell, the reference cell to be rejected is determined based on the power ratio, and a small power direction peak value fluctuation detection circuit that outputs the remaining reference cells , A threshold value calculating circuit for obtaining an average value of the reference cells output from the small power direction peak value variation detecting circuit and multiplying the average value by a coefficient, an output signal from the threshold calculating circuit and the cell setting circuit A radar device comprising: an alarm circuit that compares the size of the target cell output from the device and determines the presence or absence of a target signal for the target cell. 7. The high power direction peak value fluctuation detection circuit connected in parallel with the low power direction peak value fluctuation detection circuit is added to the output of the sort circuit, and the high power direction peak value fluctuation detection circuit is added. −
7. A cell selection circuit for selecting and outputting the reference cell output from the peak value fluctuation detection circuit and the reference cell output from the low power direction peak value fluctuation detection circuit. The radar device according to item 6. 8. A reference cell output from the memory circuit is provided with a reject cell recording circuit for recording cells rejected by the high power direction average value fluctuation detection circuit or the low power direction average value fluctuation detection circuit. 8. The radar device according to claim 5, 6, or 7.