JPH1068771A - Radar device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the deterioration of target detecting performance when an acceleration target is existed in the receiving signal of a radar. SOLUTION: A receiving signal received by a receiving antenna 1 is divided into respective frequency spectral in a coherent integral circuit 7 and amplitude is detected in an amplitude detecting circuit 8. An acceleration compensation set circuit 10 sets an acceleration and an integral path over Doppler cell of a plurality of frequency bands is set based on this acceleration. A cell of the receiving signal on this integral path is provided to an acceleration compensation integral circuit 11. The acceleration compensation integral circuit 11 performs coherent integration by finding the sum of the inputted cell. Incoherent integral result for a plurality of acceleration and a plurality of initial cells are stored in a memory circuit 12 and a termination determining circuit 13 and a target is finally detected by a target detecting circuit 15 and alarming is performed by an alarm circuit 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radar device for performing a target detection process from a radar reception signal.

[0002]

2. Description of the Related Art FIG. 21 is a diagram showing a configuration of a conventional radar apparatus for performing target detection processing.
Is a transmitter connected to this transmitting antenna 1 to form a transmitting beam, 3 is a receiving antenna, 4 is band limiting, phase detection,
A receiver 5 that performs amplification converts the received signal output from the receiver 4 from an analog signal to a digital signal.
The D converter 6 stores the output signal of the A / D converter 5 for a certain period of time CPI (Coherent Pulse Interval).
A memory circuit 7 for outputting the signal stored at the PI interval, improving a signal-to-noise power ratio of an output signal of the memory circuit 6;
A coherent integration circuit that divides the frequency component into n and outputs the resultant as n cells, and an amplitude detection circuit 8 that performs amplitude detection on an output signal of the coherent integration circuit 7.

A memory circuit 9 stores a signal output from the amplitude detection circuit 8 in units of nCPI, stores the signal in units of CPI a predetermined number of times N, and outputs them collectively. 51 is a memory circuit. 9, an incoherent integration circuit for summing the cells in the same frequency band for each frequency band and outputting the result, and a target detection circuit 52 for determining the presence or absence of a target based on the result. It is. The target detection circuit 52 sets a target cell (target cell) and a cell near the target cell (reference cell), compares the power of the target cell with the average power of the reference cell, and determines whether the target cell has a target. I do. Reference numeral 16 denotes an alarm circuit that issues an alarm when the target detection circuit 52 determines that there is a target. A cell referred to in this specification is also called a Doppler cell.

FIG. 22 shows, for example, McGRAW-HILL BOOK COM
PANY RADAR DESIGNPRINCIPLESP75 FIG. 3 is a configuration diagram of a radar device having a target detection function shown in FIG.
Reference numeral 53 denotes a matched filter circuit that passes a signal received by the receiving antenna in a predetermined band, reference numeral 8 denotes an amplitude detection circuit that detects the amplitude of an output signal of the matched filter circuit 53, and reference numeral 51 denotes an input circuit similar to FIG. It is a coherent integration circuit.

FIG. 23 is a diagram illustrating details of the coherent integration circuit 7 of FIG. The coherent integration circuit 7 is composed of n matched filter circuits having different pass frequency bands in order to obtain an n-band signal. Reference numeral 71 denotes a matched filter circuit which is connected to the memory circuit 6 and allows components of the frequency band f1 of the output signal of the memory circuit 6 to pass. Similarly, 72 to 7n are matched filter circuits that pass components in the frequency bands f2 to fn, respectively.

Next, the operation will be described. A target signal generated by reflecting radio waves emitted by the transmitter 2 and the transmission antenna 1 to an airplane or the like is received by the reception antenna 3. The signal received by the receiving antenna 3 is band-limited by the receiver 4, and further subjected to phase detection and amplification. The signal output by the receiver 4 is a signal including an amplitude value and a phase, and is called a complex signal. Further, the receiver 4 superimposes the receiver noise of the received signal.

The A / D converter 5 converts an analog signal input from the receiver 4 into a digital signal. The signal converted into a digital signal by the A / D converter 5 is input to the memory circuit 6. The memory circuit 6 stores the input signals at predetermined time intervals (CPI) and collectively outputs the input signals to the next amplitude detection circuit 8. The signal output from the memory circuit 6 is input to a coherent integration circuit 7. As shown in FIG. 23, the coherent integration circuit 7 includes a plurality of matched filter circuits 71 to 7n, and different matched pass bands are assigned to the respective matched filter circuits 71 to 7n. Therefore, the matched filter circuits 71 to 71
7n are input to n matched filter circuits 7
1 to 7n, it is divided into the number (n) of matched filter circuits 71 to 7n. Each of the matched filter circuits 71 to 7n outputs the signal component of the assigned band to the next amplitude detection circuit 8. The n signals output from the coherent integration circuit 7 are subjected to amplitude detection by an amplitude detection circuit 8, and the amplitude values are stored in a memory circuit 9.
The memory circuit 9 repeats the operation of storing the output signal of the amplitude detection circuit 8 a predetermined number of times N, and then outputs the stored signal. Therefore, the signal S9 output from the memory circuit 9 becomes amplitude value data represented by an n × N matrix as shown in FIG. ICPI
When the signal amplitude value of the J cell is expressed as s (I, J), the memory circuit 9 outputs the signal s (I, J) (I = 1, 2,.
, N) (J = 1, 2,..., N) are output. The incoherent integration circuit 51 calculates the signal amplitude ps (J) (J = 1, 2,..., N) of the J cell by the following equation.

[0008]

(Equation 1)

The incoherent integration circuit 51 calculates the signal amplitude in each cell by the above equation and outputs the result. Therefore, the output of the incoherent integration circuit 51 is
For each frequency band (cell), the value is the sum of the NCPI amplitude values for each cell.

In the target detection circuit 52, a cell (target cell) for which the presence / absence of the target is determined for the signal output from the incoherent integration circuit 51 and a cell near the target (reference cell) are set. The threshold is set from the average power of the target cell, and if the power of the cell of interest is equal to or higher than the threshold, the target is set. All Doppler cells are set as cells of interest, and the presence or absence of a target is determined and transmitted to the alarm circuit 16. The alarm circuit 16 generates an alarm indicating that there is a target for a Doppler cell determined to have a target.

[0011]

Since the conventional radar apparatus is configured as described above, if the target is accelerating, the Doppler frequency changes for each CPI, so that the sum of the same Doppler cell is calculated. There is a problem that the target signal component is not integrated in the processing to be performed. That is, since the frequency of the radio wave reflected from the target changes every moment,
The cell in which the radio wave appears changes, for example, to the second cell, the third cell,..., The nth cell. Therefore, there is a problem that the target cannot be sufficiently grasped only by adding the second cell for all the CPIs.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and has as its object to enable detection of an acceleration target even when the target exists.

[0013]

In a radar apparatus according to the present invention, coherent integration means for decomposing a radar reception signal into a plurality of cells for each frequency component at predetermined time intervals and outputting the cells is to be detected. Acceleration setting means for setting a target predicted acceleration in advance; and a cell in which the target signal is expected to be present among the plurality of cells based on the predicted acceleration, for each of the predetermined time intervals. And an incoherent integration means for setting an integration path by selecting as a selected cell, performing incoherent integration on the integration path, and a detection means for detecting a target based on the result of the incoherent integration. It is.

Further, the acceleration setting means sets the predicted acceleration by changing it according to time.

Further, the incoherent integration means includes:
Integral path setting for setting an integral path by selecting, as a selected cell, a cell in which the target signal is expected to be present among the plurality of cells based on the predicted acceleration at each of the predetermined time intervals. Means, and, among the selected cells on the integration path, one selected cell of interest is set as a cell of interest, and a power ratio between the average power of the selected cell having a power smaller than that of the cell of interest and the power of the cell of interest is detected. Unnecessary signal detection means for discriminating between the selected cell rejected as an unnecessary signal component and the selected cell output as a required signal component based on the detection result, and the selected cell output by the unnecessary signal detection means, And integrating means for performing coherent integration.

Further, the incoherent integration means includes:
Integral path setting for setting an integral path by selecting, as a selected cell, a cell in which the target signal is expected to be present among the plurality of cells based on the predicted acceleration at each of the predetermined time intervals. Means, a plurality of the selected cells, a first set that is a set of selected cells having power equal to or less than that of the one selected cell of interest, and a set of selected cells having a larger power than the selected cell of interest. It is divided into a second set, and it is determined whether or not to reject the second signal as an unnecessary signal component from the selected cell based on a difference between the average powers of the first set and the second set. Accordingly, unnecessary signal detecting means for rejecting unnecessary signal components of the selected cells and outputting the remaining selected cells, and performing incoherent integration on the selected cells output by the unnecessary signal detecting means. A minute unit, is characterized in that comprises a.

Further, the incoherent integration means includes:
Integral path setting for setting an integral path by selecting, as a selected cell, a cell in which the target signal is expected to be present among the plurality of cells based on the predicted acceleration at each of the predetermined time intervals. Means, a sorting means for rearranging the plurality of selected cells in order according to the magnitude of power, and, for the selected cells rearranged by the sorting means, detecting a power ratio between adjacent selected cells,
The selected cell rejected as an unnecessary signal component based on the detection result, unnecessary signal detecting means for discriminating the selected cell outputting as a necessary signal component, and incoherent integration of the selected cell output by the unnecessary signal detecting means The radar device according to claim 1, further comprising: integrating means for performing the following.

Further, the integration path setting circuit selects an integration path based on the power of the cell.

[0019] The acceleration setting means may include a weighting means for multiplying the radar reception signal by a predetermined weight, wherein the signal deterioration after the incoherent integration becomes equal to or less than a predetermined value based on the weight. As described above, a set interval of acceleration is set, a plurality of the predicted accelerations are output according to the set interval, and the incoherent integration means includes:
An incoherent integration is performed by setting the integration path for each of the plurality of predicted accelerations.

Further, coherent integration means for decomposing a radar reception signal into a plurality of cells for each frequency component at predetermined time intervals and outputting the same, acceleration setting means for presetting a predicted acceleration of a target to be detected, Based on the predicted acceleration, a search path is set by selecting, as a selected cell, a cell in which the target signal is expected to be present among the plurality of cells, corresponding to each of the predetermined time intervals. Search path setting means, measurement phase difference detection means for detecting a phase difference between adjacent selected cells of the selected cells arranged in order of reception time as a measurement phase difference, and position of the selected cells based on the predicted acceleration. Theoretical phase difference calculation means for calculating a theoretical value of the phase difference as a reference phase difference, and detection for detecting a target based on an error between the corresponding measured phase difference and the reference phase difference It is that a stage.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, an embodiment of the present invention will be described. FIG. 1 is a diagram showing an overall configuration of the radar apparatus according to the first embodiment. 1 is a transmitting antenna, 2 is a transmitter connected to the transmitting antenna 1 to form a transmitting beam, 3
Is a receiving antenna, 4 is a receiver that performs band limiting, phase detection, and amplification, 5 is an A / D converter that converts a received signal output from the receiver 4 from an analog signal to a digital signal,
Reference numeral 6 denotes an output signal of the A / D converter 5 for a certain time CPI.
(Coherent Pulse Interval), and a memory circuit for outputting the signal stored at the CPI interval. 7 improves the signal-to-noise power ratio of the output signal of the memory circuit 6 and divides it into n for each frequency component to obtain n signals. A coherent integration circuit 8 outputs a cell and an amplitude detection circuit 8 performs amplitude detection on an output signal of the coherent integration circuit 7.

A memory circuit 9 stores a signal output from the amplitude detection circuit 8 in units of CPI, stores the signal in units of CPI N times a predetermined number of times, and then outputs them collectively. Assuming that the acceleration is uniform, an acceleration to be compensated and an initial cell are set, a Doppler frequency that changes for each CPI is calculated based on the acceleration, and an input is made so that fluctuations in the Doppler frequency due to the acceleration are compensated. An acceleration compensation setting circuit 11 sets an integration path for coherent integration. An acceleration compensation integration circuit 11 performs incoherent integration along the initial cell set by the acceleration compensation setting circuit 10 and the integration path.

A memory circuit 12 for storing the signal transmitted from the acceleration compensation integration circuit 11 and outputting the stored signal when incoherent integration is performed for all of the accelerations assumed for the set initial cell; 13
Is an end determination circuit that outputs the signal transmitted from the memory circuit 12 as it is, and outputs an end signal when the incoherent integration processing is completed for all the initial cells;
14 is output from the memory circuit 12 and the end determination circuit 13
Is a memory circuit that stores the signal that has passed through and outputs the stored signal when an end signal that outputs the stored signal is transmitted from the end determination circuit 13.

Reference numeral 15 designates a cell (target cell) for which the presence or absence of a target is to be determined with respect to a signal output from the memory circuit 14, and a cell near the target (reference cell) in the initial Doppler frequency direction and the acceleration direction. ,
A target detection circuit that compares the power of the cell of interest with the average power of the reference cell and determines whether or not there is a target for the cell of interest. Reference numeral 16 denotes an alarm circuit that issues an alarm when the target detection circuit 15 determines that there is a target.

Next, the operation will be described. A target signal generated by reflecting radio waves emitted by the transmitter 2 and the transmission antenna 1 on a target such as an airplane is received by the reception antenna 3. The signal received by the receiving antenna 3 is band-limited, phase-detected, and amplified by the receiver 4, and A / D
After being converted from an analog signal to a digital signal by the converter 5, it is input to the memory circuit 6. After a certain time CPI has elapsed, the memory circuit 6 outputs the stored digital signal. The signal output from the memory circuit 6 is input to the coherent integration circuit 7, where the signal-to-noise power ratio is improved and divided into frequency components in units of cells.
The output signal of the coherent integration circuit 7 is amplitude-detected by an amplitude detection circuit 8 and then stored in a memory circuit 9. The memory circuit 9 repeats the operation of storing the output signal of the amplitude detection circuit 8 processed in CPI units N times, and then outputs the stored signals collectively. The signal output from the memory circuit 9 is input to the acceleration compensation setting circuit 10.

The acceleration compensation setting circuit 10 sets an initial cell of a target signal when performing incoherent integration and a cell (integration path) to be subjected to incoherent integration in each CPI based on the assumed initial velocity and acceleration of the target. And
The signal S10 of the cell on this integration path is transmitted to the acceleration compensation integration circuit 11. Here, in the output signal S10 of the acceleration setting circuit shown in FIG. 1, the hatched portion is set and output as a cell on the integration path.

The acceleration compensation integration circuit 11 performs incoherent integration along the transmitted integration path, and transmits the result to the memory circuit 12. At the same time, when incoherent integration is performed for all of the accelerations assumed for the initial cell, the all-acceleration end signal is sent to the memory circuit 1
2 When all the initial cells have been completed, an all-cell end signal is transmitted to the memory circuit 12.
The transmission of the all acceleration end signal and the all cell end signal is transmitted to the acceleration compensation setting circuit 10 via the memory circuit.

In the memory circuit 12, when the result of incoherent integration is transmitted from the acceleration compensation integration circuit 11, the signal is stored. When the full acceleration end signal is transmitted, the stored signal and the full acceleration end signal are output. When the all-cell end signal is transmitted, it outputs the signal stored in the memory circuit 12 and the all-cell end signal.

When only the stored signal is output from the memory circuit 12, the end determination circuit 13 outputs the output to the memory circuit 14. In addition, the memory circuit 12
When the signal stored in the memory circuit 12 and the all-cell end signal are transmitted, the signal stored in the memory circuit 12 and the end of all cells are output to the memory circuit 14, and the acceleration compensation setting circuit 10
The initialization cell is again transmitted to all the initial cells so that the processing of the acceleration compensation circuit 10 and the acceleration compensation integration circuit 11 is performed again.

In the memory circuit 14, when only the signal stored in the memory circuit 12 is transmitted, the signal is stored. When the all-cell end signal is transmitted simultaneously with the signal, the stored signal is targeted. Output to the detection circuit 15. Since the result of incoherent integration with the acceleration changed for each initial cell is input to the memory circuit 14, two-dimensional signals in the initial cell direction and the acceleration direction are stored.

The target detection circuit 15 receives two-dimensional data S14 in the initial cell direction and the acceleration direction. The target detection circuit 15 sets a cell (target cell) for which the presence or absence of a target is to be determined for a signal output from the memory circuit 14 and a cell (reference cell) near the target cell in the initial cell direction and the acceleration direction. Then, a threshold is set from the average power of the reference cell. If the power of the cell of interest is equal to or higher than the threshold, a target is set. here,
For all the Doppler cells output from the memory circuit 14, the presence or absence of a target is determined and transmitted to the alarm circuit 16. The alarm circuit 16 issues an alarm indicating that there is a target for a cell determined to have a target.

FIG. 2 shows the acceleration compensation setting circuit 10 of FIG.
5 is a flowchart when the operations of the acceleration compensation integration circuit 11, the memory circuit 12, and the end determination circuit 13 are realized by software using a general-purpose processor (not shown). Here, the processing realized by this flowchart is basically the same as the circuit shown in FIG.

First, the memory circuit 9 shown in FIG.
When the data of N (CPI) is accumulated, the process is started from step S0 in FIG. 2, and in step S100, an initial cell is set. The initial cell is, as shown in FIG.
Cells of 1 CPI are allocated in order. In FIG. 3, n
= 7, in which case the first cell is initially selected as the initial cell (case (a)) and step S
When the process returns from step 106 to step S100 again, the next second cell is selected as the initial cell. Similarly, up to the n-th cell is sequentially selected as an initial cell. (B) shows the case where the fourth cell as the initial cell is (c).
, The seventh cell is selected as the initial cell.
In FIG. 3, Ncell0 indicates a selected initial cell. In FIG. 3, the vertical axis represents the time axis (CP
I), the horizontal axis is a frequency axis (divided for each predetermined frequency band), and cells painted in black represent cells expected to have a target. These cells serve as integration paths in incoherent integration.

What kind of target can be detected by this integration path will be described with reference to FIG. The Doppler frequency reflected from the target depends on the speed of the target. Therefore, if there is a target moving at a certain speed V1 at 1 CPI, a large peak appears in the cell of n = 1 corresponding to this speed V1. If this target moves with a positive acceleration, the speed will gradually increase and 3CPI
At this time, the speed becomes V2. Here, when the target is moving toward the radar, the Doppler frequency of the reflected wave increases according to the speed V2. Then, the next cell (n =
A large peak appears in 2), and the peak of the original cell (n = 1) becomes smaller. Hereinafter, similarly, at 5CPI, the target speed becomes faster than the speed V2, a large peak appears in the next cell (n = 3), and the peak of the original cell (n = 2) decreases. Since the integration path shown in FIG. 3A coincides with the peak of the reflected wave from the target as described above, the signal from the reflected wave can be captured without leakage.

Next, the process proceeds to step S101, where a target acceleration Aj (j = 1, 2,..., A) is set, and an integration path obtained from the target acceleration Aj and the initial cell is calculated. Then, the cells Sjk (k = 1, 2) on this integration path
2,..., N) are extracted. The calculation of this integration path can be obtained by the following equation.

[0036]

(Equation 2)

Here, a can be obtained from the target acceleration Aj. FIG. 4 is a diagram showing integration paths of the three target accelerations A1, A2, and A3 when the initial cell Ncell0 = 1. Among the cells arranged in a lattice, the cells painted in black are the integration paths set. There is a relationship of A1 <A2 <A3 between the target accelerations Aj, and a is 1, 2, 5 respectively. In other words, when the target accelerates, the frequency of the reflected wave changes every moment due to the Doppler effect,
The cell where the target is located also moves. The setting of the integration path is performed in order to predict the movement of the cell and follow the reflected wave from the target. Then, the data of the cell on the selected integration path (the power of the frequency component of the reflected wave) is sequentially stored as Sjk.

Next, in step S102, the power sum Pij of Sjk is obtained. This power sum Pij is calculated by the following equation.

[0039]

(Equation 3)

Subsequently, the operation proceeds to step S103, where Pij calculated in step S102 is stored in the memory. Then, in step S104, it is determined whether the processing has been completed for all assumed accelerations. This determination is based on a variable A representing the number of acceleration patterns set in advance.
Is larger than a variable j which is a counter of the acceleration currently being processed, and when it is larger, it means that the processing has not been completed for all the accelerations yet. If the processing has not been completed for all the accelerations, the process proceeds to step S105, and 1 is added to j which is the acceleration counter.
Is added, the process returns to step S101, and the next acceleration A
The processing for j is performed. On the other hand, when it is determined that the processing has been completed for all the accelerations, the process proceeds to the next step S106.

In step S106, it is determined whether the processes in steps S100 to S104 have been completed for all the initial cells. This determination is made based on whether or not the variable i representing the number of the initial cell currently being processed is equal to or greater than the total initial cell number n. If it is determined that the processing has not been completed for all the initial cells, the process proceeds to step S107, 1 is added to i, the acceleration counter j is initialized (i = 1), and then the process returns to step S100. . Then, the processing from step S100 is started again for the next initial cell.
On the other hand, when it is determined that the processing has been completed for all the initial cells, the process proceeds to the next step Se, and the incoherent integration processing in consideration of the acceleration is completed.

When the process reaches step Se, the memory circuit 14 of FIG. 1 stores two-dimensional data on the initial cell and the acceleration as shown in S14. Thereafter, the processing is performed as described with reference to FIG. Embodiment 1
Is configured as described above, even if the Doppler frequency changes with time due to acceleration motion, the incoherent integration is performed by compensating for the change in Doppler frequency, so that the target detection performance can be prevented from deteriorating due to acceleration motion. .

Embodiment 2 Embodiment 2 is an embodiment of a radar apparatus capable of accurately detecting a reflected wave from a target moving at an uneven acceleration.

Embodiment 2 of the present invention will be described with reference to FIG. 5, the same reference numerals as those in FIG. 1 denote the same or corresponding parts. 17 sets a non-acceleration to be compensated and an initial cell assuming that the target acceleration is non-uniform acceleration, calculates a Doppler frequency that changes for each CPI based on the acceleration, and calculates a variation in Doppler frequency due to the acceleration. An acceleration compensation setting circuit for setting an integration path for incoherent integration so as to be compensated; and an incoherent integration along a path set by the unequal acceleration compensation setting circuit, and an incoherent integration along the integration path. Is completed, the unequal acceleration compensation integration circuit outputs the integration result to the memory circuit 12.

Next, the operation will be described. The basic operation is the same as in the first embodiment. Therefore, the incoherent integration process is the same as the flowchart shown in FIG. The difference is that the acceleration compensation circuit 10 and the acceleration compensation integration circuit 11 of the first embodiment are replaced by the unequal acceleration compensation setting circuit 17 and the unequal acceleration compensation integration circuit 18 in the second embodiment.

The operation of the unequal acceleration compensation setting circuit 17 and the unequal acceleration compensation integration circuit 18 will now be described. The non-uniform acceleration compensation setting circuit 17 sets an integration path changing at non-uniform acceleration in various patterns in order to capture a target moving at non-uniform acceleration. The pattern of the integration path is obtained by a mathematical formula given in advance as described in the first embodiment. For example, it is obtained from the initial cell Ncell0 and the rate of change of acceleration. Alternatively, a preset pattern may be stored in a memory and sequentially output to the unequal acceleration compensation integration circuit.

FIG. 6 shows an example of an integration path output from the unequal acceleration compensation setting circuit 17, wherein a black cell is a cell set as an integration path. (A) is an integration path corresponding to a case where the acceleration of the target is gradually decreasing, (b) is an integration path corresponding to a case where the acceleration of the target is gradually increasing,
(C) is an integration path corresponding to the case where the target suddenly changes the acceleration.

The integration path output from the unequal acceleration compensation setting circuit 17 may include an integration path corresponding to the case where the target moves at a constant acceleration as described in the first embodiment.

The non-uniform acceleration compensation setting circuit 17 sets the above-described integration path, and outputs data of cells on the integration path to the non-uniform acceleration compensation integration circuit 18. Upon receiving the cell data from the non-uniform acceleration compensation setting circuit 17, the non-uniform acceleration compensation integration circuit 18 calculates the sum of these data and outputs the sum to the memory circuit 12. Hereinafter, the first embodiment
The same operation as described above is performed, and a target of non-uniform acceleration is detected.

In the second embodiment, since the configuration is as described above, it is possible to prevent the target detection performance from deteriorating due to the non-uniform acceleration motion, and to catch the target moving at the non-uniform acceleration.

Embodiment 3 FIG. The third embodiment is an implementation of a radar apparatus that accurately captures a reflected wave from a target moving at the assumed acceleration by rejecting reflected wave data from a target moving at a speed other than the assumed acceleration. It is a form of.

Embodiment 3 of the present invention will be described with reference to FIG. FIG. 7 is a functional block diagram showing the configuration of the radar apparatus according to the third embodiment. In FIG. 7, the same reference numerals as those in FIG. Reference numeral 19 denotes a sort circuit for sorting the signals output from the acceleration compensation setting circuit 10 in ascending order of power, and 20 denotes an average value obtained by adding the signals sorted by the sort circuit 19 one by one in ascending order of power to obtain an average value. This is an average value fluctuation detection circuit that detects and rejects signal components of power equal to or higher than the level and outputs the remaining signal components.

FIGS. 9 and 10 show the operation of the radar apparatus. FIG. 9 is a diagram illustrating an example of an integration path for incoherent integration. Each cell receives the data of the square of the amplitude value, that is, the data of the magnitude of the electric power, and forms a two-dimensional matrix by the cell columns and the CPI provided for each frequency band. This point is the same as in FIGS. 3 and 4, but for convenience of explanation, the integration path is indicated by a straight line indicated by R1, black cells indicate high power, and white cells indicate low power. And

FIG. 10 is a graph for explaining the output value and the like of the sort circuit 19 in the integration path of FIG. (A) shows the output of the acceleration compensation setting circuit 10, (b) shows the output of the sort circuit 19, and (c) shows the output of the average value fluctuation detection circuit 20.

In the case shown in FIG. 9, the acceleration of the target is small, and the acceleration assumed by the reflected wave acceleration compensation setting circuit 10 is large, and the accelerations of the two are different.
However, on the integration path R1 based on the assumed acceleration, the data of the reflected wave of the target is included (and the power is large), and when the sum of the data on the integration path R1 is simply obtained. Although there is no target having the assumed acceleration, a relatively large value is obtained, which is not preferable. The third embodiment aims to improve such a situation.

Next, the operation will be described. Since the basic operation is the same as that of the first embodiment, the characteristic operation of the third embodiment will be described. Acceleration compensation setting circuit 10
Are output to the sorting circuit 19 and are sorted in ascending order of power.
For example, when the acceleration compensation setting circuit 10 sets an integration path as shown by R1 in FIG. 9 and outputs a value as shown in FIG. 10A, the output of the sorting circuit is as shown in FIG. Become like Symbol Sjk described in each bar graph
(K = 1,..., 6) are the cell numbers output by the acceleration compensation setting circuit 10 and are the same as Sjk in the flowchart of FIG. Then, the sorting circuit 19 determines Sj1, Sj2, Sj5, Sj6, Sj based on the sorting result.
3, and output in the order of Sj4. Here, assuming that the power of the white cell in FIG. 9 is 1, the power of the black cell is six times that of the black cell.

Subsequently, using the output of the sorting circuit, the average value fluctuation detecting circuit 20 extracts a reflected wave from the target moving at the acceleration, and removes other reflected waves. FIG. 8 shows a sort circuit 19 and an average value fluctuation detection circuit 20.
6 is a flowchart showing the processing of FIG. Step S200
Is a process performed by the sort circuit 19, steps S201 to S20.
7 is a process performed by the average value fluctuation detection circuit 20. First,
Starting from step S0, the output of the acceleration compensation setting circuit 10 is sorted in step S200. The sorting result is output as Sk (k = 1, 2,..., N).

Next, in step S201, a variable k is initialized to 1, and in step S202, a threshold value for removing unnecessary reflected waves is calculated by the following equation.

[0059]

(Equation 4)

Here, K1 is a constant, and is appropriately set according to the sensitivity of removal. When the value of K1 is large, even if the target acceleration is significantly different from the acceleration set by the acceleration compensation setting circuit 10, it is easy to catch the reflected wave from the target. Conversely, when the value of K1 is small, Even if the difference between the target acceleration and the acceleration set by the acceleration compensation setting circuit 10 is small, the reflected wave from the target is easily removed.

Next, the process proceeds to step S203, where it is determined whether or not k <N. Since N is equivalent to the number of data output from the sort circuit 19, it can be seen whether the reflected wave to be removed has been checked to the end. If it is determined that k <N is not satisfied, after adding 1 to k in step S206,
The process moves to step S207. On the other hand, if k <N, the process moves to step S204.

In step S204, Th1> Sk + 1
Determine whether or not. Sk + 1 is the data next to the data for which the threshold value has been calculated in step S202. By comparing the threshold value with Th1 and the next data Sk + 1,
The point at which the power changes significantly can be examined. For example, in FIG. 10B, Sj1, Sj2, Sj5, Sj
Up to 6, there is almost no change in power, and therefore the average value of power is constant. On the other hand, the power rapidly increases from Sj3. In step S204, this change point is found, and in subsequent step S207, processing for removing data after this change point is performed. As can be seen from FIG. 9, Sj3 and Sj4 are considered to be the data of the reflected waves from the target having an acceleration that moves the fourth and fifth cells in the 6CPI, and the currently set integration The data is different from the acceleration assumed on the road R1. Therefore, by examining the change point, it is possible to remove the data of the reflected wave of the target having an acceleration other than the acceleration assumed by the acceleration compensation setting circuit 10 (hereinafter, referred to as an unnecessary signal component).

If Th1> Sk + 1, the next data is also considered to be a reflected wave of the assumed acceleration. Therefore, to check the next data, step S205 is performed.
Adds 1 to the variable k, returns to step S202, and performs the same processing. On the other hand, when Th1> Sk + 1 is not satisfied, the next data is considered to be an unnecessary signal component, and the process proceeds to step S207.

In step S207, S1,..., Sk
Output data up to. The variable k is set in step S204.
Is set at the boundary between the assumed acceleration data and the other data by the processing up to step, and if no unnecessary signal component is found from all the data, step S2
Since all data are set to be output at 06, if data of S1,..., Sk is output, only data of the assumed acceleration can be output. For example, in FIG. 10C, k = 4, and Sj3, Sj4
(The data stored in S5 and S6, respectively) are removed, and the data of Sj1, Sj2, Sj5, and Sj6 (the data stored in S1 to S4, respectively)
Only output. Then, finally, the processing ends in step Se.

The processing result of the unnecessary signal rejection processing as described above is transmitted from the average value fluctuation detection circuit 20 to the acceleration compensation integration circuit 1.
1 and thereafter operates in the same manner as in the first embodiment.

In the third embodiment, the processing described with reference to FIG.
Although the processing has been described as above, software processing by a general-purpose processor may be used. In that case, Embodiment 1
Steps S101 and S1 in FIG.
8 is inserted between the two output values S1,..., Sk of step S207 are represented by Sjk (k = 1,.
., N).

In the third embodiment, since the data of the reflected wave from the target moving at an acceleration other than the assumed acceleration, that is, the power sum Pij on the integration path can be obtained without including the unnecessary signal component, more accurate data can be obtained. The reflected wave from the target moving at the assumed acceleration can be detected.

Embodiment 4 The fourth embodiment is an embodiment of a radar apparatus that rejects unnecessary signal components by a method different from that of the third embodiment and tries to accurately capture a reflected wave from a target moving at an assumed acceleration. .

Embodiment 4 of the present invention will be described with reference to FIG. FIG. 11 is a functional block diagram showing the configuration of the radar apparatus according to the fourth embodiment.
Alternatively, the same reference numerals as those in FIG. 7 indicate the same or corresponding parts. 2
Reference numeral 1 denotes a power ratio change detection circuit that divides a plurality of cells sorted by the sorting circuit 19 into two regions and calculates a ratio of average power in each region to determine a cell to be rejected.

Next, the operation will be described. Since the basic operation is the same as that described in the third embodiment, the characteristic operation of the fourth embodiment will be described with reference to FIG. FIG. 12 is a flowchart for explaining the operation of the sort circuit 19 and the power ratio fluctuation detection circuit 21 of FIG. Step S301 is processing performed by the sort circuit 19, and steps S302 to S309 are processing performed by the power ratio fluctuation detection circuit 21.

First, when the sorting circuit 19 receives cells on the integration path from the acceleration compensation setting circuit 10, the processing starts from step S0, and in step S301, the cells are sorted in ascending order of power, and the result is sorted into the next power. Output to the ratio fluctuation detection circuit 21. Next, the process proceeds to step S302, where 2
A variable j representing a boundary for calculating two area power ratios is initialized to 1.

In the next step S303, the average power ratio P (j) of the two regions divided by the j-th cell is calculated. For example, when this processing is described using the output of the sort circuit in FIG. 10B, when j = 4, one area is S1
The cells up to S4 and the other area are divided into areas S5 to S6, and the ratio of the average power in both areas is calculated.

Specifically, the first to j-th cells (S1 to S1)
The average power P01 (j) of Sj) and the average power P02 (j) of the (j + 1) to N-th cells (Sj + 1 to SN) are obtained by the following equations, and finally the power ratio P (j) is obtained.

[0074]

(Equation 5)

Next, the flow shifts to step S304, where it is determined whether j <N. If j <N, step S305
After adding 1 to j, the process returns to step S303, and the same processing is repeated for the next boundary j. On the other hand, j <N
If not, the process moves to the next step S306. As a result, when moving to step S306, step S30
By repeating 3, N-1 power ratios P (j) are calculated.

In step S306, step S303
Among the N-1 power ratios P (j) calculated in step (1), the power ratio with the largest power ratio is selected, and the power ratio at that time is stored as P, and the boundary cell number is stored as j.

Next, the process proceeds to step S307, where the maximum power ratio P obtained in step S306 is compared with the threshold value Th2 to check whether Th2> P. Step S306
In the processes up to, the obtained cell is divided into two regions, and the maximum value of the obtained boundary cell j is N-1. Therefore, it is not determined whether the Nth cell is an unnecessary component signal. The process of step S307 is a process for making this determination. When the maximum power ratio P is large, the possibility of an unnecessary signal component is large, and when the maximum power ratio P is small, the possibility of an unnecessary signal component is small. An appropriate value is set to determine whether or not the second cell is an unnecessary signal component.
When Th2> P, there is a high possibility that the signal is not an unnecessary signal component.
(Ie, output without rejecting the Nth cell), and then go to step S309. On the other hand, when Th2> P is not satisfied, there is a high possibility that the signal component is an unnecessary signal component, and the process directly proceeds to cell step S309.

In step S309, the data (S1 to Sj) of the first to j-th cells are transferred to the next acceleration compensation integration circuit 11
Output to At this time, the data after the (j + 1) th is discarded without being output because it is determined in the processing up to step S307 that it is an unnecessary signal component. And
Finally, the unnecessary signal rejection processing described above in step Se ends.

In the fourth embodiment, the processing described with reference to FIG.
Although the processing has been described as one processing, the processing may be software processing by a general-purpose processor. In that case, the processing steps S101 and S101 of FIG.
The processing of FIG. 12 is inserted between steps 102 and 102, and step S309 is performed.
, Sj are represented by Sjk (k = 1, k = 1) in FIG.
.., N).

In the fourth embodiment, since the data of the reflected wave from the target moving at an acceleration other than the assumed acceleration, that is, the power sum Pij on the integration path can be obtained without including the unnecessary signal component, the fourth embodiment is more accurate. The reflected wave from the target moving at the assumed acceleration can be detected.

Embodiment 5 Embodiment 5 aims at rejecting unnecessary signal components and accurately capturing a reflected wave from a target moving at an assumed acceleration by a method different from the above embodiment. 1 is an embodiment of a radar device that performs the following.

Embodiment 5 of the present invention will be described with reference to FIG. FIG. 13 is a functional block diagram showing the configuration of the radar apparatus according to the fifth embodiment. In FIG.
Alternatively, the same reference numerals as those in FIG. 7 indicate the same or corresponding parts. 2
2 calculates the power ratio of two signals adjacent to each other in order from the cell with the lowest power for a plurality of cells sorted by the sorting circuit 19, determines a cell to be rejected based on the power ratio, and determines the remaining cells. This is a peak value fluctuation detection circuit to be output.

Next, the operation will be described. Since the basic operation is the same as that described in the third embodiment, the characteristic operation of the fifth embodiment will be described with reference to FIG. FIG. 14 is a flowchart illustrating the operation of the sort circuit 19 and the peak value change detection circuit 22 of FIG. Step S401 is a process performed by the sort circuit 19;
Steps S402 to S407 are the peak value fluctuation detection circuit 2
This is the process to be performed.

First, when the sorting circuit 19 receives cells on the integration path from the acceleration compensation setting circuit 10, the processing starts from step S0, and in step S401, the cells are sorted in ascending order of power, and the result is sorted to the next peak. Output to the value change detection circuit 22. Next, the process proceeds to step S402,
A variable j indicating a cell to be compared is initialized to 1.

Next, the procedure moves to step S403, where the j-th cell is compared with the (j + 1) -th cell. Comparison is Sj + 1>
This is performed using the equation of K3 · Sj. Here, the coefficient K3 is set to an appropriate value in consideration of preventing unnecessary signal components from being output. If the coefficient K3 is too large, unnecessary signal components are likely to be output. Conversely, if the coefficient K3 is too small, not only unnecessary signal components but also necessary signal components are removed. Sj
If +1> K3 · Sj is not satisfied, it is determined that the (j + 1) th cell is not an unnecessary signal component, and the next step S404
Move on to On the other hand, when Sj + 1> K3 · Sj, j
Since the (+1) th cell is determined to be an unnecessary signal component, the process exits the loop and moves to step S406.

In step S404, it is determined whether all cells have been checked. If j <N, 1 is added to the variable j in step S405, and the process returns to step S403 to perform the same processing for the next cell. On the other hand, j <N
If not, the loop processing is stopped and the next step S40
Move to 6.

In step S406, N is substituted for a variable j. That is, since it is determined in step S404 that all cells are not unnecessary signal components, the next step S40
This is to specify that all cells are to be output in step 7.

Next, the flow advances to step S407 to output the first to j-th cells. By the processing up to this point, it has been determined that no unnecessary signal components are included in the cells up to the j-th cell, and the data of these cells is stored in the acceleration compensation integration circuit 1.
Output to 1. On the other hand, the data of the (j + 1) th and subsequent cells are not output because they are unnecessary signal components. Finally, the process proceeds to step Se to complete the unnecessary signal component rejection processing.

In the fifth embodiment, the processing described with reference to FIG.
Although the processing has been described as one processing, the processing may be software processing by a general-purpose processor. In that case, the processing steps S101 and S101 of FIG.
The processing of FIG. 14 is inserted between 102 and step S407.
, Sj are represented by Sjk (k = 1, k = 1) in FIG.
.., N).

In the fifth embodiment, since the data of the reflected wave from the target moving at a speed other than the assumed acceleration, that is, the power sum Pij on the integration path can be obtained without including the unnecessary signal component, the fifth embodiment is more accurate. The reflected wave from the target moving at the assumed acceleration can be detected.

Embodiment 6 Embodiment 6 is an embodiment of a radar apparatus for judging the presence or absence of a target based on the detection result of a phase difference.

Embodiment 6 of the present invention will be described with reference to FIG. FIG. 15 is a functional block diagram showing the configuration of the radar apparatus according to the sixth embodiment. The same reference numerals as those in FIG. 1 denote the same or corresponding parts. Numeral 9 is similar to the memory circuit 9 of FIG. 1, but stores different complex data output from the coherent integrator 7 and processed in units of CPI. That is, the memory circuit outputs the stored signal when the operation of storing the complex signal is repeated a predetermined number of times. The memory circuit 9 has N (CPI) ×
n (Doppler cell) complex signals are stored. Also,
This complex signal includes information of the amplitude and phase by the real part and the imaginary part.

Reference numeral 23 designates an acceleration to be compensated assuming that the target acceleration is equal, calculates a Doppler frequency that changes for each CPI based on the acceleration,
(CPI) × n (Doppler cell) acceleration compensation setting circuit for setting a search path for calculating a phase variation of a complex signal;
Reference numeral 24 denotes a phase variation detection circuit that calculates the phase variation based on the search path set by the acceleration compensation setting circuit. The memory circuit 12, the end determination circuit 13, and the memory circuit 14 are the same as those in the first embodiment, but differ in that the stored data is not the integration result based on the amplitude value but the above-described phase fluctuation amount. 25 denotes n stored in the memory circuit 14
A target detection circuit for detecting a target by detecting a phase fluctuation amount smaller than a predetermined threshold value Th3 with respect to a phase fluctuation amount of (Doppler cell) × A (acceleration).

Next, the operation will be described. First, the memory circuit 9 stores the complex signal output by the coherent integration circuit 7 by a predetermined amount (n × N). Then, the complex signal is transmitted to the acceleration setting circuit 23. In the acceleration compensation setting circuit 23, an initial cell i and an acceleration Aj are set, and a search path for calculating a phase variation is obtained from the initial cell i and the acceleration Aj. Then, the complex signal on the search path, the initial cell i, and the acceleration Aj are output to the next phase variation detection circuit 24.

The phase fluctuation detecting circuit 24 calculates the theoretical value of the phase difference (measured value) of the cells on the adjacent search path from the received complex signal and the phase difference obtained from the initial cell i and the acceleration Aj. Then, the phase variation amount σij ²
Is calculated. Condition where the target is set (initial cell i, acceleration Aj) when moving at, since the measured value is the same as the theoretical value, the higher the amount of phase change Shigumaij ² small target to set conditions There is likely to be.

The phase variation σij ² is stored in the memory circuit 12
After storing the j phase variation amounts σij ² , the output is output to the next end determination circuit 13. In the end determination circuit 13,
After storing the n × A phase fluctuation amounts σij ^2, they are collectively output to the next memory circuit 14. In the next target detection circuit 25, the threshold value Th is set for n × A phase fluctuation amounts σij ^2.
Those smaller than 3 are detected as targets.

FIG. 16 shows the acceleration compensation setting circuit 1 described above.
0 is a flowchart for explaining processing of a phase fluctuation amount detection circuit 24, a target detection circuit 25, and the like. In this flowchart, steps S501 and S502 are the acceleration compensation setting circuit 23, steps S503 to S505 are the phase fluctuation amount detection circuit 24, and step S510 is the target detection circuit 2.
5 is processing to be performed respectively.

When an n × N complex signal is stored in the memory circuit 9, the process proceeds to step S501, where an initial cell is set, and a variable j representing the number of the acceleration being processed is initialized to 1. The initial cell Ncell0 is a cell having a number represented by a variable i. When this step S501 is first executed, i
= 1 is set.

Next, the process proceeds to step S502, where a target acceleration Aj is set, and a search path is obtained from the initial cell i and the acceleration Aj. Then, a complex signal of the cell Sjk on this search path is extracted. The method for setting the initial cell and the method for setting the acceleration can be performed in the same manner as described in Embodiment 1 or 2.

Subsequently, the flow shifts to step S503, where a measured phase difference dΦ _k = Φ _{k + 1} -Φ _k (k = 1,..., N−1) between adjacent cells on the search path is calculated. Here, Φ _k is the phase of the k-th cell. As a result, N−1 measurement phase differences dΦ _k are obtained.

Next, the process proceeds to step S504, and the theoretical phase difference dΦ _0k of the assumed acceleration Aj is calculated. Step S
At 505, the phase fluctuation amount is calculated. The amount of phase fluctuation can be obtained by the following equation.

[0102]

(Equation 6)

Subsequently, in step S506, it is determined whether or not the processing has been completed for all accelerations. If it is determined that j ≧ A is not satisfied, 1 is added to j in step S507, and the process returns to step S502. The same processing is performed for the next acceleration. If j ≧ A, the next step S
Move to 508. In step S508, it is determined whether the processing has been completed for all the initial cells. When it is determined that i ≧ N is not satisfied, in step S509, 1 is added to i, and the process returns to step S501 to perform the same processing for the next initial cell. If i ≧ N, the process moves to the next step S510.

In step S510, step S508
The target detection is performed based on the phase fluctuation amount obtained by the processes up to. The method of target detection is nxA (all)
This is performed by searching for a phase fluctuation amount equal to or less than a preset threshold value Th3 from the phase fluctuation amount and determining that there is a target on a search path having the phase fluctuation amount. Finally, in step Se, the above-described target detection processing ends, and the result is output to the alarm circuit 16.

The alarm circuit 16 issues an alarm indicating that there is a target for a Doppler cell determined to have a target.

In the sixth embodiment, the target detection processing is performed by the acceleration setting circuit 23, the phase fluctuation amount detection circuit 24, and the target detection circuit 25. However, the processing shown in FIG. You may. Further, the acceleration set by the acceleration compensation setting circuit 23 may be not only the uniform acceleration but also the non-uniform acceleration as described in the second embodiment.

Since the sixth embodiment is configured as described above, it is possible to prevent the target detection performance from deteriorating due to the acceleration motion, and to accurately detect even the acceleration target.

Embodiment 7 Embodiment 7 is an embodiment for reducing the amount of calculation and realizing high-speed processing by rejecting an integral path which is considered unnecessary.

FIG. 17 is a functional block diagram showing the configuration of the radar apparatus according to the seventh embodiment. In FIG.
5 denote the same or corresponding parts. An integration path selection circuit 26 sets an integration path while rejecting unnecessary integration paths based on cell power.

Next, the operation will be described. Since the basic operation is the same as that of the second embodiment, a characteristic part of the seventh embodiment will be described. FIG. 18 is a flowchart illustrating the integration path selection processing of the integration path selection circuit 26. First, when the amplitude value data from the amplitude detection circuit 8 is stored in the memory circuit 9, the process is started from step S0, and in step S600, j = 1 and m0 = 1 are initialized. Here, j represents the CPI number, and m0 represents the number of the integration path. In step S601, 1C
Substitute the initial cell in PI for PATH (j, m0). PATH (j, m0) represents the m0-th integration path in which the integration path is set up to the jCPI.

In step S602, the cell selected by jCPI is taken out, and S0 (j, m0)
far. In step S603, S0 (j, m0)
Are selected as the integration cells from jCPI to j + 1. In step S604, step S604
The cells S (j + 1, m0, k) to be integrated for each candidate of the integration path selected by 603 (k = 1,
2, ...) are set. In step S605,
A predetermined number L is selected from the larger power of S (j + 1, m0, k).

In step S606, PATH
Since L new integration paths are set up to j + 1 CPI following (j, m0, k), j + 1C
The integration path PATH (j + 1, m1) set up to PI
0) (m10 is a number indicating the integration path determined up to the j + 1th CPI at the present time) and L new ones are prepared, and the selected cells S (j +
, M0, k) are added, and the integration path PATH (j
+1, m1). Generally, in jCPI, j-1
For each integration path set up to CPI, a new L
Since new integration paths are set, the number of integration paths is L to the j-1 power up to jCPI.

In step S607, m0 sets L to j-1
If it is equal to the raised value, the process moves to step S609. If the number is less than 1, 1 is added to m0 in step S608, and the process returns to step S602 to set an integration path up to j + 1 CPI for the next integration path. Step S60
In step 9, when j = N, it is determined that the integration path has been determined, and the flow shifts to step S611. Otherwise, j +
In order to set the integration path up to 1 CPI, step S61
At 0, 1 is added to j and m0 is initialized to 1, and the process returns to step S602 to repeat the same process for the next cell.

In step S611, it is determined whether or not the processing in steps S600 to 610 has been completed for all the initial cells. If not, the flow returns to step S600 to perform the same processing for the next initial cell. On the other hand, when it is determined that the process has been completed for all the initial cells, the process proceeds to step Se, and the integration path setting process ends.

Thereafter, the operation is the same as in the second embodiment. However, since all the integration paths have already been set when the processing of step S611 is completed, the target detection is performed in one pass, and the all-cell end and all-acceleration end signals performed in the second embodiment are used. No need to send and receive

In the seventh embodiment, step S605
Since the integration paths considered to be unnecessary are rejected as shown in (2), the number of integration paths that increase explosively can be suppressed, and the target can be detected at high speed.

Eighth Embodiment An eighth embodiment is an embodiment in which the set interval of the integration path is appropriately set to prevent the deterioration of the target signal.

FIG. 19 is a functional block diagram illustrating a configuration of a radar apparatus according to Embodiment 8 of the present invention. 19, the same symbols as those in FIG. 1 represent the same or corresponding parts. 27 is a weighting circuit for setting weights used in the coherent integration circuit 7, 50 is for setting an interval of acceleration to be compensated in the acceleration compensation setting circuit 10 based on the filter shape of the weight set by the weighting circuit 27, An integration interval setting circuit for transmitting the interval to the acceleration compensation setting circuit 10.

Next, the operation will be described. A target signal generated by reflecting radio waves emitted by the transmitter 2 and the transmitting antenna 1 to an airplane or the like is received by the receiving antenna 3. Thereafter, the same operation as in the first embodiment is performed, and a signal is transmitted from the memory circuit 6 to the weighting circuit 27 in CPI units. The weighting circuit 27 multiplies an input signal and outputs the weighted signal in order to control a signal-to-noise power ratio improvement effect, a leakage component of another Doppler frequency, and the like.

The weight set by the weight circuit 27 affects the characteristics of the acceleration compensation integration circuit 11. FIG. 20 shows the weighting circuit 2
7 shows the relationship between the weight set in 7 and the characteristics of the acceleration compensation integration circuit 11. The horizontal axis represents the target acceleration, and the vertical axis represents the power resulting from the incoherent integration. When the acceleration compensation interval is d, the characteristic obtained by performing incoherent integration assuming the target acceleration a and the target acceleration a +
From the characteristics obtained by performing incoherent integration assuming d, the target acceleration b at which the power is degraded by pd regardless of which integration is performed is calculated.

Since the characteristics of the acceleration compensation integration circuit 11 correspond to the weights set by the weighting circuit 27, the compensation interval d and the maximum value pd of power degradation uniquely correspond to each other when the weights are set. The integration interval setting circuit 28 calculates a compensation interval d based on a preset power degradation tolerance pd due to incoherent integration and the weight used in the weighting circuit 27.
And the acceleration compensation setting circuit 10 and the end determination circuit 13
To communicate. Acceleration compensation setting circuit 10 and end determination circuit 1
3 sets an integration path based on the transmitted compensation interval d, and thereafter operates in the same manner as in the first embodiment.

In the eighth embodiment, by appropriately setting the acceleration compensation interval, signal degradation can be suppressed within an allowable range. Therefore, it is possible to surely prevent the target detection performance from deteriorating due to acceleration motion. it can.

By the way, in the first to fifth, seventh and seventh embodiments,
In FIG. 8, detection is performed using the amplitude detector 8, but detection can also be performed using a square detector or the like. Also, when performing the target detection processing, the threshold is calculated from the average power of the cells near the cell of interest that is the target of the target detection, but processing using a fixed threshold, processing for detecting peak power, etc. The target detection processing can be performed by other processing.

[0124]

Since the present invention is configured as described above, it has the following effects. Coherent integration means for decomposing a radar reception signal into a plurality of cells for each frequency component at a predetermined time interval and outputting the same, acceleration setting means for presetting a predicted acceleration of a target to be detected, based on the predicted acceleration Setting an integration path by selecting, as a selected cell, a cell in which the target signal is expected to be present among the plurality of cells, corresponding to each of the predetermined time intervals, , And a detecting means for detecting a target based on the result of the incoherent integration, the target can be detected even if an accelerating target exists.

Further, since the acceleration setting means changes and sets the predicted acceleration according to time, the target can be detected even if there is a target that is not accelerating at non-uniform acceleration.

Further, the incoherent integration means includes:
Integral path setting for setting an integral path by selecting, as a selected cell, a cell in which the target signal is expected to be present among the plurality of cells based on the predicted acceleration at each of the predetermined time intervals. Means, and, among the selected cells on the integration path, one selected cell of interest is set as a cell of interest, and a power ratio between the average power of the selected cell having a power smaller than that of the cell of interest and the power of the cell of interest is detected. Unnecessary signal detection means for discriminating between the selected cell rejected as an unnecessary signal component and the selected cell output as a required signal component based on the detection result, and the selected cell output by the unnecessary signal detection means, And integration means for performing coherent integration, so that even if there is a target that moves at an acceleration other than the acceleration set by the acceleration setting means, Signal from the incoherent integration section, can be accurately capture the target because it is not integrated, also, it is possible to prevent false alarms.

Further, the incoherent integration means includes:
Integral path setting for setting an integral path by selecting, as a selected cell, a cell in which the target signal is expected to be present among the plurality of cells based on the predicted acceleration at each of the predetermined time intervals. Means, a plurality of the selected cells, a first set that is a set of selected cells having power equal to or less than that of the one selected cell of interest, and a set of selected cells having a larger power than the selected cell of interest. It is divided into a second set, and it is determined whether or not to reject the second signal as an unnecessary signal component from the selected cell based on a difference between the average powers of the first set and the second set. Thus, unnecessary signal detecting means for rejecting unnecessary signal components of the selected cells and outputting the remaining selected cells, and performing incoherent integration on the selected cells output by the unnecessary signal detecting means. And the integration means, even if there is a target moving at an acceleration other than the acceleration set by the acceleration setting means, the signal from the target is not integrated by the incoherent integration means, so that the target can be accurately captured. In addition, false alarms can be prevented.

Further, the incoherent integration means includes:
Integral path setting for setting an integral path by selecting, as a selected cell, a cell in which the target signal is expected to be present among the plurality of cells based on the predicted acceleration at each of the predetermined time intervals. Means, a sorting means for rearranging the plurality of selected cells in order according to the magnitude of power, and, for the selected cells rearranged by the sorting means, detecting a power ratio between adjacent selected cells,
The selected cell rejected as an unnecessary signal component based on the detection result, unnecessary signal detecting means for discriminating the selected cell outputting as a necessary signal component, and incoherent integration of the selected cell output by the unnecessary signal detecting means Therefore, even if there is a target that moves at an acceleration other than the acceleration set by the acceleration setting means, the signal from the target is not integrated by the incoherent integration means, so that the target can be accurately captured. And false alarms can be prevented.

Further, the integration path setting circuit selects an integration path based on the power of the cell, so that when setting an integration path, a cell having a high possibility that a target exists is determined based on the power and the operation is performed. Since cells are selected in a specific manner, the number of integration paths to be set can be reduced, and high-speed processing can be performed.

[0130] Further, there is provided weighting means for multiplying the radar reception signal by a predetermined weight, and the acceleration setting means makes the signal deterioration after the incoherent integration based on the weight equal to or less than a predetermined value. As described above, a set interval of acceleration is set, a plurality of the predicted accelerations are output according to the set interval, and the incoherent integration means includes:
By setting the integration path for each of the plurality of predicted accelerations and performing incoherent integration, the intervals of the accelerations are set in consideration of the weights, so that even when the weights change, signal deterioration is predetermined. Within the range,
Target detection accuracy can be improved.

Further, coherent integrating means for decomposing the radar reception signal into a plurality of cells for each frequency component at predetermined time intervals and outputting the same, acceleration setting means for presetting a predicted acceleration of a target to be detected, Based on the predicted acceleration, a search path is set by selecting, as a selected cell, a cell in which the target signal is expected to be present among the plurality of cells, corresponding to each of the predetermined time intervals. Search path setting means, measurement phase difference detection means for detecting a phase difference between adjacent selected cells of the selected cells arranged in order of reception time as a measurement phase difference, and position of the selected cells based on the predicted acceleration. Theoretical phase difference calculating means for calculating a theoretical value of the phase difference as a reference phase difference, and detecting means for detecting a target based on an error between the corresponding measured phase difference and the reference phase difference Because having a even goal has accelerated exists can be detected targets.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing a configuration of a radar device according to Embodiment 1 of the present invention.

FIG. 2 is a flowchart illustrating an integration process of acceleration compensation according to the first embodiment of the present invention.

FIG. 3 is a diagram showing an integration path of a cell when an initial cell is changed in the first embodiment of the present invention.

FIG. 4 is a diagram showing an integration path of a cell when the acceleration is changed in the first embodiment of the present invention.

FIG. 5 is a functional block diagram showing a configuration of a radar device according to Embodiment 2 of the present invention.

FIG. 6 is a diagram showing an integration path of a cell when changing at an unequal acceleration in the second embodiment of the present invention.

FIG. 7 is a functional block diagram showing a configuration of a radar device according to Embodiment 3 of the present invention.

FIG. 8 is a flowchart illustrating unnecessary signal rejection processing according to Embodiment 3 of the present invention.

FIG. 9 is a diagram illustrating an integration path of incoherent integration and power intensity according to Embodiment 3 of the present invention.

FIG. 10 is a graph illustrating output values of a sort circuit and the like according to a third embodiment of the present invention.

FIG. 11 is a functional block diagram showing a configuration of a radar apparatus according to Embodiment 4 of the present invention.

FIG. 12 is a flowchart illustrating an unnecessary signal rejection process according to Embodiment 4 of the present invention.

FIG. 13 is a functional block diagram showing a configuration of a radar device according to Embodiment 5 of the present invention.

FIG. 14 is a flowchart illustrating an unnecessary signal rejection process according to Embodiment 5 of the present invention.

FIG. 15 is a functional block diagram showing a configuration of a radar device according to Embodiment 6 of the present invention.

FIG. 16 is a flowchart illustrating a target detection process according to Embodiment 6 of the present invention.

FIG. 17 is a functional block diagram showing a configuration of a radar device according to Embodiment 7 of the present invention.

FIG. 18 is a flowchart illustrating an integration path setting process according to the seventh embodiment of the present invention.

FIG. 19 is a functional block diagram showing a configuration of a radar device according to Embodiment 8 of the present invention.

FIG. 20 is a diagram illustrating characteristics of incoherent integration according to the eighth embodiment of the present invention.

FIG. 21 is a functional block diagram showing a configuration of a conventional radar device.

FIG. 22 is a functional block diagram showing a configuration of a conventional device for performing incoherent integration.

FIG. 23 is a functional block diagram showing a configuration of a conventional coherent integration device.

[Explanation of symbols]

1 transmission antenna, 2 transmitter, 3 reception antenna, 4 receiver, 5 A / D converter, 6 memory circuit, 7 coherent integration circuit, 8 amplitude detection circuit, 9 memory circuit, 10 acceleration compensation setting circuit,
11 acceleration compensation integration circuit, 12 memory circuit,
13 End judgment circuit, 14 Memory circuit, 15 Target detection circuit, 16 Alarm circuit, 17 Non-uniform acceleration compensation setting circuit, 18 Non-uniform acceleration compensation integration circuit, 19
Sort circuit, 20 average value fluctuation detection circuit, 21
Power ratio fluctuation detection circuit, 22 peak value fluctuation detection circuit,
24 phase fluctuation detection circuit, 25 target detection circuit,
26 integration path selection circuit, 27 weight circuit, 28 integration interval setting circuit, 51 incoherent integration circuit,
52 target detection circuit, 53 matched filter circuit

Continuation of the front page (72) Inventor Taiyoshi Yoshi 2-3-2 Marunouchi, Chiyoda-ku, Tokyo, Japan Mitsubishi Electric Corporation (72) Inventor Takahiko Fujisaka 2-3-2 Marunouchi, Chiyoda-ku, Tokyo, Mitsubishi Electric Co., Ltd.

Claims (8)

[Claims] 1. Coherent integration means for decomposing a radar reception signal into a plurality of cells for each frequency component at a predetermined time interval and outputting the same, acceleration setting means for presetting a predicted acceleration of a target to be detected, Based on the predicted acceleration, an integration path is set by selecting, as a selected cell, a cell in which the target signal is expected to be present among the plurality of cells, corresponding to each of the predetermined time intervals. A radar apparatus comprising: incoherent integration means for performing incoherent integration on the integration path; and detection means for detecting a target based on a result of the incoherent integration. 2. The radar apparatus according to claim 1, wherein said acceleration setting means changes and sets said predicted acceleration according to time. 3. The incoherent integration means, based on the predicted acceleration, selects a cell in which the target signal is expected to be present among the plurality of cells at every predetermined time interval as a selected cell. An integration path setting means for setting an integration path by selecting, among the selected cells on the integration path, one selected cell of interest as a cell of interest, and an average power of a selected cell having power smaller than that of the cell of interest. An unnecessary signal detecting means for detecting a power ratio with respect to the power of the cell of interest and discriminating the selected cell to be rejected as an unnecessary signal component and the selected cell to be output as a required signal component based on the detection result; 3. An integrating means for performing incoherent integration on a selected cell output by the signal detecting means. On-board radar equipment. 4. The incoherent integration means selects a cell in which the target signal is expected to be present among the plurality of cells as a selected cell at each of the predetermined time intervals based on the acceleration. An integration path setting means for setting an integration path by performing a first set of a plurality of selected cells having power equal to or less than the power of one selected selected cell; Is also divided into a second set, which is a set of selected cells having a large power, and the second signal is used as an unnecessary signal component based on a difference between the average power of the first set and the average power of the second set. By determining whether or not to reject from the selected cell, unnecessary signal detecting means for rejecting the unnecessary signal component of the selected cell and outputting the remaining selected cells, and output by the unnecessary signal detecting means. The radar apparatus according to claim 1, further comprising: integrating means for performing incoherent integration on the selected cell. 5. The incoherent integration means, based on the predicted acceleration, sets, at every predetermined time interval, a cell in which the target signal is expected to be present among the plurality of cells as a selected cell. Integration path setting means for setting an integration path by selecting; sorting means for rearranging the plurality of selected cells in order according to the magnitude of electric power; and adjacent selected cells for the selected cells rearranged by the sorting means. An unnecessary signal detecting means for detecting a power ratio between the selected cells and discriminating the selected cell to be rejected as an unnecessary signal component and the selected cell to output as a required signal component based on the detection result; And integrating means for performing incoherent integration on the selected cell. Over da apparatus. 6. The integration path setting circuit according to claim 2, wherein the integration path setting circuit selects an integration path based on the power of the cell.
A radar device according to item 1. 7. A weighting means for multiplying a radar reception signal by a predetermined weight, wherein said acceleration setting means makes a signal deterioration after said incoherent integration based on said weight equal to or less than a predetermined value. As described above, the set intervals of the predicted acceleration are set, and the plurality of the predicted accelerations are output according to the set intervals. The incoherent integration means sets the integration path for each of the plurality of the predicted accelerations and performs the incoherent integration. 3. The radar device according to claim 1, wherein 8. A coherent integrating means for decomposing a radar reception signal into a plurality of cells for each frequency component at predetermined time intervals and outputting the same, an acceleration setting means for presetting a predicted acceleration of a target to be detected, Based on the predicted acceleration, a search path is set by selecting, as a selected cell, a cell in which the target signal is expected to be present among the plurality of cells, corresponding to each of the predetermined time intervals. Search path setting means, measurement phase difference detection means for detecting a phase difference between adjacent selected cells of the selected cells arranged in order of reception time as a measurement phase difference, and position of the selected cells based on the predicted acceleration. Theoretical phase difference calculating means for calculating a theoretical value of the phase difference as a reference phase difference, and a detecting means for detecting a target based on an error between the corresponding measured phase difference and the reference phase difference. Radar apparatus provided with a door.