JPH07245338A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

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Publication number
JPH07245338A
JPH07245338A JP3330994A JP3330994A JPH07245338A JP H07245338 A JPH07245338 A JP H07245338A JP 3330994 A JP3330994 A JP 3330994A JP 3330994 A JP3330994 A JP 3330994A JP H07245338 A JPH07245338 A JP H07245338A
Authority
JP
Japan
Prior art keywords
hydrogen
semiconductor device
compound semiconductor
resistance
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3330994A
Other languages
Japanese (ja)
Inventor
Takeshi Kikawa
健 紀川
信一郎 ▲高▼谷
Shinichiro Takatani
Junji Shigeta
淳二 重田
Nobutaka Fuchigami
伸隆 渕上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi ULSI Engineering Corp
Hitachi Ltd
Original Assignee
Hitachi ULSI Engineering Corp
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi ULSI Engineering Corp, Hitachi Ltd filed Critical Hitachi ULSI Engineering Corp
Priority to JP3330994A priority Critical patent/JPH07245338A/en
Publication of JPH07245338A publication Critical patent/JPH07245338A/en
Pending legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To provide a semiconductor device which has a small amount of impurity and levels produced by uncoupled hands and has a high-quality high- resistance layer and its manufacturing method. CONSTITUTION:A high-resistance layer 11 is formed by radiating atomic hydrogen 10 upon the surface of a compound semiconductor substrate 12 and diffusing the hydrogen into the semiconductor from the surface. When the dose of the atomic hydrogen 10 is controlled, the resistance of the layer 11 can be adjusted to a desired value. Therefore, when the hydrogen 10 is supplied to the surface of the substrate 12, the diffusion of the hydrogen into the semiconductor is accelerated. In addition, since the hydrogen introduced into the semiconductor is coupled with other impurities and uncoupled hands and makes levels caused by these point defects inactive, a high-quality high-resistance layer containing a small amount of levels can be obtained. Therefore, not only the high-frequency characteristics, isolation between elements in integrated circuits, etc., can be improved, but also an equivalent circuit having a prescribed resistance value can easily be obtained by controlling the load resistance in a resistance element.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、化合物半導体装置及び
その製造方法に関わる。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来の化合物半導体装置では、例えば素
子間に硼素イオン(B+)やクロムイオン(Cr+)、或
いはH2 +等の不純物イオンを注入するイオン注入法で高
抵抗層を設けることにより、素子間の絶縁が行なえるこ
とが例えば特開平1−184874号公報に開示されて
いる。また、抵抗素子を作製する場合には、TaNやW
SiN等の高抵抗金属の薄膜を用いて幅数μm、長さ数
十μmの抵抗用の配線を設けている。
2. Description of the Related Art In a conventional compound semiconductor device, for example, a high resistance layer is provided between elements by an ion implantation method in which impurity ions such as boron ions (B + ) or chromium ions (Cr + ) or H 2 + are implanted. By doing so, it is disclosed in, for example, Japanese Patent Laid-Open No. 1-184874 that elements can be insulated. Further, when manufacturing a resistance element, TaN or W
A resistance wiring having a width of several μm and a length of several tens μm is provided using a thin film of a high resistance metal such as SiN.

【0003】[0003]

【発明が解決しようとする課題】ところで上記従来技術
により注入されたイオン自身、及びイオン注入によって
結晶中の結合が切断されて生ずる未結合手は、しばしば
深い準位を作り電荷を捕獲する。このため緩和時間の長
い充放電が起こり、半導体装置の高速動作を阻害し、特
性を劣化させるという問題があった。また、抵抗素子で
は抵抗用の配線のために素子の面積を縮小することが困
難であり、集積度を上げることができないという問題も
あった。したがって、本発明の目的は上記従来の問題点
を解消することにあり、電荷を捕獲する深い準位のない
良好な高抵抗層を有する化合物半導体装置及びその製造
方法を提供することにある。
By the way, the ions themselves implanted by the above-mentioned conventional technique and the dangling bonds generated by breaking the bond in the crystal by the ion implantation often form deep levels and trap charges. Therefore, there is a problem that charging / discharging with a long relaxation time occurs, which hinders high-speed operation of the semiconductor device and deteriorates the characteristics. Further, in the resistance element, it is difficult to reduce the area of the element due to the wiring for resistance, and there is a problem that the degree of integration cannot be increased. Therefore, an object of the present invention is to solve the above-mentioned conventional problems, and to provide a compound semiconductor device having a good high resistance layer without deep levels for trapping charges and a method for manufacturing the same.

【0004】[0004]

【課題を解決するための手段】上記の目的は、化合物半
導体基板内に少なくとも半導体素子が形成された半導体
装置において、前記化合物半導体基板の一部に少なくと
も原子状水素により形成された高抵抗層を有して成る半
導体装置により、達成される。この高抵抗層は、例えば
集積回路内の各素子間のアイソレイションに用いること
ができるし、また、導電層の抵抗を増加させることによ
り、抵抗素子中の負荷抵抗の抵抗値の制御に用いること
もできる。また、上記目的は、図1に示す様に高抵抗化
させる領域11の表面に原子状水素ビーム10を照射
し、原子状水素を表面から半導体内部に拡散させる工程
を有して成る半導体装置の製造方法によっても達成され
る。そして化合物半導体としては、III−V族化合物半
導体は勿論のことII−VI族化合物であってもよい。そ
して高抵抗化の程度は、原子状水素の照射量と基板温度
とを制御することにより、所定の抵抗値に容易に設定す
ることができる。また、化合物半導体基板表面上に原子
状水素を照射するに際しては、水素分子線を少なくとも
1600K以上に加熱して水素分子を水素原子に熱的に
解離したものを使用することが望ましい。
SUMMARY OF THE INVENTION In a semiconductor device in which at least a semiconductor element is formed in a compound semiconductor substrate, a high resistance layer formed of at least atomic hydrogen is formed in a part of the compound semiconductor substrate. This is achieved by a semiconductor device having. This high resistance layer can be used, for example, for isolation between each element in an integrated circuit, and can also be used for controlling the resistance value of the load resistance in the resistance element by increasing the resistance of the conductive layer. You can also Further, the above object is to provide a semiconductor device including a step of irradiating the surface of a region 11 for increasing resistance with an atomic hydrogen beam 10 as shown in FIG. 1 and diffusing the atomic hydrogen from the surface into the inside of the semiconductor. It is also achieved by the manufacturing method. The compound semiconductor may be a III-V group compound semiconductor or a II-VI group compound. The degree of resistance increase can be easily set to a predetermined resistance value by controlling the irradiation amount of atomic hydrogen and the substrate temperature. Further, when irradiating the surface of the compound semiconductor substrate with atomic hydrogen, it is desirable to use one in which the hydrogen molecule beam is heated to at least 1600 K or more to thermally dissociate the hydrogen molecule into hydrogen atoms.

【0005】[0005]

【作用】原子状の水素は非常に活性であるため、結晶中
の未結合手と結合してこれを終端し、或いは電荷を供給
する浅い準位や電荷を捕獲する深い準位を作る不純物と
結合してこれら点欠陥に起因する準位を不活性化する作
用がある。また、水素原子は原子半径が小さいので半導
体の格子間に侵入し易く、半導体内を拡散し易いと云う
性質がある。それにも拘わらず、半導体表面を水素雰囲
気中にさらすだけでは、水素分子が原子に解離する反応
速度が小さいので水素原子の半導体内部への拡散は非常
に起こりにくい。従って化合物半導体表面に水素分子を
供給するだけでは、半導体内の未結合手や不純物の作る
準位を不活性化して、欠陥準位のない良質な高抵抗層を
形成するに足る充分な量の水素原子を半導体内に導入す
ることができない。そこで何らかの手法を用いて予め原
子状水素を生成して、それを半導体表面に照射すれば、
表面から内部への拡散を律速している過程が省かれるの
で原子状水素の半導体内部への拡散が促進され、良質な
高抵抗層の形成が容易となる。この高抵抗層の抵抗値
は、原子状水素の照射量と基板温度とを制御することに
より容易に所定値に設定することができる。基板温度と
しては、室温以上で400℃より低い温度が好ましく、
実用的には200〜350℃がより好ましい温度であ
る。400℃以上では、原子状水素の拡散は速くなり特
定の領域に高密度に導入することが困難になる。また、
基板表面からの再脱離の割合も非常に大きくなるので、
高抵抗化を図る上では好ましくない。しかし、他の目
的、すなわち、好ましい条件下で高抵抗化した領域を部
分的に低抵抗化したい場合には、400℃以上の温度で
熱処理すれば元の抵抗値に回復させることも可能であ
る。
[Function] Since atomic hydrogen is very active, it may combine with dangling bonds in the crystal to terminate it, or as impurities that form shallow levels for supplying charges or deep levels for trapping charges. It has the effect of binding and inactivating the levels resulting from these point defects. Further, since the hydrogen atom has a small atomic radius, it has a property that it easily penetrates between the lattices of the semiconductor and easily diffuses in the semiconductor. Nevertheless, only by exposing the semiconductor surface to a hydrogen atmosphere, the reaction rate at which hydrogen molecules dissociate into atoms is small, so that diffusion of hydrogen atoms into the semiconductor is extremely unlikely to occur. Therefore, supplying only hydrogen molecules to the surface of the compound semiconductor inactivates the levels created by dangling bonds and impurities in the semiconductor, and is sufficient to form a high-quality high resistance layer with no defect levels. Hydrogen atoms cannot be introduced into the semiconductor. Therefore, if some kind of method is used to generate atomic hydrogen in advance and irradiate it on the semiconductor surface,
Since the process that controls the rate of diffusion from the surface to the inside is omitted, the diffusion of atomic hydrogen into the semiconductor is promoted, and the formation of a high-quality high resistance layer is facilitated. The resistance value of the high resistance layer can be easily set to a predetermined value by controlling the irradiation amount of atomic hydrogen and the substrate temperature. The substrate temperature is preferably room temperature or higher and lower than 400 ° C.,
Practically, 200 to 350 ° C is a more preferable temperature. At 400 ° C. or higher, the diffusion of atomic hydrogen becomes fast and it becomes difficult to introduce it at a high density in a specific region. Also,
Since the rate of re-desorption from the substrate surface also becomes very large,
It is not preferable in order to increase the resistance. However, for another purpose, that is, when it is desired to partially reduce the resistance of a region having a high resistance under preferable conditions, it is possible to recover the original resistance value by heat treatment at a temperature of 400 ° C. or higher. .

【0006】原子状水素を生成する方法としては、例え
ば以下のような方法がある。すなわち、水素分子を16
00〜2100K、もしくはそれ以上(でき得れば24
00K以上)に加熱して原子に解離する熱解離法、もし
くはマイクロ波(μ波)や高周波(rf波)、もしくは
グロー放電などを用いて水素プラズマを発生させ、プラ
ズマ中で生成される原子状水素を取り出すプラズマ法等
がある。プラズマ法では中性の原子状水素と共に、電子
や水素イオンといった荷電粒子も生成する。荷電粒子が
試料表面に照射されると表面の原子をスパッタして表面
を荒らしたり、或いは半導体内に荷電粒子が潜り込んで
格子を壊して欠陥準位を増大させたりする。従って、プ
ラズマ法を用いる場合、プラズマと試料表面との間にグ
リッド電極により遮蔽電場を設けて荷電粒子をプラズマ
内に閉じ込めるか、或いは磁場乃至は四重極場を設けて
荷電粒子を試料の置かれていない方向へ導き出すことが
望ましい。
As a method for producing atomic hydrogen, there are the following methods, for example. That is, 16 hydrogen molecules
00-2100K or higher (24 if possible
Hydrogen plasma is generated by using a thermal dissociation method in which the hydrogen is dissociated into atoms by heating to (00K or more), microwave (μ wave) or high frequency (rf wave), or glow discharge, and the atomic state generated in the plasma is generated. There is a plasma method for extracting hydrogen. In the plasma method, charged particles such as electrons and hydrogen ions are generated together with neutral atomic hydrogen. When the surface of the sample is irradiated with charged particles, the atoms on the surface are sputtered to roughen the surface, or charged particles penetrate into the semiconductor to break the lattice and increase the defect level. Therefore, when the plasma method is used, a shielded electric field is provided between the plasma and the sample surface by a grid electrode to confine the charged particles in the plasma, or a magnetic field or a quadrupole field is provided to place the charged particles on the sample. It is desirable to derive in a direction that is not overwhelmed.

【0007】[0007]

【実施例】以下、図面にしたがって本発明の一実施例を
具体的に説明する。 〈実施例1〉この例は、本発明を化合物半導体ヘテロ構
造バイポーラトランジスタ(Heterostructure Bipola
r Transistor:HBT)の負荷抵抗に応用した場合に
ついて説明する。図2は、AlGaAs/GaAs H
BTの抵抗素子の製造工程を示す断面図である。まず、
図2(a)に示すように、抵抗率約107Ωcmの半絶
縁性のGaAs基板20の上に、高抵抗のアンドープG
aAsバファー層21、その上に厚さ1500Å、電子
濃度1x1018cm-3、抗率2x10-3Ωcmのn+
GaAs層22、n型GaAs層23、p型GaAs層
24、n型AlGaAs層25、n+型GaAs層2
6、を順次エピタキシャル成長した後、エミッタ電極2
7を形成する。次いで図2(b)に示すように、エミッ
タ電極27をマスクにして不要なn+型GaAs層2
6、及びn型AlGaAs層25を順次除去した後、こ
のエミッタ電極27の側面にSiO2からなる絶縁側壁
28を形成し、この側壁28を鋏んでベース電極29を
形成する。最後に図2(c)に示すように、不要なp型
GaAs層24、n型GaAs層23を除去し、コレク
タ電極210、負荷抵抗電極211を形成し、次いでコ
レクタ電極210と負荷抵抗電極211との間のn+
GaAs層22の表面に原子状水素10を照射して高抵
抗領域212を形成する。原子状水素10の照射量を制
御して、これら二電極間(電極210−電極211)の
抵抗を任意の値に調節することによりHBTの抵抗素子
の主要部分が完成する。図3は、以上の製造工程で得ら
れた半導体装置の等価回路図を示したものであり、抵抗
素子Rは高抵抗領域212により実現されたものであ
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be specifically described below with reference to the drawings. <Example 1> In this example, the present invention is applied to a compound semiconductor heterostructure bipolar transistor (Heterostructure Bipolar).
The case of application to the load resistance of r Transistor (HBT) will be described. Figure 2 shows AlGaAs / GaAs H
It is sectional drawing which shows the manufacturing process of the resistance element of BT. First,
As shown in FIG. 2A, a high resistance undoped G layer is formed on a semi-insulating GaAs substrate 20 having a resistivity of about 10 7 Ωcm.
aAs buffer layer 21, on which n + type GaAs layer 22, n type GaAs layer 23, p type GaAs layer 24, n type AlGaAs layer having a thickness of 1500Å, an electron concentration of 1 × 10 18 cm -3 and a resistivity of 2 × 10 -3 Ωcm 25, n + type GaAs layer 2
6 is sequentially epitaxially grown, and then the emitter electrode 2
Form 7. Then, as shown in FIG. 2B, the unnecessary n + -type GaAs layer 2 is formed by using the emitter electrode 27 as a mask.
After the 6 and the n-type AlGaAs layer 25 are sequentially removed, an insulating side wall 28 made of SiO 2 is formed on the side surface of the emitter electrode 27, and the side wall 28 is scissored to form a base electrode 29. Finally, as shown in FIG. 2C, unnecessary p-type GaAs layer 24 and n-type GaAs layer 23 are removed to form collector electrode 210 and load resistance electrode 211, and then collector electrode 210 and load resistance electrode 211. Atomic hydrogen 10 is irradiated to the surface of the n + -type GaAs layer 22 between and to form the high resistance region 212. The main part of the resistance element of the HBT is completed by controlling the irradiation amount of the atomic hydrogen 10 and adjusting the resistance between these two electrodes (electrode 210-electrode 211) to an arbitrary value. FIG. 3 is an equivalent circuit diagram of the semiconductor device obtained by the above manufacturing process, and the resistance element R is realized by the high resistance region 212.

【0008】なお、原子状水素を高抵抗形成領域に照射
する場合の一例について以下に具体的に説明す。肉厚
0.1mmのタングステンチューブに3kVの高電圧を
印加して直近の陰極から100mAの電流を供給する電
子衝撃加熱により2800Kに加熱することができる。
加熱したタングステンチューブ内に水素ガスを通すこと
により供給した水素分子の60%が熱解離して原子状の
水素となり、水素原子の分圧は水素の全圧の75%に達
する。この条件で原子状水素ビームを発生させ、半導体
基板温度300℃、試料位置での原子状水素ビームの強
度を1x1014H−atoms(水素原子)/cm2
secに調節して原子状水素の照射を15分間行うと、
+型GaAs層22の表面から1000Åの深さまで
高抵抗層212が形成され、厚さ500Åのn+領域が
残った。このとき電極の長さが2μmであれば、コレク
タ電極210と負荷抵抗電極211との間の距離が5μ
mで1kΩの負荷抵抗が得られ、同じ幅を有する表面抵
抗80Ω/sq.のTaN薄膜を抵抗層に用いた場合に
比べ、1/5の大きさにすることができた。
An example of irradiating the high resistance forming region with atomic hydrogen will be specifically described below. A high voltage of 3 kV is applied to a tungsten tube having a wall thickness of 0.1 mm, and it can be heated to 2800 K by electron impact heating which supplies a current of 100 mA from the nearest cathode.
By passing hydrogen gas through a heated tungsten tube, 60% of the hydrogen molecules supplied are thermally dissociated into atomic hydrogen, and the partial pressure of hydrogen atoms reaches 75% of the total hydrogen pressure. An atomic hydrogen beam is generated under these conditions, the semiconductor substrate temperature is 300 ° C., and the intensity of the atomic hydrogen beam at the sample position is 1 × 10 14 H-atoms (hydrogen atoms) / cm 2 ·
When adjusted to sec and irradiated with atomic hydrogen for 15 minutes,
The high resistance layer 212 was formed from the surface of the n + type GaAs layer 22 to a depth of 1000 Å, leaving an n + region having a thickness of 500 Å. At this time, if the electrode length is 2 μm, the distance between the collector electrode 210 and the load resistance electrode 211 is 5 μm.
m, a load resistance of 1 kΩ is obtained, and a surface resistance having the same width is 80 Ω / sq. The size of the TaN thin film can be reduced to 1/5 as compared with the case where the TaN thin film is used for the resistance layer.

【0009】〈実施例2〉この例は、本発明をヘテロ構
造絶縁ゲート型電界効果トランジスタ(Dopedchannel
Heterostructure Insulated Gate Field Effect
Transistor;HIGFET)のアイソレイションに適
用した場合について説明する。図4は製造工程を示した
断面図であり、以下この図にしたがって説明する。ま
ず、図(a)に示すように、半絶縁性基板20の上にア
ンドープGaAsバファー層21、p型GaAs層4
0、n型GaAs層41、アンドープAlGaAs層4
2を順次エピタキシャルに成長した後、周知の形成工程
によりWSiからなるゲート電極43、43’を形成
し、これらゲート電極43、43’の側面にSiO2
らなる側壁44を形成する。
<Second Embodiment> In this embodiment, the present invention is applied to a heterostructure insulated gate field effect transistor (Doped channel).
Heterostructure Insulated Gate Field Effect
Transistor; HIGFET) isolation will be described. FIG. 4 is a cross-sectional view showing the manufacturing process, which will be described below with reference to this drawing. First, as shown in FIG. 3A, an undoped GaAs buffer layer 21 and a p-type GaAs layer 4 are formed on a semi-insulating substrate 20.
0, n-type GaAs layer 41, undoped AlGaAs layer 4
After the epitaxial growth of 2 in sequence, gate electrodes 43 and 43 'made of WSi are formed by a well-known formation process, and side walls 44 made of SiO 2 are formed on the side surfaces of these gate electrodes 43, 43'.

【0010】次に図4(b)に示すように、これらゲー
ト電極43、43’及び側壁44をマスクにして不要な
アンドープAlGaAs層42及びn型GaAs層41
を除去する。オーミック電極を形成する領域にMOCV
D法によりn++型GaAs層45を選択成長し、その上
にAuGeからなるソース電極46、46’、及びドレ
イン電極47、47’の各オーミック電極を形成し、同
一基板上に隣接してトランジスタTrs1およびTrs
2を実現する。
Next, as shown in FIG. 4B, unnecessary undoped AlGaAs layer 42 and n-type GaAs layer 41 are formed by using the gate electrodes 43 and 43 'and the side wall 44 as a mask.
To remove. MOCV in the region where the ohmic electrode is formed
An n ++ type GaAs layer 45 is selectively grown by the D method, and ohmic electrodes of source electrodes 46 and 46 'and drain electrodes 47 and 47' made of AuGe are formed on the n + + type GaAs layer 45, and they are adjacent to each other on the same substrate. Transistors Trs1 and Trs
Achieve 2.

【0011】次いで図4(c)に示すように、これら隣
接するトランジスタTrs1およびTrs2間のアイソ
レイション領域に原子状水素を下記の方法で導入し、高
抵抗化して素子間分離を行う。すなわち、空洞共振器内
に水素ガスを導入し、周波数2450MHzのμ波を用
いて水素プラズマを発生させ、原子状水素10を生成す
ることができる。μ波の出力が50Wの時、90%以上
の水素分子が解離してその多くは原子状水素になる。プ
ラズマ中の電子及び水素イオンは空洞共振器と試料との
間に置かれた数枚のグリッド電極に電圧を印加して電場
勾配を設けることによりプラズマ中に閉じ込めることが
できる。半導体基板温度300℃、試料位置での原子状
水素ビームのフラックス強度を1x1015H−atom
s/cm2・secにして10分間、素子間のp型Ga
As層42に原子状水素10を照射して高抵抗領域48
を形成して素子間のアイソレイションが完了する。
Next, as shown in FIG. 4 (c), atomic hydrogen is introduced into the isolation region between the adjacent transistors Trs1 and Trs2 by the following method to increase the resistance and isolate the elements. That is, hydrogen gas can be introduced into the cavity resonator, and hydrogen plasma can be generated by using μ waves having a frequency of 2450 MHz to generate atomic hydrogen 10. When the output of μ wave is 50 W, 90% or more of hydrogen molecules are dissociated and most of them become atomic hydrogen. Electrons and hydrogen ions in the plasma can be confined in the plasma by applying a voltage to several grid electrodes placed between the cavity resonator and the sample to provide an electric field gradient. The semiconductor substrate temperature is 300 ° C., and the flux intensity of the atomic hydrogen beam at the sample position is 1 × 10 15 H-atom.
s / cm 2 · sec for 10 minutes, p-type Ga between elements
By irradiating the As layer 42 with atomic hydrogen 10, the high resistance region 48 is exposed.
To complete the isolation between the elements.

【0012】本実施例では、水素プラズマを空洞共振器
内でμ波を用いて発生させたが、放電管を用いてrf波
によりプラズマを発生させてもよく、或いはまた、グロ
ー放電やコロナ放電などを用いてもよいことは云うまで
もない。また、電子やイオンをグリッドバイアスで閉じ
込めたが、プラズマと試料との間に四重極場を設けた
り、或いは磁場を印加したりして荷電粒子が試料表面に
到達しえないようにしてもよい。
In the present embodiment, the hydrogen plasma is generated by using the μ wave in the cavity resonator, but the plasma may be generated by the rf wave by using the discharge tube, or the glow discharge or the corona discharge may be generated. It goes without saying that, etc. may be used. Although electrons and ions are confined by a grid bias, a quadrupole field may be provided between the plasma and the sample, or a magnetic field may be applied to prevent charged particles from reaching the sample surface. Good.

【0013】本実施例のアイソレイションでは、素子間
に溝(リセス)を掘る必要がなく、段差が殆ど無いので
配線が容易になる。また、図5に示すようにサイドゲー
ト効果を調べるために、まず第一の素子Trs1のソー
ス電極46に−1V、ゲート電極43に−0.8Vのバ
イアス電位を印加してドレイン電極47をグランド電位
にバイアスし、更に隣接する第二の素子Trs2のソー
ス電極46’の電位を0Vから−5Vまで変化させた。
図6は、素子間距離が15μmの場合の、第一のドレイ
ン電極47に流れるドレイン電流Idの第二のソース電
極46’に印加されるサイドゲート電圧vsgに対する依
存性を示したものであり、縦軸はId、横軸はvsgを示
している。但し縦軸はvsg=0Vの時のIdの値で規格
化している。そして、図中の60は本実施例の、61は
比較例となる従来構造の特性をそれぞれ示している。従
来構造においてはドレイン電極47に流れるドレイン電
流Idは、第2のソース電極46’に印加されるサイド
ゲート電圧vsgに大きく依存し、vsg=−2Vのときに
規格化Idは0.9に減少した。すなわち、サイドゲー
ト耐圧Bvsgは−2Vであった。一方、本実施例におい
てはサイドゲート耐圧Bvsgは−約5Vと2倍以上に向
上した。
In the isolation of this embodiment, it is not necessary to form a groove (recess) between the elements, and there is almost no step, so that the wiring becomes easy. Further, as shown in FIG. 5, in order to investigate the side gate effect, first, a bias potential of -1 V is applied to the source electrode 46 of the first element Trs1 and a bias potential of -0.8 V is applied to the gate electrode 43, and the drain electrode 47 is grounded. The potential of the source electrode 46 'of the second element Trs2 adjacent to the second element Trs2 was changed from 0V to -5V.
FIG. 6 shows the dependence of the drain current I d flowing through the first drain electrode 47 on the side gate voltage v sg applied to the second source electrode 46 ′ when the element distance is 15 μm. The vertical axis represents I d and the horizontal axis represents v sg . However, the vertical axis is normalized by the value of I d when v sg = 0V. Further, in the figure, 60 indicates the characteristics of the present embodiment, and 61 indicates the characteristics of the conventional structure as a comparative example. In the conventional structure, the drain current I d flowing through the drain electrode 47 largely depends on the side gate voltage v sg applied to the second source electrode 46 ′, and the normalized I d is 0 when v sg = −2V. It decreased to .9. That is, the side gate breakdown voltage Bv sg was −2V. On the other hand, in this example, the side gate breakdown voltage Bv sg was doubled or more to about −5V.

【0014】本実施例では、HIGFETの素子間のア
イソレイションに用いたが、他の電界効果トランジス
タ、例えばショットキーゲート型電界効果トランジスタ
(Metal Semiconductor FET; MESFET)、
MIS型電界効果トランジスタ(Metal Insulator S
emiconductor FET;MISFET)、或いは高電子
移動度トランジスタ(High Electron Mobility Tra
nsistor;HEMT)等の素子間アイソレイションに用
いてもよいことは云うまでもない。なお、図4に於い
て、アンド−プGaAsバファ−層21を予め原子状水
素を用いて高抵抗化しておけば一層効果的である。
In this embodiment, the HIGFET is used for isolation between elements, but other field effect transistors such as Schottky gate type field effect transistors (Metal Semiconductor FET; MESFET),
MIS field effect transistor (Metal Insulator S)
emiconductor FET (MISFET) or high electron mobility transistor (High Electron Mobility Tra)
Needless to say, it may be used for isolation between elements such as nsistor (HEMT). Further, in FIG. 4, it is more effective if the AND-type GaAs buffer layer 21 is made high in resistance by using atomic hydrogen in advance.

【0015】〈実施例3〉この例は、HBTのベース/
コレクタ接合容量(CBC)を選択的に減らす手法とし
て適用した場合について説明する。図7は、AlGaA
s/GaAs HBTの製造工程を示す断面図である。
まず、図7(a)に示すように、半絶縁性GaAs基板
20の上にアンドープのGaAsバファー層21、n+
型GaAs層22、n型GaAs層23、p型GaAs
層24、n型AlGaAs層25、n+型GaAs層2
6、を順次エピタキシャル成長した後、エミッタ電極2
7を形成する。エミッタ電極27をマスクにして不要な
+型GaAs層26及びn型AlGaAs層25を除
去した後、原子状水素ビーム10を照射して、基板表面
からn型GaAs層23の深さまで高抵抗化し、高抵抗
領域70、71を形成する。次に図7(b)に示すよう
に、400℃に昇温した真空加熱炉に導入し、高抵抗領
域70の導電性のみを元のp型GaAs層24に回復さ
せた後、エミッタ電極27の側面にSiO2からなる絶
縁側壁28を形成し、この側壁28を鋏んでベース電極
29を形成する。最後に図7(c)に示すように、不要
なp型GaAs層24および高抵抗化したGaAs層7
1を除去し、コレクタ電極210を形成することにより
HBTの主要部分が完成する。
<Embodiment 3> This example is based on HBT base /
A case where the method is applied as a method of selectively reducing the collector junction capacitance (CBC) will be described. FIG. 7 shows AlGaA.
It is sectional drawing which shows the manufacturing process of s / GaAs HBT.
First, as shown in FIG. 7A, an undoped GaAs buffer layer 21, n + , is formed on a semi-insulating GaAs substrate 20.
Type GaAs layer 22, n type GaAs layer 23, p type GaAs
Layer 24, n-type AlGaAs layer 25, n + -type GaAs layer 2
6 is sequentially epitaxially grown, and then the emitter electrode 2
Form 7. After removing the unnecessary n + type GaAs layer 26 and the n type AlGaAs layer 25 using the emitter electrode 27 as a mask, the atomic hydrogen beam 10 is irradiated to increase the resistance from the substrate surface to the depth of the n type GaAs layer 23. The high resistance regions 70 and 71 are formed. Next, as shown in FIG. 7B, after introducing into a vacuum heating furnace heated to 400 ° C. to restore only the conductivity of the high resistance region 70 to the original p-type GaAs layer 24, the emitter electrode 27 An insulating side wall 28 made of SiO 2 is formed on the side surface of, and the side wall 28 is scissored to form a base electrode 29. Finally, as shown in FIG. 7C, the unnecessary p-type GaAs layer 24 and the GaAs layer 7 having a high resistance are formed.
By removing 1 and forming the collector electrode 210, the main part of the HBT is completed.

【0016】図7(a)の工程にてp型GaAs層24
の厚さが700Å、n型GaAs層23の厚さが300
0Åの場合、基板温度350℃、試料位置での原子状水
素ビームのフラックス強度を1x1015H−atoms
/cm2・secに制御して10分間原子状水素を照射
することにより両層を高抵抗化することができた。ま
た、図7(b)の工程にてp型GaAs層24中での原
子状水素の拡散速度は、n型GaAs層23内での拡散
速度よりも速いので、15秒間400℃に加熱すること
により高抵抗化した厚さ700ÅのGaAs層70は正
孔濃度が回復し、元のp型導電層24に戻るが、高抵抗
化したGaAs層71は高抵抗化したままの状態に保持
することができた。
In the process of FIG. 7A, the p-type GaAs layer 24 is formed.
Has a thickness of 700Å and the n-type GaAs layer 23 has a thickness of 300.
In the case of 0Å, the substrate temperature is 350 ° C. and the flux intensity of the atomic hydrogen beam at the sample position is 1 × 10 15 H-atoms.
Both layers could be made to have a high resistance by irradiating with atomic hydrogen for 10 minutes while controlling to / cm 2 · sec. Further, since the diffusion rate of atomic hydrogen in the p-type GaAs layer 24 is higher than that in the n-type GaAs layer 23 in the step of FIG. 7B, heating at 400 ° C. for 15 seconds. The hole concentration of the GaAs layer 70 having a high resistance of 700 Å recovered by the above is restored and returns to the original p-type conductive layer 24. However, the GaAs layer 71 having a high resistance is kept in the high resistance state. I was able to.

【0017】本実施例の結果、原子状水素を照射しない
場合に較べ、コレクタ層であるn型GaAs層23の電
子濃度を一定にした場合でもCBCを約3分の1に低減す
ることができ、その結果、最大発信周波数fmaxを約
1.7倍にすることができた。また同時に、CBCを増や
すことなくコレクタ層であるn型GaAs層23の電子
濃度を大幅に増加することができた。その結果、コレク
タ空乏層幅を十分に小さくすることも可能となり、CBC
を増やすことなくコレクタ走行時間(τC)をベース走
行時間(τB)に較べ十分に小さくすることができた。
BCとτCが共に改善された結果、従来構造に比べて電
流利得遮断周波数fTは約2倍に向上し、最大発信周波
数fmaxも約2.4倍に改善することができた。
As a result of this embodiment, compared with the case where atomic hydrogen is not irradiated, C BC can be reduced to about 1/3 even when the electron concentration of the n-type GaAs layer 23 which is the collector layer is kept constant. As a result, the maximum transmission frequency f max could be increased by about 1.7 times. At the same time, the electron concentration of the n-type GaAs layer 23, which is the collector layer, could be significantly increased without increasing C BC . As a result, the collector depletion layer width can be made sufficiently small, and C BC
The collector running time (τ C ) was able to be made sufficiently smaller than the base running time (τ B ) without increasing.
As a result of improving both C BC and τ C, the current gain cutoff frequency f T was improved about twice and the maximum oscillation frequency f max was also improved about 2.4 times compared with the conventional structure.

【0018】〈実施例4〉本発明は、光電気集積回路
(OEIC)に適用することも可能であり、その一実施
例としてPIN構造の受光ダイオード(Photo−Diod
e;PD)を有する光電気変換装置の負荷抵抗に用いた
場合について示す。図8は、本実施例に係る光電気変換
装置の構造を示した断面図である。以下、この図にした
がって説明すると、電極83を通して入射した光84が
PD内、主としてアンドープのi型GaAs層81内で
電子正孔対を生成すると、PDには逆バイアスが印加さ
れているので、電子はn型GaAs層82側に、正孔は
p型GaAs層80側に引き寄せられて逆方向に光電流
が流れる。このように光入射で生成した電子正孔対を光
電流として取り出すことで光入力を電気出力に変換する
ことができる。光電流を電圧の信号として取り出すため
にはPDとグランド電位との間に抵抗素子を設け、図9
に示す等価回路を完成する必要がある。本実施例では、
電極85と電極86との間のp型GaAs層80の領域
に、実施例1の場合と同様にして原子状水素を照射して
高抵抗領域87を形成した。その結果、図9に示すよう
な抵抗Rを有する等価回路の光電気変換装置が容易に完
成する。本実施例によれば抵抗層87の面積を従来構造
の素子に比べ5分の1に縮小することができた。電極8
3は透明、或いは半透明電極でもよく、或いは光を透過
させる窓を開けた不透明電極でもよい。また、i型Ga
As層81に原子状水素を照射することにより、このi
型GaAs層81をより高品質化することができ、光電
気変換効率を2割向上させることができた。
<Embodiment 4> The present invention can also be applied to an optoelectronic integrated circuit (OEIC), and as one embodiment thereof, a light receiving diode (Photo-Diod) of a PIN structure is used.
e; PD) is used as a load resistance of a photoelectric conversion device. FIG. 8 is a sectional view showing the structure of the photoelectric conversion device according to the present embodiment. In the following description with reference to this figure, when the light 84 incident through the electrode 83 generates electron-hole pairs in the PD, mainly in the undoped i-type GaAs layer 81, the PD is reverse-biased. Electrons are attracted to the n-type GaAs layer 82 side and holes are attracted to the p-type GaAs layer 80 side, and photocurrent flows in the opposite direction. Thus, the light input can be converted into an electric output by taking out the electron-hole pairs generated by the light incidence as a photocurrent. In order to take out the photocurrent as a voltage signal, a resistance element is provided between the PD and the ground potential.
It is necessary to complete the equivalent circuit shown in. In this embodiment,
A high resistance region 87 was formed by irradiating the region of the p-type GaAs layer 80 between the electrodes 85 and 86 with atomic hydrogen in the same manner as in the first embodiment. As a result, the photoelectric conversion device of the equivalent circuit having the resistance R as shown in FIG. 9 is easily completed. According to this example, the area of the resistance layer 87 could be reduced to one fifth of that of the element having the conventional structure. Electrode 8
Reference numeral 3 may be a transparent or semi-transparent electrode, or an opaque electrode having a window for transmitting light. In addition, i-type Ga
By irradiating the As layer 81 with atomic hydrogen, this i
The type GaAs layer 81 can be made higher in quality, and the photoelectric conversion efficiency can be improved by 20%.

【0019】なお、原子状水素を照射しない場合、光電
気変換回路には抵抗が負荷されず、PDの出力信号はグ
ランド電位に固定されるので光電気変換回路をアレイ状
に並べ、一部のPDのp型導電層81のみを同様の方法
で選択的に高抵抗化すれば不揮発性メモリとしても利用
できる。400℃に加熱することにより容易に低抵抗化
するので書き換えも容易である。図8ではPIN構造の
PDを含む光電気変換装置の場合について説明したが、
アバランシェ型の受光ダイオード(APD)や、ショッ
トキ接合型の受光ダイオードを含む光電気変換装置に利
用することも可能である。
When atomic hydrogen is not irradiated, no resistance is loaded on the photoelectric conversion circuit, and the output signal of the PD is fixed at the ground potential. If only the p-type conductive layer 81 of the PD is selectively made high in resistance by the same method, it can be used as a nonvolatile memory. Rewriting is easy because the resistance is easily lowered by heating to 400 ° C. In FIG. 8, the case of the photoelectric conversion device including the PD having the PIN structure has been described.
It can also be used for an avalanche type light receiving diode (APD) and a photoelectric conversion device including a Schottky junction type light receiving diode.

【0020】以上の実施例では、化合物半導体としてG
aAsを代表例として説明したが、本発明はその他の化
合物半導体、例えばInP、InGaAs、InGaA
sP、GaP等のIII−V族化合物半導体、更には周知
のII−VI族化合物半導体を用いた場合についても同様
である。
In the above embodiments, G is used as the compound semiconductor.
Although aAs has been described as a typical example, the present invention is applicable to other compound semiconductors such as InP, InGaAs, and InGaA.
The same applies to the case where a III-V group compound semiconductor such as sP or GaP, or a well-known II-VI group compound semiconductor is used.

【0021】[0021]

【発明の効果】以上詳述したように本発明により、所期
の目的を達成することができた。すなわち、半導体基板
の所望領域に原子状水素を照射して水素を導入すること
により高抵抗化でき、しかも照射量を制御することによ
り抵抗値を所望値に設定することが容易である。これを
アイソレイションに用いれば、サイドゲート耐圧を向上
させることができ、且つリセスが不要となるためにリセ
スに伴う段差が無くなり配線が容易になった。また、H
BTのベース/コレクタ接合容量の低減に用いれば電流
利得遮断周波数、最大発振周波数を共に向上することが
でき、高周波特性を大幅に改善することができた。抵抗
素子の負荷抵抗に用いるた場合、負荷抵抗の面積を縮小
することができた。
As described above in detail, according to the present invention, the intended purpose can be achieved. That is, it is possible to increase the resistance by irradiating atomic hydrogen onto a desired region of the semiconductor substrate to introduce hydrogen, and it is easy to set the resistance value to a desired value by controlling the irradiation amount. If this is used for isolation, the side gate breakdown voltage can be improved, and since the recess is not required, the step due to the recess is eliminated and wiring is facilitated. Also, H
When used for reducing the base / collector junction capacitance of BT, both the current gain cutoff frequency and the maximum oscillation frequency could be improved, and the high frequency characteristics could be greatly improved. When used as the load resistance of the resistance element, the area of the load resistance could be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の高抵抗層を実現するための原理説明用
断面図。
FIG. 1 is a sectional view for explaining the principle for realizing a high resistance layer of the present invention.

【図2】本発明の一実施例となる半導体装置の製造工程
を示す断面図。
FIG. 2 is a cross-sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

【図3】同じく、半導体装置の等価回路図。FIG. 3 is likewise an equivalent circuit diagram of the semiconductor device.

【図4】同じく、他の実施例となる半導体装置の製造工
程を示す断面図。
FIG. 4 is a sectional view showing a manufacturing process of a semiconductor device according to another embodiment of the present invention.

【図5】同じく、半導体装置のサイドゲート効果の測定
方法を示す回路図。
FIG. 5 is a circuit diagram showing a method of measuring a side gate effect of a semiconductor device, similarly.

【図6】同じく、ドレイン電流のサイドゲート電圧依存
性を示す特性図。
FIG. 6 is a characteristic diagram showing the dependency of drain current on the side gate voltage.

【図7】同じく、他の実施例となる半導体装置の製造工
程を示す断面図。
FIG. 7 is a sectional view showing a manufacturing process of a semiconductor device according to another embodiment of the present invention.

【図8】同じく、さらに異なる他の実施例となる光電気
変換装置の断面図。
FIG. 8 is a sectional view of a photoelectric conversion device according to still another embodiment of the present invention.

【図9】同じく、光電気変換装置の等価回路図。FIG. 9 is an equivalent circuit diagram of the photoelectric conversion device.

【符号の説明】[Explanation of symbols]

10…照射される原子状水素ビーム、 11…高抵抗化
された化合物半導体、12…化合物半導体基板、
20…半絶縁性GaAs基板 21…アンドープGaAsバッファ層、22…n+型G
aAs層、23…n型GaAs層、 24
…p型GaAs層、25…n型AlGaAs層、
26…n+型GaAs層、27…エミッタ電極、
28…絶縁側壁、29…ベース電極、
210…コレクタ電極、211…負荷
抵抗電極、 212…高抵抗領域、40…
p型GaAs層、 41…n型GaAs
層、42…アンドープAlGaAs層、 43、4
3’…ゲート電極、44…絶縁側壁、
45…n++型GaAs層、46、46’…ドレイン
電極、 47、47’…ソース電極、48…高抵
抗領域、 60…本発明の特性曲線、
61…比較例(従来構造)の特性曲線、70…p型Ga
As層の原子状水素により高抵抗化された領域、71…
n型GaAs層の原子状水素により高抵抗化された領
域、80…p型GaAs層、 81…アン
ドープi型GaAs層、82…n型GaAs層、
83…電極、84…入射光、
85…電極、86…電極、
87…高抵抗領域。
10 ... Irradiated atomic hydrogen beam, 11 ... Compound semiconductor with high resistance, 12 ... Compound semiconductor substrate,
20 ... Semi-insulating GaAs substrate 21 ... Undoped GaAs buffer layer, 22 ... N + type G
aAs layer, 23 ... N-type GaAs layer, 24
... p-type GaAs layer, 25 ... n-type AlGaAs layer,
26 ... N + type GaAs layer, 27 ... Emitter electrode,
28 ... Insulating side wall, 29 ... Base electrode,
210 ... Collector electrode, 211 ... Load resistance electrode, 212 ... High resistance region, 40 ...
p-type GaAs layer, 41 ... n-type GaAs
Layer, 42 ... Undoped AlGaAs layer, 43, 4
3 '... Gate electrode, 44 ... Insulating side wall,
45 ... N ++ type GaAs layer, 46, 46 '... Drain electrode, 47, 47' ... Source electrode, 48 ... High resistance region, 60 ... Characteristic curve of the present invention,
61 ... Characteristic curve of comparative example (conventional structure), 70 ... p-type Ga
A region of the As layer having a high resistance due to atomic hydrogen, 71 ...
A region of the n-type GaAs layer having a high resistance due to atomic hydrogen, 80 ... P-type GaAs layer, 81 ... Undoped i-type GaAs layer, 82 ... N-type GaAs layer,
83 ... Electrode, 84 ... Incident light,
85 ... Electrode, 86 ... Electrode,
87 ... High resistance region.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/265 C 9171−4M 29/80 E (72)発明者 ▲高▼谷 信一郎 東京都国分寺市東恋ケ窪1丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 重田 淳二 東京都国分寺市東恋ケ窪1丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 渕上 伸隆 東京都小平市上水本町5丁目20番1号 日 立超エル・エス・アイ・エンジニアリング 株式会社内─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Reference number within the agency FI Technical indication location H01L 21/265 C 9171-4M 29/80 E (72) Inventor ▲ Taka ▼ Shinichiro Tokyo Kokubunji 1-280, Higashi-Koigakubo, Hitachi, Ltd., Central Research Laboratory, Hitachi, Ltd. (72) Inventor, Junji Shigeta, 1-280, Higashi-Koikeku, Tokyo, Kokubunji, Ltd., Central Research Laboratory, Hitachi, Ltd. (72) Nobutaka Fuchigami, Kamimizumoto, Kodaira, Tokyo 5-20-1 Hitate Cho LLS Engineering Co., Ltd.

Claims (11)

【特許請求の範囲】[Claims] 【請求項1】化合物半導体基板内に少なくとも半導体素
子が形成された半導体装置において、前記化合物半導体
基板の一部に少なくとも原子状水素により形成された高
抵抗層を有して成る半導体装置。
1. A semiconductor device in which at least a semiconductor element is formed in a compound semiconductor substrate, wherein the compound semiconductor substrate has a high resistance layer formed of at least atomic hydrogen in a part thereof.
【請求項2】化合物半導体基板内に複数個の半導体素子
が形成され、これら各素子間を上記高抵抗層で絶縁分離
して成る請求項1記載の半導体装置。
2. A semiconductor device according to claim 1, wherein a plurality of semiconductor elements are formed in the compound semiconductor substrate, and the elements are insulated and separated by the high resistance layer.
【請求項3】化合物半導体基板内に形成された抵抗素子
を上記高抵抗層で構成して成る請求項1記載の半導体装
置。
3. A semiconductor device according to claim 1, wherein a resistance element formed in a compound semiconductor substrate is formed of the high resistance layer.
【請求項4】化合物半導体基板内に集積回路が形成され
て成る請求項1乃至3何れか記載の半導体装置。
4. The semiconductor device according to claim 1, wherein an integrated circuit is formed in a compound semiconductor substrate.
【請求項5】化合物半導体基板をIII−V族化合物半導
体で構成して成る請求項1乃至4何れか記載の半導体装
置。
5. The semiconductor device according to claim 1, wherein the compound semiconductor substrate is composed of a III-V group compound semiconductor.
【請求項6】化合物半導体基板表面上に原子状水素を照
射することにより高抵抗層を形成する工程を有して成る
半導体装置の製造方法。
6. A method of manufacturing a semiconductor device, comprising a step of forming a high resistance layer by irradiating the surface of a compound semiconductor substrate with atomic hydrogen.
【請求項7】上記原子状水素の照射量と基板温度とを制
御して上記高抵抗層の抵抗値を所定値に制御する工程と
して成る請求項6記載の半導体装置の製造方法。
7. The method of manufacturing a semiconductor device according to claim 6, which is a step of controlling the irradiation amount of the atomic hydrogen and the substrate temperature to control the resistance value of the high resistance layer to a predetermined value.
【請求項8】上記化合物半導体基板を400℃より低い
温度域に保持した状態で上記原子状水素を基板上に照射
する工程として成る請求項6記載の半導体装置の製造方
法。
8. A method of manufacturing a semiconductor device according to claim 6, which comprises the step of irradiating the substrate with the atomic hydrogen while the compound semiconductor substrate is kept in a temperature range lower than 400 ° C.
【請求項9】上記化合物半導体基板を200〜350℃
の温度域に保持した状態で上記原子状水素を基板上に照
射する工程として成る請求項6記載の半導体装置の製造
方法。
9. The compound semiconductor substrate at 200 to 350 ° C.
7. The method of manufacturing a semiconductor device according to claim 6, which comprises a step of irradiating the substrate with the atomic hydrogen in a state of being kept in the temperature range.
【請求項10】化合物半導体基板表面上に原子状水素を
照射する工程を、予め水素分子線を少なくとも1600
K以上に加熱して水素分子を水素原子に熱的に解離した
ものを照射する工程として成る請求項6乃至9何れか記
載の半導体装置の製造方法。
10. The step of irradiating the surface of a compound semiconductor substrate with atomic hydrogen is performed in advance with at least 1600 hydrogen molecular beams.
10. The method for manufacturing a semiconductor device according to claim 6, which comprises a step of irradiating a material obtained by thermally dissociating hydrogen molecules into hydrogen atoms by heating to K or more.
【請求項11】空洞共振器、もしくは放電管内に水素ガ
スを導入し、この水素ガスでマイクロ波、高周波もしく
はグロー放電により水素プラズマを発生させた後、少な
くとも電子及び水素イオンを含む荷電粒子を電場、磁場
もしくは四重極場により、空洞共振器、もしくは放電管
内に封じ込め、もしくは特定方向に除外することにより
形成した原子状水素のみを取り出して半導体基板上に照
射する工程を有して成る請求項6乃至9何れか記載の半
導体装置の製造方法。
11. Hydrogen gas is introduced into a cavity resonator or a discharge tube, and hydrogen plasma is generated by microwave, high frequency or glow discharge with the hydrogen gas, and then charged particles containing at least electrons and hydrogen ions are subjected to an electric field. The method comprises a step of irradiating a semiconductor substrate with only the atomic hydrogen formed by confining it in a cavity resonator or a discharge tube by a magnetic field or quadrupole field or excluding it in a specific direction. 10. The method for manufacturing a semiconductor device according to any one of 6 to 9.
JP3330994A 1994-03-03 1994-03-03 Semiconductor device and its manufacture Pending JPH07245338A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3330994A JPH07245338A (en) 1994-03-03 1994-03-03 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3330994A JPH07245338A (en) 1994-03-03 1994-03-03 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH07245338A true JPH07245338A (en) 1995-09-19

Family

ID=12382966

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3330994A Pending JPH07245338A (en) 1994-03-03 1994-03-03 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPH07245338A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014063877A (en) * 2012-09-21 2014-04-10 Fujitsu Ltd Resistance variable memory and driving method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014063877A (en) * 2012-09-21 2014-04-10 Fujitsu Ltd Resistance variable memory and driving method thereof

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