JPH07245298A - Manufacture of semiconductor device and semiconductor processing equipment - Google Patents

Abstract

PURPOSE:To minimize the uneven distribution of temperature within the surface of a wafer to be heated, by inserting the wafer into a furnace at its insertion end, subjecting it to a first processing in a region at a specified temperature, transferring it to a high temperature region, subjecting it to a second processing there, and returning it to the specified temperature region. CONSTITUTION:A wafer 2 is placed on a wafer holder 3, and a wafer holder elevating system 11 is moved up to its upper end. A supporting table 7 is pushed against the lower end of quartz reaction tube 4, and the wafer is sealed in the resultant region at a temperature of 700 deg.C. Then a thin film is formed thereon. A wafer moving magnet 9 is driven to move the wafer up to a position at 850 deg.C, and the wafer is held there for 15-30 minutes for annealing. The wafer moving magnet 9 is driven again to move the wafer down to the position at 700 deg.C. This minimizes the uneven distribution of temperature within the surface of a wafer to be heated, and makes it possible to continuously perform thin film formation and annealing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing method and a semiconductor manufacturing apparatus, and more particularly to a technique for enabling rapid thermal processing using an electric furnace.

[0002]

2. Description of the Related Art With the progress of semiconductor technology in recent years, various heat treatment techniques have been developed. The manufacture of VLSI requires oxidation, diffusion, CVD and other heat treatments.

As a heat treatment furnace for these requirements,
Hot wall type electric furnaces called horizontal furnaces and vertical furnaces have been used.

On the other hand, with the miniaturization of the element size, it has been required to form a shallow junction and suppress the redistribution of impurities, and various lamp annealings are adopted from the viewpoint of reducing the heat treatment temperature and the heat treatment time. Is coming.

The former is capable of batch processing and is excellent in temperature stability, but has difficulty in temperature control. The latter is a single-wafer treatment, and has the merit of being able to control the process temperature, and has recently attracted attention.

Speaking of 64M-DRAM, 0.3
Since it becomes a device with a pattern rule of 5μ, a CVD oxide film as an interlayer insulating film and a B-PSG for planarization
The heating temperature for forming the reflow film such as a film and the reflow process temperature is very important.

That is, in a transistor manufactured by the conventional process, when a heat quantity of, for example, 70 to 200 minutes or more is applied at 850 ° C. for a long time, the shape of the source / drain changes in proportion to the quantity of heat applied, and ion implantation is performed. If the impurity dose amount is large, the characteristics of the transistor are significantly impaired. Therefore, if the implantation amount of the source / drain is reduced, the resistance of the source / drain and the contact resistance of the electrode output are increased, and the transistor cannot obtain desired characteristics.

In this case, 16M-DRAM (0.6-
In the case of a CVD oxide film growth using monosilane, which can be used in a transistor of 0.4 μ rule), it is usually formed at a high temperature and a long time of 800 to 850 ° C. for 60 to 120 minutes. Get tougher.

In the 64M process, a process of forming a B-PSG film continuously on a polysilicon layer covered with a CVD oxide film is often used. The B-PSG film here is used as a flattening film. CVD of polysilicon layer
Covering with an oxide film is to prevent boron and phosphorus in the B-PSG film from diffusing into polysilicon, and for that purpose, about 300 to 500 angstroms is necessary.

Further, when aluminum wiring is formed on the B-PSG film, C containing no impurities after reflow is used.
It is necessary to form the VD oxide film as a protective film. In addition, low-temperature treatment is essential in order not to change the shape of the source / drain. Therefore, B-PS
Although methods such as adding oxidized Ge to G have been taken, addition of a large amount of various substances deteriorates the film quality. Therefore, at present, the B-PSG film is considered to be the best film.

[0011]

As described above, the lamp anneal is particularly suitable for manufacturing a device having a shallow junction, but the temperature distribution in the wafer surface is not as uniform as an electric furnace. As a result, thermal strain is generated and slip lines are generated from the peripheral portion of the wafer.

Experimentally, lamp annealing seems to have been quite successful for 6-inch wafers, but when a large amount of experiments at the mass production level are performed, the occurrence of slip lines is unavoidable. In order to use it, the heating rate must be reduced to a considerable extent.

Moreover, 8 required from 16M-DRAM
For inch wafers, rapid thermal annealing becomes more difficult, and the current scale-up cannot be used for actual mass production.

An attempt to carry out this rapid thermal annealing in a hot wall type electric furnace using a silicon carbide reaction tube has also been reported (US Vacuum Science and Technology J.
VAC. SCI. TECHNOL. B, Volume 8 Issue 6 199
0 / December / December). However, this furnace is merely a furnace for annealing.

In view of this problem, the present invention provides a method capable of controlling the in-plane temperature distribution of a wafer heated during rapid thermal annealing of a large diameter wafer of 8 inches or more to a minimum. It is an object of the present invention to provide a manufacturing method that is capable of realizing a clean process that is aimed at and compatible with a semiconductor process. It is another object of the present invention to provide a semiconductor manufacturing apparatus and a manufacturing method that can achieve this object and generate few particles.

[0016]

In order to achieve the above object, the present invention firstly provides a predetermined temperature region of a constant length in the depth direction from a wafer insertion end and a constant length higher than the predetermined temperature. From the insertion end of the furnace equipped with a high temperature region, the wafer is inserted, the first process is performed in the predetermined temperature region, then the wafer is moved to the high temperature region, the second process is performed, and the predetermined temperature region is set. The present invention provides a method for manufacturing a semiconductor device, which includes a step of returning.

Secondly, the wafer is inserted into a furnace having a temperature setting region for growing the thin film and a reflow temperature higher than the temperature, and the thin film is grown in the temperature region for growing the thin film. A wafer is moved to a reflow temperature setting region, and a method for manufacturing a semiconductor device is provided, in which a thin film is reflowed. Thirdly, a temperature for growing a thin film and a reflow temperature higher than the temperature. In a furnace having a set area, the wafer is inserted, the thin film is grown in a temperature area where the thin film is grown, and then the wafer is moved to a reflow temperature set area, and another kind of thin film is formed on the thin film while performing reflow. A method of manufacturing a semiconductor device, which comprises growing a thin film.

Fourth, it comprises a furnace having a predetermined temperature region of a constant length in the depth direction from the insertion end of the wafer and a high temperature region of a constant length higher than the predetermined temperature, and between the predetermined temperature region and the high temperature region. With a mechanism to move the wafer with
It is intended to provide a semiconductor manufacturing apparatus that makes it possible to perform processing such as annealing and film growth by moving a wafer in two regions having different temperatures.

Fifth, a transition region is provided in the middle or in the vicinity of the high temperature region and the low temperature region of the above two regions, and the region is separated from the upper heater and the lower heater to adjust the interval and change the temperature gradient. With a structure that allows
It is intended to provide a semiconductor device having means for preventing the generation of particles by providing an exhaust hole in the area.

[0020]

In the present invention, the rapid heating annealing is realized by using the electric furnace having good thermal stability and the compatibility with the semiconductor process is achieved. That is, taking a typical vertical CVD furnace as an example, it is a relatively low temperature part for growing a thin film in the lower part of the furnace, and a high temperature part for annealing or growing another thin film in the upper part of the furnace. That said, typically one wafer is inserted from below and first a thin film is grown at a low temperature.

The term "low temperature thin film growth" as used herein refers to growth at a furnace temperature of about 700 ° C., which is growth of silicon dioxide using organosilane or disilane, tetraethoxysilane (TEOS), tetramethoxyphosphorus (TMOP). , B-PSG film using tetramethoxyboron (TMOB) or tetramethoxysilicate boron (TMSB) is grown.

High temperature annealing or thin film growth means 850
It is a heat treatment at around C, and the B-PSG film formed previously can be reflowed, and the CVD of the silicon dioxide film using the conventional monosilane can be carried out.

The feature of the present invention is that the electric furnace having a large heat mass can realize a gradual temperature gradient from a low temperature portion to a high temperature portion. Therefore, a wafer having a small heat capacity is rapidly raised from the bottom. By doing so, it is possible to bring it to a high temperature portion, and by immediately returning it to a low temperature portion after a predetermined short-time treatment, rapid thermal annealing can be realized in a clean process subsequent to thin film formation. The thermal stability of the electric furnace has been demonstrated in a vertical furnace that has an excellent in-plane temperature distribution in the cross section, and has the advantage that rapid heating annealing for large wafers of 8 inches or more can be performed without the occurrence of slip lines. .

In the present invention, as described above, the single-wafer type is basically used, but two or three wafers can be simultaneously processed within a range that does not affect the thermal history. For this purpose, the wafer holder does not have to be a special one, and ordinary quartz is sufficient, and it is preferable that the wafer holder is rotatable during processing as in the vertical furnace to ensure the in-plane distribution.

As the embodiment of the present invention, the rapid thermal annealing after the above thin film formation is the best implementation method, but if categorized, the following CVD method is given as an example. Low temperature area High temperature area Low temperature area Lower in vertical furnace Upper in vertical furnace Lower in vertical furnace B B-PSG growth reflow-ro Silicon dioxide growth B-PSG growth-ha Silicon dioxide growth B-PSG growth reflow-ni B- PSG growth Reflow Silicon dioxide growth e Silicon dioxide growth B-PSG growth / reflow-f Silicon dioxide growth B-PSG growth / reflow Silicon dioxide growth To sputter Ti by RTP sintering under N ₂ atmosphere or by nitriding with NH _3. TiN of TiSi ₂ of TiSi ₂

The reflow to the ha can be carried out under the condition of 850 ° C. × 70 minutes (condition 1). 5 from this condition
At 0 ° C high temperature of 900 ° C, the same source / drain diffusion length as condition 1 is 1/5 time, that is, 14 minutes (840 seconds).
Is given by (condition 2). The above reflow is 900
It can be carried out at a temperature of 100 ° C. for 100 seconds (condition 3). This amount of heat is ⅛ of the condition 2, and the condition 3 is considered to be applicable to the manufacture of the 256M-DRAM to which the putter rule of 0.25 μ is applied.

The substrate on which the above-mentioned growth is performed is carried out in the middle of various steps, but in a typical example, as described above, patterning of polysilicon is performed on the surface insulating film of the silicon substrate. It can be performed on the wafer in the as-prepared state.

In the example of C, the B-PSG growth is performed after the silicon dioxide CVD in the low temperature portion, and in the example of E, the B-PSG growth and the reflow are performed simultaneously in the high temperature portion. There is.

By the way, there is known a method in which a low temperature part, a high temperature part and a low temperature part are sequentially provided in a vertical furnace and diffusion is performed on a large number of wafers in this order. It is of the form that it is sent out by nature and is essentially a CV
It is unsuitable for D film formation and rapid thermal annealing.

In a vertical CVD furnace, the reaction gas is generally introduced from the bottom and exhausted from the upper end, but in diffusion, oxidation and heat treatment, the atmospheric gas is generally introduced from the upper end and exhausted from the lower end. Is. In any case, the heater is set so that the temperature distribution of the furnace gradually increases from bottom to top. When the total heat mass is relatively small, for example, as shown in FIG. 1, 500 ° C, 700 ° C, 900 ° C, 11
A constant temperature range of 00 ° C. is maintained, and a heater is provided between these temperature ranges to provide a stepwise distribution. The amount of temperature difference is determined according to the temperature rising speed and the maximum temperature. When the temperature rising speed is increased and the maximum temperature is increased, the step difference is increased. It is possible to stabilize the temperature inside the wafer at each constant temperature portion.

When the overall heat mass is relatively large,
It is not affected by the rapid heating of the wafer, and therefore, it is not necessary to provide the above-mentioned multi-step uniform heating zone.
No heater spacing is required. In this case, as shown in FIG. 2, the constant temperature region is only two regions of 500 ° C. and 1100 ° C., and there is a gradual temperature gradient during this period. This is applied when the temperature rising speed can be reduced.

Further, in the present invention, gas is prevented from flowing from one of the high temperature region and the low temperature region into the other by exhausting gas from the transition region. As a result, it is possible to prevent particles generated / precipitated by the space reaction due to the inflow of the reaction gas. In this structure, it is preferable that the reaction gas or the inert gas such as nitrogen is introduced from both ends of the reaction tube. In this case, both gases are exhausted from the transition region which is the confluent portion. As for the mode of using the various gases described above, the reaction gas is introduced into the temperature region where the wafer is arranged for film formation, and the inert gas such as nitrogen is introduced into the temperature region where other wafers are not arranged. It is good to flush. As a result, it is possible to prevent the reaction gas from flowing into a high temperature or low temperature region where the wafer is not arranged, and prevent contamination and particles from being generated. As described above, by exhausting from the transition region or its vicinity, the upper (lower)
The gas flowing in from the region does not enter the lower (upper) region, and it is possible to effectively prevent contamination, particle generation, and the like.

In the above, the wafer should be placed at a right angle to the insertion direction into the tube, but it may be tilted to some extent, and when the degree of rapid movement is low, it should be parallel to the insertion direction. It is also possible to arrange a plurality of sheets to improve the processing efficiency.

[0034]

EXAMPLE FIG. 3 is a sectional view of a vertical electric furnace used in one example of the present invention. In the figure, 1 is a furnace body containing a heater, 2 is a wafer, 3 is a wafer holder, 4 is a quartz reaction tube, 5 is a quartz heat insulating tube, 6 is a wafer moving rod, and 7
Is a pedestal, 8 is a wafer moving outer tube, 9 is a wafer moving magnet, 10 is a wafer moving drive system, and 11 is a wafer holder elevating system.

FIG. 4 shows the temperature distribution realized by the furnace body (heater) 1. The lower stage is 700 ° C. and the upper stage is 850 ° C.
The transition area is set in the middle.

FIG. 3 shows a state in which the wafer 2 is located in the high temperature region. This time is annealing,
The gas introduced and discharged from the arrow on the right side of the figure to the arrow on the left side may be an inert gas of nitrogen.

One wafer 2 is placed on the wafer holder 3 having a reduced heat mass. Next, a processing method in this embodiment will be described.

First, the wafer holder raising / lowering system 11 is set at the lowermost position shown by the chain double-dashed line. Further, the wafer moving magnet 9 is not at the position shown in FIG. One wafer 2 is taken out from a cassette (not shown) and placed on the wafer holder 3. Next, the wafer holder elevating system 11 is moved to the upper end as shown in FIG. 3, and the pedestal 7 is abutted against the lower end of the quartz reaction tube 4 to seal it. In this state, the wafer is in the temperature range of 700 ° C.

Here, a thin film is formed. As an example,
When a TEOS-based B-PSG film is grown, TEOS, TMOP, TMO are used for a 6-inch wafer.
All of B are kept at a source temperature of 35 to 60 ° C., a carrier gas of nitrogen is bubbled through the source at a flow rate of 400 CC / min, and introduced into the quartz reaction tube 4 in FIG. If the inside of the tube 4 is 0.3 TORR and the reaction is performed at 700 ° C., a growth rate of 100 Å / min can be obtained.

Next, the wafer moving magnet 9 is driven to raise the wafer to a position of 850 ° C. and maintain it for 15 to 30 minutes, as shown in FIG. To 700 ° C.

3 to 6 when the upper high temperature part is 900 ° C.
In the case of 950 ° C. for 35 minutes, each may be maintained at a high temperature portion for 35 to 70 seconds. The overall weight of the wafer holder 3 is kept low, and therefore, there is an advantage that the temperature can be rapidly increased and decreased from 700 ° C to 850 ° C.

In the above-mentioned embodiment, the B-PSG film is grown on the low temperature side and then annealed on the high temperature side. However, in the single-wafer type, compared to the batch type in which a large number of sheets are processed at one time, the process is performed. Since the margin is wide, it is possible to grow the wafer uniformly even at a temperature of 800 ° C. or higher. In particular, even if nitric oxide is added, the generation of particles can be suppressed and a stoichiometric reaction can be achieved.
In the range of up to 850 ° C., the B-PSG film can be grown while performing reflow (while performing the flattening treatment), and therefore, this growth and reflow can be performed on the high temperature side.

It is a common feature that the upper end of the reaction tube 4 terminates in the high temperature region, because the thin film produced adheres strongly to the tube wall in the high temperature portion, and as a result, the wafer Particle accretion on the surface can be avoided.

FIG. 5 is a sectional view of a vertical electric furnace used in the second embodiment of the present invention. In the figure, 12 is a quartz reaction system outer tube, and 13 is a quartz reaction system inner tube, and is characterized by being a double tube type.

FIG. 6 is a sectional view of a vertical electric furnace used in the third embodiment of the present invention. In the figure, 14 is a quartz heater tube, 15 is a heater, 16 is a water cooling jacket, and 17 is a reflector, which is a gold furnace type.

In the example of FIG. 6, heat rays are reflected on the gold surface, and as a result, it is easy to realize a stepwise temperature distribution. Both the embodiment of FIGS. 5 and 6 have the same temperature profile as that of FIG. 3, and the same processing can be performed.

As a method for preventing particle deposition on the wafer surface, there are methods shown in FIGS. 7 and 8. In the figure, 21 is a furnace body containing a heater, 22 is an upper heater, 23 is a wafer holder, 24 is a quartz reaction tube, 25 is a quartz heat insulation tube, 26 is a lower heater, and 27 is a quartz protection tube. In FIG. 7, there is a space for adjusting the space between the lower heater 26 and the upper heater 22, and the upper and lower heater regions are single-tube heating furnaces each having a space capable of accommodating and processing about 25 wafers. The interval adjusting portion is a transition region, and a large number of exhaust holes 30 shown are provided. The lower heater 26 is at a low temperature, and the upper heater 2
2 is set to high temperature. As shown in the figure, there are two gas inlets, one on the lower side and one on the lower side for the reaction gas, and the upper side for the inert gas. The following are examples of the use of this device.

For the growth of CVD PSG, the wafer 2 is set in the lower part of the apparatus and heated to 680 to 750 ° C. by the lower heater 26. TEOS and TMOP are kept at 60 ° C. from the lower gas inlets, respectively, and are flowed over at a flow rate of, for example, 2000 cc / min, and an inert gas such as nitrogen gas is also fed to the upper gas inlets. For example, the flow rate is 2000 cc / min. B
In order to grow PSG, TMB may be added as a reaction gas from the lower gas inlet in the above method. For reflow, the wafer 2 is immediately moved to the position of the upper heater 22, and PSG reflow is performed at 1050 ° C., for example.

For the deposition of diffused impurities from the glass layer, POCl ₃ and O ₂ are introduced at the set position of the lower heater 26. The temperature of the lower heater 26 may be 700 to 800 ° C. After the impurities are deposited, the wafer 2 is moved to the position of the upper heater 22, and drive-in is performed at 900 to 1100 ° C.

Diffusion from Doped Polysilicon The wafer 2 is set at the position of the lower heater 26, and polysilicon doped with one or more of phosphorus, boron, arsenic or antimony is grown on the wafer by a usual method. The reaction gas used to grow polysilicon is Si ₂ H
_In the case of ₆ , polysilicon can be grown at 500 ° C. by heating the lower heater 26. When the source used for growing polysilicon is SiH ₄ , the temperature of the lower heater is set to 610 ° C. Next, the wafer 2 can be moved to the position of the upper heater 22, and an applied process of diffusing impurities at 900 to 1100 ° C. can be performed.

FIG. 8 shows a structure similar to that of the single pipe of FIG. 7 and similarly enables exhaust from the space adjusting portion.

[0052]

As described above, according to the present invention, it is possible to use an electric furnace having a low temperature part and a high temperature part, to form a thin film in the low temperature part and to perform annealing in the high temperature part. ,
Rapid heating annealing can be achieved, thin film formation and annealing can be continuously performed in a furnace, and a clean process can be performed, and a practical process for a wafer of 8 inches or more can be provided.

[Brief description of drawings]

FIG. 1 is a diagram of an apparatus for providing a temperature distribution used to practice the present invention.

FIG. 2 is a diagram of an apparatus for providing another temperature distribution used in the practice of the present invention.

FIG. 3 is a diagram of an embodiment of the present invention.

FIG. 4 is a diagram showing a temperature distribution in the embodiment of FIG.

FIG. 5 is a diagram showing another embodiment of the present invention.

FIG. 6 is a diagram showing another embodiment of the present invention.

FIG. 7 is a diagram showing another embodiment of the present invention.

FIG. 8 is a diagram showing another embodiment of the present invention.

[Explanation of symbols]

 1 Furnace Body (Heater) 2 Wafer 3 Wafer Holder 4 Quartz Reaction Tube 5 Quartz Insulation Tube 6 Wafer Moving Rod 7 Cradle 8 Wafer Moving Outer Tube 9 Wafer Moving Magnet 10 Wafer Moving Drive System 11 Wafer Holder Lifting System 12 Quartz Reaction system outer tube 13 Quartz reaction system inner tube 14 Quartz heater tube 15 Heater 16 Water cooling jacket 17 Reflector plate 21 Furnace body (heater) 22 Upper heater 23 Wafer holder 24 Quartz reaction tube 25 Quartz insulation tube 26 Lower heater 27 Quartz protection tube

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[Procedure amendment]

[Submission date] October 29, 1992

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

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[Figure 3]

[Figure 5]

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Claims (8)

[Claims] 1. A wafer is inserted from an insertion end of a furnace having a predetermined temperature region having a constant length in a depth direction from a wafer insertion end and a high temperature region having a constant length higher than the predetermined temperature, and a predetermined temperature region is inserted. The method of manufacturing a semiconductor device, comprising the steps of: first performing the first treatment, then moving the wafer to a high temperature region, performing the second treatment, and returning the wafer to a predetermined temperature region. 2. The wafer is inserted into a furnace having a temperature for growing a thin film and a reflow temperature setting region higher than the temperature,
The thin film is grown in a temperature range where the thin film is grown, and then
A method of manufacturing a semiconductor device, wherein the wafer is moved to a reflow temperature setting region to reflow a thin film. 3. A wafer is inserted into a furnace having a temperature setting region for growing a thin film and a reflow temperature higher than the temperature, and the thin film is grown in the temperature region for growing the thin film. Move to the reflow temperature setting area,
A method of manufacturing a semiconductor device, wherein another type of thin film is grown on the thin film while performing reflow. 4. The semiconductor device according to claim 1, wherein a transition region is provided between the high temperature treatment region and the low temperature treatment region, and gas is exhausted from the transition region or the vicinity thereof. Manufacturing method. 5. The first processing gas is introduced from a first position on the wafer insertion side of the processing region, and the second processing gas is supplied from a second position opposite to the first position. The method of manufacturing a semiconductor device according to claim 4, wherein the semiconductor device is made to flow. 6. A furnace comprising a predetermined temperature region having a constant length in a depth direction from a wafer insertion end and a high temperature region having a constant length higher than the predetermined temperature, the wafer being located between the predetermined temperature region and the high temperature region. A semiconductor manufacturing apparatus comprising a mechanism for moving a semiconductor. 7. The semiconductor manufacturing apparatus according to claim 6, wherein a transition region is provided between the high temperature treatment region and the low temperature treatment region, and an exhaust hole is formed in or near the transition region. 8. A first processing gas, particularly a reaction gas inlet, is provided at a first position on the wafer insertion side of the processing region, and a second processing gas, particularly an annealing atmosphere gas inlet is provided. The semiconductor manufacturing apparatus according to claim 6 or 7, wherein the semiconductor manufacturing apparatus is provided at a second position opposite to the one position.