JPH07244983A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To increase an operating speed without increasing a chip area. CONSTITUTION:Word shunt parts per one word line of memory arrays MA1 to MAk are provided so that the number of shunt parts becomes the minimum in a memory array MA1 arranged at a position nearest to a first decoder 1 and becomes the maximum in a memory array MAk arranged at a position farthest to the decoder 1 and are successively increased as arrays become farther from the decoder 1 in intermediate memory arrays. When the total number of word shunt parts WS are not changed, longest signal transmission times are shortened by increasing the number of shunt parts in farther memory arrays and the signal transmission times are prolonged by decreasing the number of shunt parts in nearer positions and then signal transmission times are uniformized mutually in respective memory arrays.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device having a large capacity and capable of operating at high speed, comprising a plurality of memory cell arrays each having a row selection line connected to a sub-row selection line and having a low resistance.

[0002]

2. Description of the Related Art In a semiconductor memory device having a memory cell array in which a plurality of memory cells are arranged in a matrix of rows and columns, the memory cells are generally selected in units of rows. A row selection line (word line) for selecting the memory cells row by row is usually formed of polycrystalline silicon because of the ease of manufacturing process. However, since the row selection line formed of polycrystalline silicon has a large resistance value, the signal transmission time becomes long and it is difficult to speed up the operation.

Therefore, a sub-row selection line formed of a low resistance material such as metal is added in parallel with the row selection line and connected to the row selection line at a predetermined interval to reduce the apparent resistance value of the row selection line. Technology has been used (eg 198
4. IEE International Solid State Circuits Conference (IEEEIn
international Solidstate Ci
rcuits Conference), ISSC Digest Off Technical Papers (ISSCC Digest of Technical)
Papers), February 23, 1984, 218-.
See page 219, "A 25 ns 64K SRAM".

Further, as the capacity is increased, the number of memory cells connected to one row selection line increases, and there is a limit to the increase in speed only by lowering the resistance by the above-described sub-row selection line, and Since power consumption also increases, in a large capacity semiconductor memory device, the number of memory cells connected to one row selection line is reduced by dividing the memory cell array into a plurality of memory cells (or providing a plurality of memory cell arrays). In many cases (for example, published by Science Forum, ULSI DRAM technology,
90-94).

FIG. 5 is a circuit diagram showing an example of the most common semiconductor memory device using the above-described technique of reducing resistance by the sub row selection line and the technique of dividing a memory cell array (a plurality of memory cell arrays).

This semiconductor memory device includes a plurality of memory cells Q11 to Qmm arranged in a matrix of rows and columns, and a plurality of word lines (row selection for selecting a plurality of memory cells in a row unit at a selection level). Line) WL1 to WLm,
A plurality of sub-word lines (sub-row selection lines) SWL1 to SWL corresponding to the plurality of word lines WL1 to WLm and formed in close proximity and in parallel with each other with a low resistance material such as a metal material.
m and a plurality of word shunt portions (selection line connecting portions) W for connecting the plurality of word lines WL1 to WLm and the corresponding sub word lines (SWL1 to SWLm) at predetermined intervals.
A plurality of memory cell arrays MA1 each provided with S and sequentially arranged to read the stored data of the selected memory cells.
x, MA2x, ..., MAkx, and a first decoder 1 arranged at predetermined positions to receive an address signal (not shown), decode it, and output it as a first decode signal DA1.
A plurality of second decoders 21 to 2k which are provided corresponding to and close to the memory cell arrays MA1x to MAkx, respectively, and which have a predetermined word line of the corresponding memory cell array (MA1x to MAkx) as a selection level in accordance with the first decode signal DA1. It is configured to have and. In this semiconductor memory device, the memory cell arrays MA1x to MA1x to M
The number of word shunt portions WS of each word line WL1 to WLm of Akx is the same.

[0007]

In this conventional semiconductor memory device, the decode signal DA1 is supplied from one first decoder to the sequentially arranged second decoders 21 to 2k, and the second decoders 21 to 21k are supplied. 2k is a memory cell array (MA1x ...
A predetermined word line (WL1 to WLm) of (MAkx) is set to the selection level, and each word line WL1
To WLm, sub word lines SWL1 to SWLm for reducing the resistance value are connected by a plurality of word shunt sections WS, but each word line WL1 to
Since the number of word shunt sections WS of each WLm is the same for all the memory cell arrays MA1x to MAkx, the maximum signal transmission times inside the memory cell arrays MA1x to MAkx are equal, and therefore the first decoder 1 outputs the same. The operation time until a predetermined memory cell is brought into a selected state by the generated first decode signal DA1 is
The memory cell array (eg, MAkx) arranged farthest from the first decoder 1 has the longest length, and the operating time of the memory cell array (MAkx) influences the operating time of the entire semiconductor memory device. Has the problem of becoming longer.

Further, as a method of shortening this operation time, there is a method of increasing the number of word shunt portions per word line, but there is a problem that the chip area is increased by the increase of the word shunt portions. .

An object of the present invention is to provide a semiconductor memory device capable of shortening the operation time without increasing the chip area.

[0010]

A semiconductor memory device according to the present invention comprises a plurality of memory cells arranged in a matrix of rows and columns, and a plurality of memory cells which are in a selected state row by row at the selection level. A row select line, a plurality of sub-row select lines corresponding to each of the plurality of row select lines, formed in parallel and in parallel with each other, and formed of a low resistance material; and a plurality of the row select lines and corresponding sub-row select lines. A plurality of memory cell arrays, each of which is provided with a plurality of selection line connecting portions connected at a predetermined interval and is sequentially arranged to read the stored data of the memory cells in a selected state, and arranged at a predetermined position to output a first decode signal. Corresponding to the first decoder and each of the plurality of memory cell arrays and provided in proximity to each other, and a predetermined row selection line of the corresponding memory cell array is set to a selection level according to the first decode signal. That in a semiconductor memory device having a plurality of second decoders, said plurality of memory cell arrays each row selection line of each selection line connector, in number,
The memory cell array arranged closest to the first decoder has a minimum value, the memory cell array arranged at the farthest position has a maximum value, and the memory cell array arranged at an intermediate position has a larger value as the distance increases. It has the configuration provided. Further, in order to equalize the longest time of each memory cell array in the signal transmission time from the output terminal of the first decoder to each memory cell, the selection line per row selection line of each memory cell array is equalized. It is configured by defining the number of connection parts.

[0011]

According to the present invention, the number of row selection line connection portions per row selection line of each of the plurality of memory cell arrays is increased as the memory cell array arranged farther from the first decoder is used. First to make the selected state
Since the signal transmission time from the decoder to each memory cell is made uniform, when the number of row selection line connecting portions of the entire semiconductor memory device is the same as the conventional example and the chip area is unchanged, In the memory cell array arranged at the farthest position from the decoder, the number of row selection line connection portions per row selection line is larger than the average value (all of the conventional examples are average values). Therefore, the distance to the first decoder is shortened accordingly, the signal transmission time from the first decoder to this memory cell array is shortened, and the signal line for selecting a memory cell in the memory cell array is shortened. And the signal transmission time becomes short. That is, the longest signal transmission time from the first decoder to the memory cell of this memory cell array can be shortened. Also in other memory cell arrays, the longest signal transmission time from the first decoder to the memory cell is equalized, so that the signal transmission time is similar to that of the memory cell arranged at the farthest position. ing.

Therefore, the reduction in the longest signal transmission time of the memory cell array arranged at the farthest position directly leads to the reduction in the operation time of this semiconductor memory device.

[0013]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

This embodiment is different from the conventional semiconductor device shown in FIG. 5 in that it has a plurality of memory cell arrays MA1x.
To the memory cell array MA1 corresponding to each MAkx
.About.MAk word lines WL1 to WLm, the number of word shunt portions WS arranged in the memory cell array (eg, M
A1) is the smallest, the largest is the memory cell array (eg, MAk) arranged at the farthest position, and the intermediate memory cell array is so arranged that the intermediate memory cell array increases in number as it goes away.
In addition, each of the memory cell arrays MA1 to MA in the signal transmission time from the output terminal of the first decoder 1 to each memory cell.
The point is that the number of word shunt sections WS for each word line of each of the memory cell arrays MA1 to MAk is determined so that the maximum time of each k is equalized.

Next, the time until a predetermined memory cell of the memory cell arrays MA1 to MAk is brought into a selected state by the first decode signal DA1 output from the first decoder 1 of this embodiment, that is, the first How the signal transmission time from the decoder to a predetermined memory cell changes with respect to the conventional example shown in FIG. 5 will be described.

The above-mentioned longest signal transmission time depends on the signal transmission time of the first decoded signal DA1 from the first decoder 1 to the second decoders 21 to 2k and the second decoders 21 to 2k. Decoding operation time and this second
The signal transmission time inside the memory cell array from the decoders 21 to 2k to the predetermined memory cell can be divided into three parts. Since the decoding operation time by the second decoders 21 to 2k is the same in both the present invention and the conventional example, the signal transmission time of the first decode signal DA1 is compared with the signal transmission time in the memory cell array.

As a condition for comparison, the arrangement of each part of the present invention and the conventional example is as shown in FIGS. 1 and 5, and since the chip areas are the same, the number of memory cell arrays (k) and word line 1 are set.
Number of memory cells per book (n), word shunt section WS
Are equal in number. Also, the word shunt section W
For each S1, the signal line of the first decode signal DA1 (hereinafter referred to as the first decode signal line) and the word line are lengthened by ΔL, and the resistance values thereof are increased by ΔR and Δr, respectively. The resistance per memory cell array of the first decode signal line excluding the portion corresponding to WS is R, and the resistance per memory cell of the word line is rs. Further, in the conventional example, the number of word shunt sections is N for each of the memory cell arrays MA1x to MAkx, and in the present invention, N1, N2, ..., Nk for each of the memory cell arrays MA1, MA2 ,. N2
<... Ni <N <N (i + 1) <... Nk.

First, the signal transmission time of the first decode signal line will be described with reference to FIG.

The first decode signal DA1 of the decoder 21
When the input terminal is the reference (0), the decoders 22-2j-2
In the present invention (Rj), the resistance value of the first decode signal line up to the input terminal of the first decode signal DA1 of k is Rj = (j-1) R + (N1 + ... + N (j-1)). ΔR ... (1), and in the conventional example (Rjx), Rjx = (j-1) R + (j-1) N.ΔR (2).

Comparing Rj and Rjx, j≤i
Since N1 to N (j-1) are all smaller than N, Rj <Rjx (3), and when j> i, N1 + ... + N (j-1) = N1 + ... + Nk- ( Nj + ... + Nk) = k.N- (Nj + ... + Nk) ... (4) (j-1) N = k.N- (k-j + 1) .N ... (5) Since it is larger than N, Rj <Rjx similarly holds. That is, when the decoder 21 is used as a reference, all the resistance values of the first decode signal lines up to the input ends of the decoders 22 to 2k can be made smaller than in the conventional example, and the transmission time of the first decode signal DA1 can be reduced. It can be shortened.

Next, each memory cell array MA1 to MAk
The longest signaling time in (MA1x to MAkx) is compared. The resistance value of the sub word line SWL is the word line WL.
Since it is extremely smaller than that of the above, if this is ignored, the point where the resistance value of the word line WL from the second decoder of each memory cell array to the memory cell Q becomes maximum is the middle point (C ). Adjacent 2
An equivalent circuit diagram around one word shunt section WS is shown in FIG.

The number of memory cells Q connected to the word line WS between two adjacent word shunt sections WS is n / (Nj
-1) (n / (N-1) in the conventional example). If this number is odd, the memory cell Q exists at the position of the intermediate point C, and if it is even, the intermediate point C is sandwiched. Two memory cells Q
However, since the numbers n / (Nj−1) and n / (N−1) of the memory cells Q have values sufficiently larger than “1”, the intermediate point C part is usually calculated. The resistance value rj up to the memory cell Q (conventional example r) existing in 1 is as follows, where rw is the resistance of the word shunt section WS.

Rj = rw / 4 + rs · n / 4 (Nj−1) (6) r = rw / 4 + rs · n / 4 (N−1) (7) Equation (6), (7) From the equation, in the conventional example, the same resistance value is obtained in any memory cell array MA1x to MAkx
That is, although the signal transmission time is the same, in the present invention, the resistance value is smaller and the signal transmission time is shorter in the memory cell array arranged farther from the first decoder 1.

Therefore, the longest transmission time of the signal from the first decoder 1 to each memory cell of the memory cell arrays MA1 to MAk is made uniform, and the maximum value is significantly smaller than that of the conventional example. FIG. 4 shows a comparison result between the present invention and the conventional example of the wiring signal transmission time, which is the sum of the transmission time of the first decode signal DA1 and the longest signal transmission time in the memory cell array.

The transmission time of the signal transmitted through the signal line is determined by the resistance value of the signal line and the capacitance added to the signal line. In the comparison of the above-mentioned example and the conventional example, the resistance value was compared without considering the additional capacitance of the signal line, but if the signal line becomes short, it is slightly, but the capacitance of the signal line itself is reduced, Further, in the word line, as the number of word shunt portions increases, the number of memory cells connected to the word line between two adjacent word shunt portions also decreases, so that the additional capacitance is reduced accordingly. Therefore, the signal transmission time is further shortened.

In the above embodiment, the case where a predetermined word line of the memory cell arrays MA1 to MAk is selected by the first decode signal DA1 has been described, but the present invention corresponds to each of the memory cell arrays MA1 to MAk. One common word line is provided for each of the plurality of word lines, and one of these common word lines is used.
The present invention can be applied to a semiconductor memory device having a double word line structure in which a book is selected by a first decoder and one of a plurality of corresponding word lines is selected by a second decoder, and similar effects can be obtained.

[0028]

As described above, according to the present invention, the number of connection portions (selection line connection portions) with the sub-row selection lines per row selection line of a plurality of memory cell arrays is the first decoder. On the other hand, the memory cell array located closest to the memory cell array must have a minimum size, the memory cell array located at the farthest position must have a maximum size, and the memory cell array located at an intermediate position must increase in number as the distance increases. As a result, when the total number of select line connecting portions is not changed, the longest signal transmission of the memory cell array farther from the first decoder is performed as compared with the conventional example having the same number of select line connecting portions for each memory cell array. Since the time can be shortened and the memory cell array in a close position can be stretched and made uniform in each memory cell array, the longest signal transmission time is left and right. The entire operation time, there is an effect that can be shortened without increasing the chip area.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a layout diagram for obtaining a signal line resistance (signal transmission time) between the first and second decoders of the embodiment shown in FIG.

FIG. 3 is an equivalent circuit diagram for obtaining a signal line resistance (signal transmission time) in each memory cell array of the embodiment shown in FIG.

FIG. 4 is a diagram showing a wiring signal transmission time for each memory cell array for explaining the effect of the embodiment shown in FIG. 1;

FIG. 5 is a circuit diagram showing an example of a conventional semiconductor memory device.

[Explanation of symbols]

1, 21 to 2k Decoders MA1 to MAk, MA1x to MAkx Memory cell arrays Q, Q11 to Qmn Memory cells SWL, SWL1 to SWLm Sub word lines WL, WL1 to WLm Word lines WS Word shunt section

Claims (3)

[Claims] 1. A plurality of memory cells arranged in a matrix of rows and columns, a plurality of row selection lines which bring the plurality of memory cells into a selected state in a row unit at a selection level, and each of the plurality of row selection lines. A plurality of sub-row selection lines corresponding to, adjacent to, and formed in parallel with each other, and a plurality of selection line connecting portions for connecting the plurality of row selection lines and the corresponding sub-row selection lines at predetermined intervals. A plurality of memory cell arrays sequentially arranged to read data stored in memory cells in a selected state, a first decoder arranged at a predetermined position to output a first decode signal, and the plurality of memory cell arrays. A semiconductor memory having a plurality of second decoders corresponding to the respective ones and having a predetermined row selection line of the corresponding memory cell array as a selection level according to the first decode signal. In the memory device, the selection line connecting portions of the respective row selection lines of the plurality of memory cell arrays are arranged at the smallest and farthest positions in the memory cell array arranged in the closest position to the first decoder. In the semiconductor memory device, the maximum number is provided in the memory cell array, and the memory cell array arranged at an intermediate position is provided so as to increase in number with increasing distance. 2. The row select line is formed of polycrystalline silicon,
The semiconductor memory device according to claim 1, wherein the sub row selection line is formed of a metal material. 3. A row select line for each memory cell array so that the maximum time of each memory cell array in the signal transmission time from the output terminal of the first decoder to each memory cell is equalized. 2. The semiconductor memory device according to claim 1, wherein the number of selection line connecting portions of the above is determined.