JPH07244736A - Pattern inspection device - Google Patents

Abstract

PURPOSE:To perform stripe conversion which is fast and efficient by expanding data in low-order hierarchical structure, obtained by a rough expansion means, into bat pattern data by a detailed expansion means. CONSTITUTION:The rough expansion circuit 3 functions to perform expansion from a layer of drawing stripes to a layer below it, i.e., a layer of cells. The detailed expansion circuit 5 reads address pointers out of a painter memory 4 in order, accesses data memories 1 and 2 that the pointers indicate to read graphic data out, and decodes the graphic data and outputs element graphic information to a graphic image generation circuit 6, thereby performing the detailed expansion from the cells to graphic data in the layer which is one layer below. Thus, the expansion is performed from the drawing stripes to the cell structure and then from the cell structure to the graphic information to enable the process which is extremely fast.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing technique for converting numerical data into image data, and particularly to a pattern inspection suitable for inspecting a pattern of a mask, a wafer, a liquid crystal substrate or the like used for manufacturing a semiconductor integrated circuit. It relates to the device.

[0002]

2. Description of the Related Art One of the major causes of a decrease in yield in manufacturing a large scale integrated circuit (LSI) is a defect of a mask used in manufacturing by a photolithography technique. In mask manufacturing, mask defects cause a great deal of damage, and therefore, highly accurate inspection is required.

Therefore, conventionally, a pattern inspection apparatus for inspecting a pattern defect of a mask manufactured by an electron beam drawing apparatus has been used. As shown in FIG. 7, this apparatus irradiates a mask 102 to be inspected with light from a lamp 101 to form a mask 1
02. An optical signal corresponding to the pattern formed on 02 is detected by the photo array sensor 104, the observation data 110 processed by the sensor circuit 105, and the design data 109 used when the pattern is formed on the mask 102. Are configured to compare. More specifically, design data 1
09 is stored in a storage medium such as a magnetic disk and is generated as standard data 111 via the bit expansion circuit 108 and the reference data generation circuit 107.
And the observation data 110 are compared and collated, and the mask 10
It is intended to inspect the presence / absence of a pattern defect and the correctness / absence of the pattern.

Then, using this type of device, the mask 1
When the pattern 02 is inspected, the table 103 on which the mask 102 is placed is continuously moved in the x direction or the y direction to scan the entire surface of the mask in a strip shape, and the strip inspection is performed for each stripe. . Further table 103
The table 103 is moved by the stripe width in the direction orthogonal to the continuous movement direction of the above, and the above stripe inspection is repeated.
An inspection covering the entire pattern formation region of the mask 102 is performed.

In this stripe inspection, an optical signal corresponding to the pattern formed on the mask 102 is detected as a detection signal by the photodiode array 104 and the sensor circuit 105, and is also used when forming a pattern on the mask 102. The designed data 109 is read from the computer, the reference data 111 corresponding to the optical signal is generated by the bit expansion circuit 108, and both signals are stored in the table 1.
The process of performing comparison and verification for each measurement position 04 is performed while continuously moving the table 104 at a constant speed.

In such a database-based comparison method, the design data input to the bit expansion circuit 109 includes a stripe 120 and a fixed area 121 as shown in FIG.
The area is separated by, and the area is described in the format of FIG. 9 in which the position of the element graphic and the graphic code indicating the graphic shape, the length of each side of the graphic, and the like are described. This data description format is exemplified by the types shown in FIG.

The process of extracting the area 121 starts by directly inputting the data used for drawing into the inspection device. First, if the stripe inspection width of the inspection device and the stripe width of the data used for drawing match, the area can be easily divided into units of 121 and the bit expansion processing can be continued.

However, the stripe inspection width which can be measured by the inspection device differs depending on the magnification of the optical system, and is high magnification when high sensitivity and high precision inspection is required, and low magnification when low sensitivity and high speed inspection are required. Since the inspection is performed in step 1, the stripe inspection width of the inspection device and the stripe width of the data used for drawing often do not match (do not match). When the stripe inspection width of the inspection device and the stripe width of the data used for writing do not match in this way, the stripe width of the drawing data must be converted in advance to inspection-specific data that matches the stripe inspection width. However, the conversion process for that purpose took time and the efficient inspection could not be performed.

Further, in such a conventional inspection apparatus,
Even when the inspection stripe width is slightly inconsistent with the drawing stripe width, conversion processing is performed over the entire drawing stripe to match the drawing data with the stripe inspection width in accordance with the processing algorithm at each inspection process. There was a need. For this reason, an extra processing time is required by performing the stripe conversion, which has been a cause of limiting the inspection speed.

As described above, in the conventional inspection apparatus, it is necessary to create two or more types of drawing design data for the drawing apparatus and the inspection apparatus for one product mask, and it takes time to perform conversion processing for that purpose. However, there were some issues to be improved, such as high cost.

[0011]

In the above-mentioned conventional pattern inspection apparatus, it is necessary to create two or more types of drawing design data for the drawing apparatus and the inspection apparatus for one product mask, and conversion for that purpose is required. There was a problem that processing took time.

The present invention has been made to improve the above situation, and an object of the present invention is to perform high-speed and efficient stripe conversion to improve the inspection speed of a pattern inspection apparatus.

[0013]

In order to achieve the above object, in the present invention, irradiation means for irradiating a sample on which a pattern is formed with light, and transmitted light or reflected light of the light irradiated on the sample are provided. Light receiving means for receiving light and outputting measurement data according to the image of the pattern, storage means for storing the drawing data used for drawing and forming the pattern, and reading the drawing data from the storage means An inspection of a pattern formed on the sample by comparing the measurement data and the bit pattern data with a bit expanding means that inputs and creates bit pattern data according to the drawing data based on the drawing data. In the pattern inspecting device, the writing data is a plurality of writing stripe data having a predetermined stripe width. And is stored in the storage means, and each of these drawing stripe data is composed of a data structure in which the pattern is described in a hierarchical manner, and the bit expanding means is an upper layer that constitutes the drawing stripe pattern. It is composed of a rough expanding means for expanding the structure data into lower hierarchical structure data, and a detailed expanding means for expanding the lower hierarchical structure data obtained by the general expanding means into the bit pattern data. It is characterized by that.

[0014]

According to the pattern inspection apparatus of the present invention having the above-described structure, the drawing data used when designing the pattern formed on the sample is defined as the drawing stripe data having a predetermined stripe width, and the drawing stripe is formed. Since the data is defined as data of a plurality of hierarchical structures, and these hierarchical structure data are expanded by the general expansion means and the detailed expansion means, respectively, the drawing stripe data can be expanded to graphic information as in the conventional case. It is possible to perform extremely high-speed processing as compared with what was done in.

Further, since the drawing data used for the drawing device is converted into the stripe data for the inspection at high speed in the pattern inspection device during execution of the pattern inspection, the inspection speed can be improved and the pattern inspection can be performed. It is not necessary to prepare the inspection data for the inspection device separately.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A pattern inspection apparatus of the present invention will be described below with reference to the drawings. Generally, in a mask pattern for a semiconductor integrated circuit, a pattern having a predetermined definition often appears repeatedly, and design data can also describe this pattern in a modular manner and adopt a hierarchical structure that can be defined as repetition of the module. It is valid. Therefore, the pattern inspection apparatus of the present invention employs this "hierarchical structure" data.

Further, in the drawing of the mask pattern by the drawing device, a strip-shaped region having a deflection width of the electron beam, that is, a "drawing stripe" is continuously drawn on the entire surface of the mask and a direction orthogonal to the continuous drawing direction. In addition, it is performed to cover the entire surface of the pattern formation region by repeatedly moving the "drawing stripe" by stepwise moving by the drawing stripe width. In this specification, the width of the "drawing stripe" is defined as d, and the above-mentioned modular description unit is defined as "cell". Further, one drawing stripe is composed of an aggregate of "cells" defined by arbitrary dimensions (according to the inspection condition of the inspection device). Further, one cell is defined by an aggregate of a plurality of element figures. Of these, the data that describes the coordinates for arranging cells is called "cell arrangement data",
Data describing a set of element graphics is called "graphic data". The size of the cell is not constant and varies depending on the pattern to be described, but the maximum size is restricted such that one side is a square with the drawing stripe width.

The database comparison type inspection apparatus such as the pattern inspection apparatus of the present invention uses the same data as the design data for drawing of the drawing apparatus as the inspection reference data, but the same stripe as the drawing stripe width of the drawing apparatus. It is not always possible to inspect with the width d. In the following embodiments, the stripe width for inspection is k, and the case of d ≧ k will be described.

(First Embodiment: Configuration and Operation) FIG. 1 is a schematic configuration block diagram according to a first embodiment for explaining a main part of a pattern inspection apparatus of the present invention. FIG. 1 shows the conventional FIG.
The portion corresponding to the bit expansion circuit 108 and the reference data generation circuit 107 of the pattern inspection apparatus shown in FIG. 2 is shown, and other components such as the lamp 101 and the mask 10 are shown.
2, table 103, photo array sensor 104, sensor circuit 105, comparison determination circuit 106, design data 1 stored in a storage medium such as a magnetic disk or magnetic tape
The description of 09 is omitted because it is the same as the conventional one.

That is, the pattern inspection apparatus of the present invention is
As shown in FIG. 1, the portions corresponding to the conventional bit expansion circuit 108 and the reference data generation circuit 107 have a new configuration, and the data memories 1 and 2, the general expansion circuit 3,
The pointer memory 4, the detailed expansion circuit 5, and the graphic image generation circuit 6 are roughly configured.

In this embodiment, the design data stored in a storage medium such as a magnetic disk or magnetic tape is
As shown in FIG. 2, the drawing stripe pattern width is defined, and the data of the first drawing stripe 14 and the data of the second drawing stripe 15 are transferred to the two data memories 1 and 2, respectively, as shown in FIG. Then, the state is temporarily accumulated. The areas of the cell layout data and the cell graphic data described above are provided in the respective data memories 1 and 2.

The cut-out information 7 for cutting out an inspection stripe having a width different from the drawing stripe width from the drawing stripe is input to the general outline developing circuit 3 by means of a command from the upper control computer. The content of the cut-out information 7 includes a position and a width at which the inspection stripe is cut out from the drawing stripe, a flag for setting the inspection stripe across two drawing stripes, and the like.

The general expansion circuit 3 reads out the cell arrangement data information in the data memories 1 and 2, judges from the cell coordinates and the cell dimensions, and even a part of the cells is included in the target inspection stripe range. In this case, the address pointer for accessing the graphic data area of the cell is written in the pointer memory 4.

That is, the general expansion circuit 3 has a function of expanding the hierarchy of the drawing stripes to the lower hierarchy, that is, the hierarchy of the cells. The detailed expansion circuit 5 is
The address pointers in the pointer memory 4 are sequentially read, and the data memories 1 and 2 pointed to by the pointers are further read.
Access the inside to read the graphic data. Then, the detailed expansion circuit 5 decodes the graphic data and outputs the element graphic information to the graphic image generation circuit 6 in the format shown in FIG.

That is, the detailed expansion circuit 5 has a function of in charge of detailed expansion from a cell hierarchy to a lower hierarchy, that is, a hierarchy of graphic description. The series of processes described above is a case where the target inspection stripe is included in one drawing stripe like the first inspection stripe 16 and the second inspection stripe 17 in FIG.

On the other hand, when the target inspection stripe extends over the two drawing stripes 14 and 15 like the third inspection stripe 18, the schematic expansion circuit 3 of FIG.
By alternately accessing the two data memories 1 and 2 according to a certain rule and writing information to one pointer memory 4, a desired cell can be extracted from two drawing stripes. In this case, the detailed expansion circuit 5 accesses the data memory 1 to read the graphic data or accesses the data memory 2 depending on whether the original belonging of the read cell is the first drawing stripe 14 or the second drawing stripe 15. Then, the operation for switching whether to read the graphic data is performed. This switching method is performed by, for example, the data memory 1,
2 is managed by a serial address, an offset is superimposed on the address for the data memory 2, and a method such as preparing a dedicated signal line bus for designating a bank in addition to the address bus is adopted. You can

In the first embodiment, the general expansion circuit 3 and the detailed expansion circuit 5 may be operated at the same time in accordance with the progress of the inspection of one inspection stripe, or may be performed prior to the inspection. It is also possible to activate the expansion circuit 3 and, after the general expansion for one inspection stripe, to activate the detailed expansion circuit 5 successively to advance the inspection for that inspection stripe. As a specific method, first, when operating in the former same period, bus competition occurring in the data memories 1 and 2 and the pointer memory 4 is arbitrated by a certain rule. Further, the latter continuous activation can be realized by similar control of the data memories 1 and 2 and switching the bus of the pointer memory 4 to the operating circuit side.

In the first embodiment, the pointer memory functions as a first-in, first-out type buffer, and the general expansion circuit 3 and the detailed expansion circuit 5 operate in units of inspection stripes.

(Embodiment 1 Operation / Effect) As described above, in the first embodiment of the present invention, the design data for drawing is defined as a group of drawing stripes, and the drawing stripes are defined as a group of cells. However, a hierarchical structure is adopted in which cells are defined as an aggregate of element figures.

Then, the general expansion circuit 3 reads out the cell arrangement data information in the data memories 1 and 2 and writes the address pointer for accessing the graphic data area of the cell to the pointer memory 4 so that the data can be read from the drawing stripe. The expansion to the cells of the hierarchy below the step is implemented.

Further, the detailed expansion circuit 5 sequentially reads the address pointers in the pointer memory 4, accesses the data memories 1 and 2 pointed to by the pointers, reads the graphic data, decodes the graphic data, and decodes them. By outputting the graphic information to the graphic image generation circuit 6,
Detailed development is performed from the cell to the graphic data in the layer one step lower.

In this way, the development from the drawing stripe to the cell structure and from the cell structure to the figure information are performed stepwise as described above, so that the drawing stripe to the figure information is developed in a single step as in the prior art. Compared with the above, extremely high speed processing becomes possible.

Further, not only when the target inspection stripe is covered by one drawing stripe, but also when the target inspection stripe extends over the two drawing stripes 14 and 15, the general development is performed. Circuits 3 and 2
This can be dealt with by alternately accessing the combination of two data memories 1 and 2.

(Second Embodiment: Configuration / Operation) FIG. 3 is a schematic block diagram showing a second embodiment of the present invention. Similar to FIG. 1, FIG. 3 also includes the bit expanding circuit 108 and the reference data generating circuit 107 of the conventional pattern inspection apparatus shown in FIG.
Corresponding to the other components, such as the lamp 101, the mask 102, the table 103, the photo array sensor 104, the sensor circuit 105, and the comparison / determination circuit 1.
06, the design data 109 stored in a storage medium such as a magnetic disk or a magnetic tape is the same as the conventional one, and therefore its description and illustration are omitted.

Like the first embodiment, this second embodiment is also roughly composed of data memories 1 and 2, a general expansion circuit 3, a pointer memory 4, a detailed expansion circuit 5, and a graphic image generation circuit 6. The second embodiment is different from the first embodiment in that the pointer memory 4 has a plurality of banks 8,
The feature is that 9 and 10 are provided.

It is possible to write information from the general expansion circuit 3 to the plurality of banks 8, 9 and 10. However, from the detailed expansion circuit 5, one bank is selected from among the plurality of banks for each inspection stripe. It is configured to read. The data memories 1 and 2 can be accessed from the general expansion circuit 3 or the detailed expansion circuit 5 by switching the buses.

The function of the second embodiment having the above configuration will be described with reference to FIG. As shown in FIG. 2, the drawing stripe pattern width is defined, and the data of the first drawing stripe 14 and the data of the second drawing stripe 15 are transferred to the two data memories 1 and 2, respectively, as shown in FIG. Then, the state is temporarily accumulated. The areas of the cell layout data and the cell graphic data described above are provided in the respective data memories 1 and 2. First, the general expansion circuit 3 uses the cut-out information 11 by means such as a command from the host computer to determine the stripe width cut-out dimension positions 21 to 25 from the drawing stripe to the inspection stripe.
To know Then, the cell arrangement data information is read from the data memories 1 and 2, and it is determined which inspection stripe the cell coordinates correspond to. Bank 8 of pointer memory 4,
9 and 10 are reserved corresponding to the above-mentioned inspection stripes.

The general expansion circuit 3 writes an address pointer for accessing the graphic data area of the cell in the bank 8, 9, 10 for the inspection stripe determined from the coordinates of the cell in the pointer memory 4. If the read cell is a cell 27 that spans two test stripes
In this case, the data is registered in the banks for both the first inspection stripe 16 and the second inspection stripe 17.

That is, the general expansion circuit 3 has a function of expanding the hierarchy of the drawing stripes to the lower hierarchy, that is, the hierarchy of the cells. The detailed expansion circuit 5 is
Pointer memory 4 according to the progress of the inspection stripe inspection
The address pointer is read out from the bank inside, and the data memories 1 and 2 pointed to by the pointer are accessed to read the graphic data. Then, the detailed expansion circuit 5 decodes the graphic data and outputs the element graphic information to the graphic image generation circuit 6 in the format shown in FIG.

That is, the detailed expansion circuit 5 has a function of in charge of detailed expansion from a cell hierarchy to a lower hierarchy, that is, a hierarchy of graphic description. In the second embodiment, since the cut-out positions of a plurality of inspection stripes are designated, in the relation of (drawing stripe width d) ≧ (inspection stripe width k), the general expansion circuit 3 is used for a plurality of inspection stripes at a time. Can generate an address pointer for Therefore, prior to the inspection, the general expansion circuit 3 is activated, and after the general expansion of a plurality of inspection stripes, the detailed expansion circuit 5 is activated successively to inspect the plural stripes.

That is, in one rough development process, the address to the graphic data of a part of the inspection stripes 18 extending from the first drawing stripe 14 to the two inspection stripes 16 and 17 and the second drawing stripe 15 in FIG. The pointers are assigned to the first to third banks 8 to 3 of the pointer memory 4.
Are generated in each bank 10. In the detailed expansion circuit 5, the bank in the pointer memory 4 to be quoted for each inspection stripe is specified by the bank specifying information 12 by means such as a command from the upper control computer. For this reason,
When inspecting the first inspection stripe 16, the detail expansion circuit 5 accesses the first bank 8 of the pointer memory 4, and when inspecting the second inspection stripe 17, The operation of accessing the second bank 9 is controlled.

Since the third inspection stripe 18 straddles the first drawing stripe 14 and the second drawing stripe 15, in the second embodiment, the general expansion circuit 3 sets the two data memories 1 and 2 at a constant level. Access alternately according to the rules of
By writing the processing result to the third bank 10 of the pointer memory 4, desired cells can be extracted from the two drawing stripes. In this case, the detailed expansion circuit 5 switches and accesses the data memory 1 or the data memory 2 depending on whether the original belonging of the read cell is the first drawing stripe 14 or the second drawing stripe 15. As the switching means, a serial address or offset method or the like can be adopted as in the first embodiment.

(Embodiment 2: Operation / Effect) As described above, in the second embodiment of the present invention, design data for drawing is defined as an assembly of drawing stripes, and drawing stripes are defined as an assembly of cells. However, a hierarchical structure is adopted in which cells are defined as an aggregate of element figures.

In the general expansion circuit 3, the cell arrangement data information in the data memories 1 and 2 is read out, and the address pointer for accessing the graphic data area of the cell is written in the pointer memory 4. Deployment of cells to the lower layer structure is performed.

Further, the detailed expansion circuit 5 sequentially reads the address pointers in the pointer memory 4, accesses the data memories 1 and 2 pointed to by the pointers, reads the graphic data, decodes the graphic data, and decodes them. By outputting the graphic information to the graphic image generation circuit 6,
Detailed development is performed from cells to graphic data of a one-step lower layer structure.

In this way, the development from the drawing stripe to the cell structure, and from the cell structure to the figure information in a stepwise manner, the development from the drawing stripe to the figure information is performed one step as in the conventional case. Compared with the above, extremely high speed processing becomes possible.

Further, not only when the target inspection stripe is included in one drawing stripe, but also when the target inspection stripe is spread over the two drawing stripes 14 and 15, the general development is performed. Circuits 3 and 2
This can be dealt with by alternately accessing the combination of two data memories 1 and 2.

Further, in the second embodiment, since the cut-out positions of a plurality of inspection stripes are designated, in the relation of (drawing stripe width d) ≧ (inspection stripe width k), the general expansion circuit 3 Can generate address pointers for multiple check stripes at one time. For this reason, the general expansion circuit 3 is activated prior to the inspection, and after the general expansion for a plurality of inspection stripes, the detailed expansion circuit 5 is activated successively to perform the inspection for the plurality of stripes. Can be inspected.

(Third Embodiment: Configuration / Operation) FIG. 4 is a schematic block diagram for explaining a third embodiment of the present invention. Similar to FIGS. 1 and 3, FIG. 4 also shows a portion corresponding to the bit expansion circuit 108 and the reference data generation circuit 107 of the conventional pattern inspection apparatus shown in FIG. 7, and other components, the lamp 101, Mask 102, table 103,
The design data 109 stored in the photo array sensor 104, the sensor circuit 105, the comparison / determination circuit 106, and the storage medium such as the magnetic disk or the magnetic tape is the same as the conventional one, and the description and illustration thereof are omitted.

Like the first embodiment, the third embodiment is also roughly composed of the data memories 1 and 2, the general expansion circuit 3, the pointer memory 4, the detailed expansion circuit 5, and the graphic image generation circuit 6, The third embodiment is different from the second embodiment in that a second pointer memory 30, a second detailed expansion circuit 31, and two systems of detailed expansion circuits 5 and 3 are provided.
The configuration is characterized by including an arbiter 43 that receives the output of 1 and outputs it to the bit image generation circuit 6.

The function of the third embodiment having the above-mentioned structure will be described with reference to FIG. As shown in FIG. 2, the drawing stripe is defined by a predetermined pattern width, and the two data memories 1 and 2 respectively include a first drawing stripe 14 and a second drawing stripe 15 as shown in FIG. The data is transferred, and the data is temporarily stored. And
The respective data memories 1 and 2 are provided with areas for the above-mentioned cell arrangement data and cell graphic data.

First, the general expansion circuit 3 determines a plurality of banks 8 in the first pointer memory 4 according to the inspection stripe width d and the division positions 21 to 23 given by the cut-out information 11 by the command from the host computer. , 9 and 10 write out address pointers for cell graphics. It is assumed that the processing of the general expansion circuit 3 is performed in advance while the first and second detailed expansion circuits 5 and 31 are not operated.

In the third embodiment, the schematic expansion circuit 3 selects a cell that can be extracted from the first drawing stripe 14 as a first pointer even when the drawing stripe 2 extends over two drawing stripes like the third inspection stripe 18. Only the data is output to the third bank 10 of the memory 4, and the extraction from the second drawing stripe 15 is not performed.

Subsequent to the completion of the processing of the general expansion circuit 3, the detailed expansion circuit 5 is activated in accordance with the progress of the stripe inspection,
Detailed expansion processing of the first and second inspection stripes 16 and 17 is performed. These first and second inspection stripes 16 and 17
Since the drawing stripes do not cross over, only one of the detailed expansion circuits 5 and 31 of the first or second system operates to execute a predetermined detailed expansion process. If first
When the detailed expansion circuit 5 of 1 operates, the arbiter 43 functions so as to distribute the output from the operating first detailed expansion circuit 5 exclusively.

The data buses of the respective parts in which the detailed expansion circuit on one side is operating are connected as follows. In other words, the pointer bus 3 through which the detailed expansion circuit accesses the pointer memory
The banks 8, 9, 10 of the first pointer memory 9 can be accessed by opening the cells 8, 39 on the side of the first detailed expansion circuit 38 in operation. On the other hand, the pointer bus 39 on the inactive side is cut off. The graphic data buses 34 and 35 to which the detailed expansion circuit accesses the data memory are also opened by the side of the first detailed expansion circuit 34 which is operating, and the first data memory 1 can be accessed. The graphic data bus 35 on the inactive side is cut off.

While the detailed expansion circuit 5 is operating, the general expansion circuit 3 is the second one on the side not accessed by the detailed expansion circuit 5.
The data memory 2 and the second pointer memory 30 can be operated. Therefore, the graphic data bus 33 for the general expansion circuit 3 and the pointer bus 37 are activated.

The operating state of the one-sided detailed expansion circuit is succeeded to the scene of inspecting the second inspection stripe 17. The third inspection stripe 18 in which the writing stripe straddles functions as follows.

As described above, the general expansion circuit 3 can be operated by using the data memory and the pointer memory to which the bus is connected even when one of the detailed expansion circuits is operating. In other words, even after the detailed expansion circuit 5 is operating after the general expansion processing of the first drawing stripe 14, the second drawing stripe data 14 stored in the second data memory 14 is stored.
Can be processed and written to the second pointer memory 30. At this time, the general development circuit 3 recognizes the positions 24 and 25 at which the inspection stripe is cut out from the second drawing stripe 15 by the cut-out information 11 by means such as a command.

The general expansion circuit 3 assigns the pointer for the third check stripe 3 to the first bank 40 of the second pointer memory 30, and similarly the pointers for the fourth and fifth check stripes to the first bank 40. It outputs to the second and third banks 41 and 42.

At the time when the general development processing of the second drawing stripe 15 is completed, there is a stripe crossing third
The pointers for the inspection stripes 18 are distributed and stored in the third bank 10 of the first stack pointer and the first bank of the second stack pointer.

When inspecting the third inspection stripe 18, the following procedure is performed. The bank specification information 1 is used as a command for accessing the third bank of the first pointer memory 4 and the first data memory 1 to the first detailed expansion circuit 5.
2 is sent, and the bank specification information 32 is sent as a command to access the first bank 40 of the second pointer memory 30 and the second data memory 2 to the second detailed expansion circuit 31. Set the situation and activate each detail expansion circuit. The arbiter 43 has two detailed expansion circuits 5 and 3.
The graphic data from 1 is received, the order is judged according to items such as x or y coordinates, and the figure data is output to the bit image generating means 6.

For the following fourth check stripe 19, the second detailed expansion circuit 31 is provided with the second pointer memory 3
The status of the bus is set by sending the command 22 for accessing the second bank 41 of 0 and the second data memory 2, and the second detailed expansion circuit 31 is activated. Arbiter 43
Functions to distribute the graphic data from the second detailed expansion circuit 31 exclusively.

When the inspection of the third inspection stripe 18 is completed, the data in the first data memory 1 and the first pointer memory 4 are used up. Therefore, the third drawing stripe data can be continuously input to the first data memory 1, and the rough expansion processing can be performed using the first pointer memory.

(Embodiment 3: Action / Effect) As described above, also in the third embodiment of the present invention, design data for drawing is defined as an assembly of drawing stripes, and the drawing stripe is defined as an assembly of cells. However, a hierarchical structure is adopted in which cells are defined as an aggregate of element figures.

Then, in the general expansion circuit, the cell arrangement data information in the data memories 1 and 2 is read out, and the address pointer for accessing the graphic data area of the cell is written in the pointer memory, so that one layer below the drawing stripe. Expansion of the structure into cells is carried out.

Further, the detailed expansion circuit sequentially reads the address pointers in the pointer memory, further accesses the data memories 1 and 2 pointed by the pointers, reads the graphic data, decodes the graphic data, and extracts the element graphic information. Is output to the graphic image generating circuit 6, the detailed expansion from the cell to the graphic data of the one-step lower layer structure is performed.

In this way, the development from the drawing stripe to the cell structure and from the cell structure to the figure information are performed stepwise as described above, so that the drawing stripe to the figure information is developed in a single step as in the prior art. Compared with the above, extremely high speed processing becomes possible.

Further, not only when the target inspection stripe is covered by one drawing stripe, but also when the target inspection stripe extends over the two drawing stripes 14 and 15, the general development is performed. Circuits 3 and 2
This can be dealt with by alternately accessing the combination of two data memories 1 and 2.

Further, in this third embodiment, since the two systems of pointer memories and the two systems of the detailed expansion circuits are provided, the general expansion circuit is as described above, even when one of the detailed expansion circuits is operating, the bus is It can be operated using the connected data memory and pointer memory. In other words, after the first drawing stripe 14 is roughly expanded, the second drawing stripe data 14 stored in the second data memory is processed and the second pointer is processed even if the detailed expansion circuit 5 is operating. Since the data can be written in the memory 30, extremely efficient inspection can be performed.

(Fourth Embodiment: Configuration / Operation) FIG. 5 is a schematic block diagram for explaining a fourth embodiment of the present invention. Similarly to FIGS. 1, 3 and 4, FIG. 5 also shows a portion corresponding to the bit expansion circuit 108 and the reference data generation circuit 107 of the conventional pattern inspection apparatus shown in FIG. 7, and other components, Lamp 101, mask 102, table 1
03, photo array sensor 104, sensor circuit 105,
The comparison / determination circuit 106 and the design data 109 stored in a storage medium such as a magnetic disk or a magnetic tape are the same as the conventional ones, and therefore description and illustration thereof are omitted.

Like the first embodiment, the fourth embodiment is also roughly composed of a data memory, a rough developing circuit 3, a pointer memory 4, a detailed developing circuit 5 and a graphic image generating circuit 6. The third embodiment is characterized in that it has three systems each of a data memory and a pointer memory as compared with the third embodiment.

The function of the fourth embodiment having the above configuration will be described with reference to FIG. As shown in FIG. 2, the drawing stripe is defined by a predetermined pattern width, and the three data memories 1, 2, and 44 respectively have a first drawing stripe 14 and a second drawing stripe as shown in FIG. 15
Then, the data of the third drawing stripe (not shown) is transferred, and the data is temporarily stored. Then, in the respective data memories 1, 2 and 44, areas for the above-mentioned cell arrangement data and cell graphic data are provided. First, the general expansion circuit 3 determines the plurality of banks 8, 9 in the first pointer memory 4 according to the inspection stripe width d and the division positions 21 to 23 given by the cut-out information 11 by a command from the host computer. Write out the address pointer for the cell graphic in 10. It is assumed that the processing of the general expansion circuit 3 is performed in advance while the first and second detailed expansion circuits 5 and 31 are not operated.

In the fourth embodiment as well, the general expansion circuit 3 selects the cells that can be extracted from the first drawing stripe 14 as the first pointer even when the drawing stripes extend over two drawing stripes like the third inspection stripe 18. Only the data is output to the third bank 10 of the memory 4, and the extraction from the second drawing stripe 15 is not performed.

Subsequent to the completion of the processing of the general expansion circuit 3, the detailed expansion circuit 5 is activated in accordance with the progress of the stripe inspection,
Detailed expansion processing of the first and second inspection stripes 16 and 17 is performed. These first and second inspection stripes 16 and 17
Since the drawing stripes do not cross over, only one of the detailed expansion circuits 5 and 31 of the first or second system operates to execute a predetermined detailed expansion process. If first
When the detailed expansion circuit 5 of 1 operates, the arbiter 43 functions so as to distribute the output from the operating first detailed expansion circuit 5 exclusively.

The data buses of the respective parts in which the detailed expansion circuit on one side is operating are connected as follows. In other words, the pointer bus 3 through which the detailed expansion circuit accesses the pointer memory
The banks 8, 9, 10 of the first pointer memory 4 can be accessed by opening the cells 38, 39 on the side of the first detailed expansion circuit 38 in operation. On the other hand, the pointer bus 39 on the inactive side is cut off. The graphic data buses 34 and 35 to which the detailed expansion circuit accesses the data memory are also opened by the side of the first detailed expansion circuit 34 which is operating, and the first data memory 1 can be accessed. The graphic data bus 35 on the inactive side is cut off.

While the detailed expansion circuit 5 is operating, the general expansion circuit 3 is the second one on the side not accessed by the detailed expansion circuit 5.
The data memory 2 and the second pointer memory 30 can be operated. Therefore, the graphic data bus 33 for the general expansion circuit 3 and the pointer bus 37 are activated.

The operating state of the one-sided detailed expansion circuit is succeeded to the scene of inspecting the second inspection stripe 17. The third inspection stripe 18 in which the writing stripe straddles functions as follows.

As described above, the general expansion circuit 3 can be operated by using the data memory and the pointer memory to which the bus is connected even when one of the detailed expansion circuits is operating. In other words, even after the detailed expansion circuit 5 is operating after the general expansion processing of the first drawing stripe 14, the second drawing stripe data 14 stored in the second data memory 14 is stored.
Can be processed and written to the second pointer memory 30. At this time, the general development circuit 3 recognizes the positions 24 and 25 at which the inspection stripe is cut out from the second drawing stripe 15 by the cut-out information 11 by means such as a command.

The general expansion circuit 3 assigns the pointer for the third check stripe 3 to the first bank 40 of the second pointer memory 30, and similarly the pointers for the fourth and fifth check stripes to the first bank 40. It outputs to the second and third banks 41 and 42.

At the time when the general development processing of the second drawing stripe 15 is completed, there is a stripe crossing third
The pointers for the inspection stripes 18 are distributed and stored in the third bank 10 of the first stack pointer and the first bank of the second stack pointer.

When inspecting the third inspection stripe 18, the following procedure is performed. The bank specification information 1 is used as a command for accessing the third bank of the first pointer memory 4 and the first data memory 1 to the first detailed expansion circuit 5.
2 is sent, and the bank specification information 32 is sent as a command to access the first bank 40 of the second pointer memory 30 and the second data memory 2 to the second detailed expansion circuit 31. Set the situation and activate each detail expansion circuit. The arbiter 43 has two detailed expansion circuits 5 and 3.
The graphic data from 1 is received, the order is judged according to items such as x or y coordinates, and the figure data is output to the bit image generating means 6.

The fourth embodiment has three systems of data memory and pointer memory in addition to the third embodiment, so that the third inspection stripe 18 shown in FIG. First and second detailed expansion circuits 5 and 3 under inspection
1 is in operation, the general expansion circuit 3 uses the third data memory 44 and the third pointer memory 45,
It is possible to roughly develop the third drawing stripe (not shown). This configuration is very effective in avoiding the rate limiting by the rough expansion processing when the rough expansion processing takes a relatively long time.

(Fourth Embodiment: Action / Effect) As described above, also in the fourth embodiment of the present invention, design data for drawing is defined as a set of drawing stripes, and drawing stripes are defined as a set of cells. However, a hierarchical structure is adopted in which cells are defined as an aggregate of element figures.

Then, in the general expansion circuit, the cell arrangement data information in the plurality of data memories is read out, and the address pointer for accessing the graphic data area of the cells is written out in the pointer memory, so that one-step lower layer structure from the drawing stripe. Is deployed to the cells.

Further, the detailed expansion circuit sequentially reads the address pointer in the pointer memory, accesses the data memory pointed to by the pointer, reads the graphic data, decodes the graphic data, and obtains the element graphic information as a graphic image. By outputting to the generation circuit, detailed expansion from the cell to the figure data of the one-step lower layer structure is performed.

In this way, the development from the drawing stripe to the cell structure and from the cell structure to the figure information are performed stepwise as described above, so that the drawing stripe to the figure information is developed in a single step as in the conventional case. Compared with the above, extremely high speed processing becomes possible.

Further, not only when the target inspection stripe is covered by one drawing stripe, but also when the target inspection stripe extends over the two drawing stripes 14 and 15, the general development is performed. This can be dealt with by alternately accessing the combination of the circuit 3 and a plurality of data memories.

Since the fourth embodiment has three systems of data memory and pointer memory in addition to the third embodiment, the third inspection stripe 18 shown in FIG. 2 is used. First and second detailed expansion circuits 5 and 3 under inspection
1 is in operation, the general expansion circuit 3 uses the third data memory 44 and the third pointer memory 45,
It is possible to roughly develop the third drawing stripe (not shown). Therefore, this configuration is very effective in avoiding the rate-limiting by the rough expansion processing when the rough expansion processing takes a relatively long time.

(Embodiment 5: Configuration / Operation / Effect) FIG.
It is a schematic block diagram explaining the 5th Example of this invention. FIG. 5 is similar to FIG. 1, FIG. 3 and FIG.
The portion corresponding to the bit expansion circuit 108 and the reference data generation circuit 107 of the pattern inspection apparatus shown in FIG. 4 is shown, and other constituent lamps 101, masks 102, tables 103, photo array sensors 104, sensor circuits 10 are shown.
5, the comparison / determination circuit 106, the design data 109 stored in the storage medium such as the magnetic disk or the magnetic tape, etc. are the same as the conventional ones, and therefore the description and illustration thereof are omitted.

This fifth embodiment is different from the previous embodiment in that
Further, it is characterized in that it has four systems of data memory and three systems of pointer memory. By adopting this configuration, during the period in which the first and second detailed expansion circuits 5 and 31 are inspecting the third inspection stripe 18 shown in FIG. , Third data memory 44
And the third pointer memory 45
It is possible to input and transfer the fourth drawing stripe data (not shown) to the fourth data memory 46 even while the drawing stripe is being developed.

This configuration is effective in avoiding the rate-limiting by the transfer processing time when the data capacity of the drawing stripe data is large and the input transfer to the data memory takes a relatively long time.

(Other Embodiments) Instead of the command for specifying the data memory or pointer memory to be accessed given to the general expansion circuit and the detailed expansion circuit according to the above description, the bus to be connected to the data memory or the pointer memory or A method of instructing each expansion circuit may be adopted.

The description format of the data input to the bit expansion circuit of the present invention according to the above description is a hierarchical structure in which the description of the data occurs even if the drawing method is different, such as the spot beam method and the variable shaped beam method. If so, the effect obtained is the same.

[0094]

According to the pattern inspection apparatus of the present invention, the design data used for mask drawing can be converted into the inspection data in the pattern inspection apparatus. Therefore, the data can be directly input to the pattern inspection apparatus without software data conversion. Is possible. As a result, data conversion time becomes unnecessary,
Since management of pattern inspection data can be omitted, inspection efficiency is improved.

[Brief description of drawings]

FIG. 1 is a schematic configuration block diagram of a main part of a pattern inspection apparatus showing a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a relationship between a drawing stripe and an inspection stripe.

FIG. 3 is a schematic block diagram of a main part of a pattern inspection apparatus showing a second embodiment of the present invention.

FIG. 4 is a schematic block diagram of a main part of a pattern inspection apparatus showing a third embodiment of the present invention.

FIG. 5 is a schematic configuration block diagram of a main part of a pattern inspection apparatus showing a fourth embodiment of the present invention.

FIG. 6 is a schematic block diagram of a main part of a pattern inspection apparatus showing a fifth embodiment of the present invention.

FIG. 7 is a schematic overall block configuration diagram for explaining the configuration of a conventional pattern inspection apparatus.

FIG. 8 is a conceptual diagram showing the relationship between stripes, areas, and figures.

9 is an explanatory diagram showing an example in which the graphic of FIG. 8 is described.

FIG. 10 is an explanatory diagram for explaining types of graphics.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 data memory 2 data memory 3 general expansion circuit (outline expansion means) 4 pointer memory 5 detailed expansion circuit (detail expansion means) 6 graphic image generation circuit 7 inspection stripe cutout information 8 bank in pointer memory 9 bank in pointer memory 10 Bank in pointer memory 11 Inspection stripe cutout information 14 First drawing stripe 15 Second drawing stripe 16 First inspection stripe 17 Second inspection stripe 18 Third inspection stripe 26 cells 27 cells 28 cells 30 Pointer memory 31 Detailed development circuit 40 Pointer memory 43 Arbiter 45 Pointer memory 101 Light source 102 Mask (sample) 103 Table 104 Line sensor (light receiving means) 105 Sensor circuit 106 Comparison judgment circuit 107 Reference data generation circuit 10 8-bit expansion circuit 109 Design data 110 Observation data 111 Inspection standard data

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number in the agency FI Technical indication location H01L 21/66 J 7630-4M (72) Inventor Masao Takanashi Komukai Toshiba-cho, Kawasaki-shi, Kanagawa Prefecture No. 1 Incorporated company Toshiba Research & Development Center

Claims (5)

[Claims] 1. An irradiation unit that irradiates a sample on which a pattern is formed with light, and a light receiving unit that receives transmitted light or reflected light of the light irradiated on the sample and outputs measurement data corresponding to an image of the pattern. And storage means for storing drawing data used for drawing and forming the pattern,
The drawing data is read from this storage means and input,
An inspection for inspecting a pattern formed on the sample by comparing the measurement data and the bit pattern data with a bit expanding unit that creates bit pattern data according to the drawing data based on the drawing data In the pattern inspection apparatus including means, the drawing data comprises a plurality of drawing stripe data having a predetermined stripe width and is stored in the storage means. And a general expanding means for expanding the bit expanding means to expand the data of the upper hierarchical structure forming the drawing stripe data into the data of the lower hierarchical structure, and the general expanding means. The obtained data of the lower hierarchical structure is used as the bit pattern data. Pattern inspection apparatus characterized by being composed of a detailed expansion means for opening process. 2. The bit expanding means obtains the drawing stripe data read from the storage means by temporarily storing the drawing stripe data and outputting the drawing stripe data to the general expanding means, and expanding the data by the general expanding means. 2. The pattern inspection apparatus according to claim 1, further comprising: a pointer memory that temporarily stores information about the data of the lower hierarchical structure that has been stored and that can output the information to the detailed expansion means. 3. A double buffer function is provided, wherein a plurality of the pointer memories are provided, and a write access from the general expansion means to the pointer memory and a read access from the pointer memory to the detailed expansion means can be performed in parallel. The pattern inspection apparatus according to claim 2, wherein: 4. The general expansion means performs the expansion processing from the drawing stripe data read from the data memory and distributes the inspection stripe data to a plurality of inspection stripe data.
A predetermined address of the data memory in which detailed data of the inspection stripe data is described is written in the pointer memory, and the detailed expansion means reads out from the pointer memory for each of the distributed inspection stripe data, and the predetermined address. The pattern inspection apparatus according to claim 2, wherein the pattern memory device is configured to access the data memory corresponding to and to expand the data described at a predetermined address of the data memory. 5. A plurality of detailed expansion means are provided, and a plurality of inspection stripe data expanded by the general expansion means and output to the pointer memory are expanded in parallel by the plurality of detailed expansion means. And output the data to the arbiter. The data expanded in parallel by the detailed expansion means in this arbiter are combined under a predetermined condition and output to the graphic image generating means. The bit pattern data is generated by the graphic image generating means. The pattern inspection apparatus according to claim 2, wherein the pattern inspection apparatus is configured to generate