JPH07241732A - Board material small diameter hole machining method - Google Patents
Board material small diameter hole machining methodInfo
- Publication number
- JPH07241732A JPH07241732A JP3474094A JP3474094A JPH07241732A JP H07241732 A JPH07241732 A JP H07241732A JP 3474094 A JP3474094 A JP 3474094A JP 3474094 A JP3474094 A JP 3474094A JP H07241732 A JPH07241732 A JP H07241732A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- waveform
- application time
- wave
- diameter hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)
- Perforating, Stamping-Out Or Severing By Means Other Than Cutting (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、基板の小径穴加工の切
粉詰まり処理並びに内壁荒れの除去を高速で確実に行う
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for surely carrying out a chip clogging process for small-diameter holes in a substrate and a removal of inner wall roughness at a high speed.
【0002】[0002]
【従来の技術】従来、電子機器の基板材料である両面銅
貼りのガラス繊維入りエポキシ樹脂基板の穴明け加工
は、0.3mm以上の穴を加工することが多く、発生す
る切粉は超音波洗滌などの方法で除去することが普通で
あった。しかし、最近では配線も微細パターン化して、
高密度、多層化となってきており、スルーホール径も
0.25mmから0.1mm程度と細径の穴径となり、
ドリル刃の摩耗、折損などの問題もあって、切粉詰まり
や内壁荒れ、バリ発生が多く、超音波洗滌方法では切粉
排除、内壁荒れやバリ除去は不可能になってきている。2. Description of the Related Art Conventionally, a glass fiber-containing epoxy resin substrate with a double-sided copper coating, which is a substrate material for electronic devices, is often drilled with a hole having a diameter of 0.3 mm or more. It was common to remove it by washing or the like. However, recently, the wiring has been made into a fine pattern,
The density is increasing and the number of layers is increasing, and the diameter of through holes is also small, from 0.25 mm to 0.1 mm.
Due to problems such as wear and breakage of the drill blade, there are many cases in which chips are clogged, the inner wall is roughened, and burrs are generated, and it is becoming impossible to remove chips, roughen the inner wall and remove burrs by the ultrasonic cleaning method.
【0003】又、プラズマ放電を利用する従来の基板汚
れクリーニング方法として、真空容器に基板を中央に入
れ、両側に多数の線状電極を設置し、それに直流電圧を
交互に印加する方法と、交番電圧を印加する方法とあっ
た。直流電圧の場合は数千ボルトであり、交番電圧の場
合は数百サイクルから数メガサイクルまで含まれる。し
かし、これらの場合は、安定なプラズマ放電を発生させ
るのが目的であるため、その真空度は1Torr以下で
あった。この方法の問題点は放電が静かであり、容器内
に含ませた腐食性ガス(フッ化物、塩化物など)のプラ
ズマ放電によるイオン化した反応基により基板中の切り
粉、汚れなどを静かに化学的反応除去するため、可成り
の時間がかかることと切り粉などは容器内では静電気的
に付着したままとなり除去されず、基板汚れクリーニン
グ方法としてはきわめて不十分な方法であった。更に、
本出願人等は、通常のプラズマ放電のような低い真空度
を用いず、10ないし2×103Torr下でプラズマ
放電処理して、被加工基板材料の小径穴を加工する方法
を見い出し、特開平5−285895号として既に出願
している。Further, as a conventional substrate dirt cleaning method using plasma discharge, a method is used in which a substrate is placed at the center in a vacuum container, a large number of linear electrodes are installed on both sides, and a DC voltage is alternately applied to it. There was a method of applying a voltage. In the case of a DC voltage, it is several thousand volts, and in the case of an alternating voltage, several hundred cycles to several megacycles are included. However, in these cases, the degree of vacuum was 1 Torr or less because the purpose is to generate stable plasma discharge. The problem with this method is that the discharge is quiet, and the chips and stains on the substrate can be chemically treated by the ionized reactive groups generated by the plasma discharge of the corrosive gas (fluoride, chloride, etc.) contained in the container. It takes a considerable amount of time to remove by reactive reaction, and chips and the like remain electrostatically attached in the container and are not removed, which is an extremely insufficient method for cleaning the substrate. Furthermore,
The present applicants have found a method of processing a small-diameter hole of a substrate material to be processed by plasma discharge processing under 10 to 2 × 10 3 Torr without using a low degree of vacuum such as usual plasma discharge. An application has already been filed as Kaihei 5-285895.
【0004】これによれば、例えば、アルミナ基板やシ
リコン基板のように耐熱、耐食性の良い材料を用いた基
板の場合は、例えば一般にセラミックスエッチング用と
して使われるフッ化水素系ガス以外に水酸化ナトリウム
や水酸化カリウム水を50〜60℃に温め、アルカリ蒸
気とする。その雰囲気760Torr中で基板穴に対し
てプラズマ放電処理を行うと、従来のフッ素酸エッチン
グよりも3〜4倍も効率良く、細穴壁面のみのエッチン
グができることがわかった。そこで用いられる電圧波形
は正電圧付加τonのみが繰り返し印加されるものであっ
た。このプラズマ放電による加工法は従来法に比べると
格段に優れたものであるが、切粉詰まり、穴内壁面の平
滑化、バリの除去などをより短時間で100%除去する
ための改良の余地があった。According to this, for example, in the case of a substrate using a material having good heat resistance and corrosion resistance such as an alumina substrate or a silicon substrate, sodium hydroxide is used in addition to the hydrogen fluoride gas which is generally used for ceramics etching. And potassium hydroxide water is heated to 50 to 60 ° C. to be alkali vapor. It was found that when the plasma discharge treatment is performed on the substrate hole in the atmosphere of 760 Torr, only the wall surface of the fine hole can be etched three to four times more efficiently than the conventional fluorine acid etching. The voltage waveform used there was such that only positive voltage addition τ on was repeatedly applied. This machining method using plasma discharge is far superior to the conventional method, but there is room for improvement to remove 100% of clogging of chips, smoothing of the inner wall surface of holes, and removal of burrs in a shorter time. there were.
【0005】[0005]
【発明が解決しようとする課題】そこで、本発明では、
小径穴内の切粉処理、内壁面の平滑性、バリの除去など
が短時間でほぼ完全にできる方法を提供せんとするもの
である。Therefore, according to the present invention,
The purpose of the present invention is to provide a method capable of almost completely completing cutting of small diameter holes, smoothing of inner wall surface, removal of burrs and the like.
【0006】[0006]
【課題を解決するための手段】本発明者らは鋭意研究し
た結果、通常のプラズマ放電のような低い真空度を用い
ず、しかも特定の波形の電圧でプラズマ放電処理するこ
とによって、上記課題が解決されることを見出し本発明
に至った。即ち、本発明は以下(1)〜(3)である。 (1)被加工基板材料の両側に電極を配置し、この電極
に正電圧印加時間τonと負電圧印加時間−τonが交互に
繰り返す波形の電圧又は該波形の電圧に直流電圧を重畳
した波形の電圧を印加し気圧10ないし2×103To
rr下でプラズマ放電処理して、被加工基板材料の小径
穴を加工することを特徴とする基板材料の小径穴加工方
法。Means for Solving the Problems As a result of intensive studies by the present inventors, the above-mentioned problems are solved by performing plasma discharge treatment with a voltage of a specific waveform without using a low degree of vacuum as in ordinary plasma discharge. The inventors have found that these problems can be solved and have reached the present invention. That is, the present invention is the following (1) to (3). (1) Electrodes are arranged on both sides of a substrate material to be processed, and a DC voltage is superposed on a voltage of a waveform in which a positive voltage application time τ on and a negative voltage application time −τ on are alternately repeated or a voltage of the waveform. Waveform voltage is applied and atmospheric pressure is 10 to 2 × 10 3 To
A method for processing a small-diameter hole in a substrate material, which comprises processing a small-diameter hole in a substrate material to be processed by plasma discharge treatment under rr.
【0007】(2)被加工基板材料の両側に2極間間隔
0.01〜50mmで電極を配置し、気圧10ないし2
×103Torr下で、正電圧印加時間τonと負電圧印
加時間−τonが交互に繰り返す波形の電圧又は該波形の
電圧に直流電圧を重畳した波形の電圧が、τonと−τon
が交互に繰り返す正弦波、二等辺三角波、方形波、台形
波、鋸歯状波、一般三角波、矩形衝撃波及びこれらに直
流電圧を重畳した波形から選ばれる一種であり、ピーク
電圧は2極間間隔に合せて10Vないし50000Vに
変化させてプラズマ放電処理して、被加工材の小径穴を
加工することを特徴とする基材材料の小径穴加工方法。 (3)処理雰囲気は空気、非酸化性ガス、反応性ガス、
蒸気のいずれかである上記(1)又は(2)項記載の基
板材料の小径穴加工方法。(2) Electrodes are arranged on both sides of the substrate material to be processed with a distance between the two electrodes of 0.01 to 50 mm, and an atmospheric pressure of 10 to 2
Under × 10 3 Torr, the voltage of the waveform in which the positive voltage application time τ on and the negative voltage application time −τ on are alternately repeated or the voltage of the waveform in which the DC voltage is superimposed on the voltage of the waveform is τ on and −τ on.
Is a type selected from alternating sine wave, isosceles triangular wave, square wave, trapezoidal wave, sawtooth wave, general triangular wave, rectangular shock wave, and waveform in which DC voltage is superimposed on these, and the peak voltage is in the interval between two poles. A small-diameter hole drilling method for a base material, characterized in that plasma discharge treatment is performed while changing the total to 10 V to 50,000 V to machine a small-diameter hole in a workpiece. (3) The processing atmosphere is air, non-oxidizing gas, reactive gas,
The method for processing a small-diameter hole in a substrate material according to the above (1) or (2), which is either steam.
【0008】上記(1)〜(3)のように、本発明は、
基板材料の小径穴加工において、特定の圧力下でかつ特
定波形の電圧を印加するプラズマ放電処理が切粉処理、
穴内面の平滑性、バリの除去などに著しい効果があるこ
とを見出すとともに、雰囲気、圧力とピーク電圧を選択
設定することによって所期の目的を達成するものであ
る。本発明においては、気圧の制御は重要で10Tor
r未満では、基板材料の小径穴以外にも沿面放電が生
じ、グロー放電となり、目的とする穴のプラズマ放電処
理効率が悪くなるばかりでなく、プラズマ放電処理の不
必要な箇所まで処理することになってくる。又、2×1
03Torrを超えるとプラズマ放電処理装置の高圧化
に問題が生じると共に放電も生じ難くなる。As described in (1) to (3) above, the present invention is
When processing small-diameter holes in substrate materials, plasma discharge processing that applies a voltage with a specific waveform under a specific pressure is a chip treatment,
It is found that the smoothness of the inner surface of the hole and the removal of burrs are significantly effective, and the intended purpose is achieved by selectively setting the atmosphere, pressure and peak voltage. In the present invention, control of atmospheric pressure is important and 10 Tor
If it is less than r, creeping discharge occurs in addition to small-diameter holes in the substrate material, causing glow discharge, which not only deteriorates the plasma discharge treatment efficiency of the target hole, but also causes the plasma discharge treatment to be performed to unnecessary points. Is coming. Also, 2 × 1
When it exceeds 0 3 Torr, there is a problem in increasing the pressure of the plasma discharge treatment apparatus and it becomes difficult for discharge to occur.
【0009】本願発明において印加される電圧波形は、
前記特開平5−285895号に記載された発明のよう
に、正電圧印加時間τonがある一定の時間毎に繰り返し
印加されるものではなく、正電圧印加時間τonと負電圧
印加時間−τonが交互に繰り返される波形又は該波形の
電圧に直流電圧を重畳した波形のものであって、この点
に発明の最大の特徴を有する。これらの波形の具体例
は、正電圧印加時間τonと負電圧印加時間−τonが交互
に繰り返す正弦波、二等辺三角形、方形波、台形波、鋸
歯状波、一般三角波、矩形衝撃波などである。これらの
波形を図1に示す。図1において、τonは正電圧印加時
間、−τonは負電圧印加時間、Vpは正のピーク電圧、
−Vpは負のピーク電圧を示す。The voltage waveform applied in the present invention is
As in the invention described in JP-A-5-285895, the positive voltage application time τ on is not repeatedly applied every certain time, but the positive voltage application time τ on and the negative voltage application time −τ. It is a waveform in which on is alternately repeated or a waveform in which a direct current voltage is superimposed on the voltage of the waveform, and has the greatest feature of the invention in this respect. Specific examples of these waveforms are a sine wave, an isosceles triangle, a square wave, a trapezoidal wave, a sawtooth wave, a general triangular wave, and a rectangular shock wave, in which a positive voltage application time τ on and a negative voltage application time −τ on alternate. is there. These waveforms are shown in FIG. In FIG. 1, τ on is a positive voltage application time, −τ on is a negative voltage application time, V p is a positive peak voltage,
-V p indicates a negative peak voltage.
【0010】図1(a)は正弦波であり、(b)は二等
辺三角波、(c)は方形波、(d)は台形波、(e)は
鋸歯状波、(f)一般三角波、(g)は矩形衝撃波の典
型例である。本願発明においては、上記のような正電印
加時間τonと負電圧印加時間−τonが交互に繰り返され
る波形に直流電圧Vを重畳した波形の電圧を印加する場
合も含まれる。これらの波形を図2に示す。各記号は図
1の場合と同義である。図2(a)は、正電圧印加時間
τonと負電圧印加時間−τonか交互に繰り返される波形
のピーク電圧Vpより大なる絶対値を有する直流電圧V
を重畳した波形を示す。この場合負電圧印加時間−τon
は現われず、正電圧印加時間τonは無限大となる。
(b),(c)は正の直流電圧を重畳した場合、即ち、
┃+V1┃>┃−V2┃の場合の例であって、(b)の場
合は┃+τon┃>┃−τon┃であり、(c)の場合は┃
+τon┃=┃−τon┃である。(d),(e)は、負の
直流電圧を重畳した場合、即ち、┃+V1┃<┃−V2┃
の場合の例であって、(d)の場合は┃+τon┃<┃−
τon┃であり、(e)の場合は┃τon┃=┃−τon┃で
ある。直流電圧を重畳した波形はこれらに限られず、図
1(b),(d)〜(g)に正又は負の直流電圧を重畳
したものが含まれる。ただし、直流電圧が重畳されるこ
とによって、単にτonとτoffが繰り返されるような、
いわゆるパルス波形は含まれない。FIG. 1 (a) shows a sine wave, (b) an isosceles triangular wave, (c) a square wave, (d) a trapezoidal wave, (e) a sawtooth wave, (f) a general triangular wave, (G) is a typical example of a rectangular shock wave. The present invention includes the case of applying a voltage having a waveform in which the DC voltage V is superimposed on a waveform in which the positive voltage application time τ on and the negative voltage application time −τ on are alternately repeated. These waveforms are shown in FIG. Each symbol has the same meaning as in FIG. FIG. 2A shows a DC voltage V having an absolute value larger than a positive voltage application time τ on and a negative voltage application time −τ on or a peak voltage V p of a waveform which is alternately repeated.
Shows a waveform in which is superimposed. In this case, negative voltage application time-τ on
Does not appear, and the positive voltage application time τ on becomes infinite.
(B) and (c) are when a positive DC voltage is superimposed, that is,
In the case of ┃ + V 1 ┃> ┃-V 2 ┃, in the case of (b) it is ┃ + τ on ┃> ┃-τ on ┃, and in the case of (c) it is ┃
+ Τ on ┃ = ┃ − τ on ┃. (D), (e), when superimposing a negative DC voltage, i.e., ┃ + V 1 ┃ <┃ -V 2 ┃
In the case of (d), ┃ + τ on ┃ <┃−
It is a τ on ┃, a ┃τ on ┃ = ┃τ on ┃ in the case of (e). The waveform on which the DC voltage is superimposed is not limited to these, and includes those in which a positive or negative DC voltage is superimposed on FIGS. 1B, 1D to 1G. However, when the DC voltage is superimposed, τ on and τ off are simply repeated,
So-called pulse waveforms are not included.
【0011】本願発明においては、電極条件も重要で、
まず2極間の間隔は0.01〜50mmの範囲がよい。
0.01mm未満では現在最も薄い基板として超LSI
基板の厚さが0.005mm位であるので、電極間隔は
0.01が限度であり、また電極間隔が50mmを超え
ると電極間のピーク電圧は50000V以上必要となり
基板材料の小径穴が10mm間隔の場合、放電が電極に
近い小径穴のみならず、遠い小径穴に分散するため、プ
ラズマ放電処理効果が半減する。電圧変動率が±2%で
あるから、49000Vが限界である。むしろ現状では
小径穴の間隔は10mm以下であるから最大ピーク電圧
から電極間隔が決まり、50mmが最大間隔である。電
圧波形の正電圧印加時間τonは0.01μs未満では放
電が生じ難くなる。又、20s未満が好ましい。ピーク
電圧が10V未満ではプラズマ放電が発生し難く、生じ
たとしても単発的放電となり極めて不安定で処理効率は
低い。50000Vを超えると多数の小径穴に分散し効
率が低下するのみならず装置の安全性にも問題を生じて
くる。In the present invention, the electrode conditions are also important,
First, the distance between the two poles is preferably in the range of 0.01 to 50 mm.
If it is less than 0.01 mm, it is currently the thinnest substrate as a VLSI
Since the thickness of the substrate is about 0.005 mm, the electrode interval is 0.01, and when the electrode interval exceeds 50 mm, the peak voltage between the electrodes needs to be 50,000 V or more, and the small hole of the substrate material has an interval of 10 mm. In this case, the discharge is dispersed not only in the small-diameter holes close to the electrodes but also in the small-diameter holes distant from the electrodes, so that the plasma discharge treatment effect is halved. Since the voltage fluctuation rate is ± 2%, 49000V is the limit. Rather, at present, the distance between the small diameter holes is 10 mm or less, so the electrode distance is determined from the maximum peak voltage, and 50 mm is the maximum distance. If the positive voltage application time τ on of the voltage waveform is less than 0.01 μs, the discharge is unlikely to occur. Also, it is preferably less than 20 s. When the peak voltage is less than 10 V, plasma discharge is unlikely to occur, and even if it occurs, it is a single discharge, which is extremely unstable and the treatment efficiency is low. If it exceeds 50,000 V, it will be dispersed in a large number of small-diameter holes and the efficiency will be reduced, as well as a problem will occur in the safety of the device.
【0012】処理雰囲気は、空気、例えばAr,He,
N2などの非酸化性ガス例えばCH4,CCl4,C2H2
などの反応性ガス、例えばNaOH水蒸気などの蒸気を
適宜選択して適用する。特に、燃えやすい紙製品の如き
基板については、Ar,N2ガス雰囲気でプラズマ放電
処理すれば好ましい。本発明によるプラズマ放電処理の
メカニズムは必ずしも十分解明されていないが、該プラ
ズマ放電処理と同時にコロナ放電が基板材料の小径穴内
面や表面上に生じ、その放電が多数の線条の沿面コロナ
放電となることで大きな衝撃波が発生し、更に該衝撃波
によって圧力も発生し、切り粉などは飛ばされ、放電に
よる活性化したイオン、電子によって穴内面の汚れも十
分除去されるものと考えられる。The processing atmosphere is air such as Ar, He,
Non-oxidizing gas such as N 2 such as CH 4 , CCl 4 , C 2 H 2
Reactive gas such as, for example, vapor such as NaOH steam is appropriately selected and applied. Particularly, for a substrate such as a paper product which is easily burned, it is preferable to perform plasma discharge treatment in an Ar, N 2 gas atmosphere. Although the mechanism of the plasma discharge treatment according to the present invention has not been sufficiently clarified, at the same time as the plasma discharge treatment, corona discharge occurs on the inner surface or the surface of the small-diameter hole of the substrate material, and the discharge is a surface corona discharge of many filaments. As a result, a large shock wave is generated, pressure is also generated by the shock wave, chips and the like are blown off, and the dirt on the inner surface of the hole is sufficiently removed by the ions and electrons activated by the discharge.
【0013】この点、従来の高真空下の静かなプラズマ
放電処理とは根本的に相違するだけでなく、本発明者ら
による放電が一方向に限られる先行技術と比べても、放
電が正方向と逆方向に繰り返し行われるか、又は一方向
であっても強弱が繰り返されることで放電処理効果が格
段に向上するものである。In this respect, not only is it fundamentally different from the conventional quiet plasma discharge treatment under a high vacuum, but also the discharge is positive compared with the prior art in which the discharge by the present inventors is limited to one direction. The discharge treatment effect is remarkably improved by repeatedly performing the discharge in the opposite direction or by repeating the strength even in one direction.
【0014】[0014]
【実施例】以下、本願発明を実施例を用いて詳しく説明
する。厚さ0.8mm、縦20cm、横30cmの樹脂
基板に、各一枚毎に直径0.25mm、0.2mm、
0.15mmの穴をそれぞれNCボール盤で全面に5m
m間隔で穴明け加工した。穴数は2300穴となった
が、ステップ加工中、0.25mm細径ドリルは139
0穴位から切粉詰まりが著しくなった。0.2mm細径
ドリルでは680穴位から、さらに0.15mm、細径
ドリルでは430穴位から切粉詰まりが著しくなり、穴
内壁荒れ、バリ発生も多くなった。EXAMPLES The present invention will be described in detail below with reference to examples. A resin substrate having a thickness of 0.8 mm, a length of 20 cm, and a width of 30 cm is 0.25 mm in diameter, 0.2 mm in diameter, and 0.2 mm in diameter.
Each hole of 0.15mm is 5m on the whole surface by NC drilling machine.
Drilled at m intervals. The number of holes was 2,300, but during the step processing, 139 was used for the 0.25 mm small diameter drill.
From the 0th hole, the clogging of chips became remarkable. With the 0.2 mm thin drill, from the 680 hole position, 0.15 mm was further increased, and from the 430 hole with the small diameter drill, the chip clogging became remarkable, the inner wall of the hole was roughened, and burrs were frequently generated.
【0015】実施例1 上記基板を用い、0.25mm穴の基板については雰囲
気は空気中、760Torr、2極間間隔は10mmと
して、正電圧印加時間τonが10ms負電圧印加時間
−τonが10msの正弦波を用い、正のピーク電圧は1
1000Vにて、プラズマ放電処理を行った。処理時間
は2300穴を2分でNC移動処理した。その結果、穴
内部の切粉は全くなく、穴内壁面もプラズマ放電により
突出したガラス繊維などや樹脂のめくれ、突出しなどは
溶融酸化などで滑らかとなり、バリも殆どない状態とな
った。0.2mm、0.15mmの穴の基板についても
それぞれ、0.2mmの場合は電極間隔を8mm、正の
ピーク電圧を9000V、又、0.15mmの場合は電
極間隔6mm、正のピーク電圧6000Vの条件とする
こと以外は上記と同様に正弦波で処理した。Example 1 Using the above substrate, for a substrate having a hole of 0.25 mm, the atmosphere is air, 760 Torr, the distance between the two electrodes is 10 mm, the positive voltage application time τ on is 10 ms, and the negative voltage application time −τ on is Use a sine wave of 10 ms, positive peak voltage is 1
Plasma discharge treatment was performed at 1000V. The treatment time was 2300 holes for 2 minutes, and the NC movement treatment was performed. As a result, the inside of the hole was completely free of chips, and the inner wall surface of the hole was smoothed due to melting and oxidation of the glass fibers and resin protruding due to plasma discharge, and the protrusion was smooth, and there was almost no burr. Also for substrates with holes of 0.2 mm and 0.15 mm, the electrode interval is 8 mm and the positive peak voltage is 9000 V when 0.2 mm, and the electrode interval is 6 mm and the positive peak voltage is 6000 V when 0.15 mm. Processing was performed with a sine wave in the same manner as above, except that the condition was set.
【0016】比較例1 比較のために、正電圧印加時間τonが10msのみのパ
ルス波形の電圧を印加する以外は実施例1と同じ放電処
理を行った。その結果、各孔径において、穴内部の切粉
の除去、穴内壁面の状態、バリの除去などに効果があっ
たものの、いずれも実施例1には及ばなかった。図3は
CdS光検出器を使用して、基板穴の光の透過量による
出力電圧をとり、穴内の切粉の除去具合を調べた図であ
る。縦軸は光起電力の電圧を示し、2300個の平均光
透過量に比例した光起電力の電圧である。0.25mm
の場合、穴明けが100%で良好ならば、出力電圧は5
mVとなるが、本発明のプラズマ放電処理方法では5.
0mVで光透過率は100%である。超音波処理の従来
方法では1.4mVで28%であり、τonのみの比較例
1のプラズマ放電処理方法では4.9mVで光透過率は
98%であった。穴径が0.15mmになると、光透過
率は本願発明のプラズマ放電処理の場合98%であるの
に対して、比較例1のプラズマ放電処理では11%に過
ぎないことがわかった。Comparative Example 1 For comparison, the same discharge treatment as in Example 1 was performed except that a voltage having a pulse waveform with a positive voltage application time τ on of only 10 ms was applied. As a result, at each hole diameter, although it was effective in removing chips inside the hole, the state of the inner wall surface of the hole, and removing burrs, none of them were as good as those in Example 1. FIG. 3 is a diagram in which a CdS photodetector is used to obtain an output voltage according to the amount of light transmitted through a substrate hole, and a state of removing chips in the hole is examined. The vertical axis represents the voltage of the photovoltaic power, which is the voltage of the photovoltaic power proportional to the average light transmission amount of 2300 pieces. 0.25 mm
In the case of, if the drilling is 100% and good, the output voltage is 5
Although it becomes mV, in the plasma discharge treatment method of the present invention, it is 5.
The light transmittance is 100% at 0 mV. The conventional method of ultrasonic treatment was 28% at 1.4 mV, and the plasma discharge treatment method of Comparative Example 1 using only τ on was 4.9 mV and the light transmittance was 98%. It was found that when the hole diameter was 0.15 mm, the light transmittance was 98% in the plasma discharge treatment of the present invention, whereas it was only 11% in the plasma discharge treatment of Comparative Example 1.
【0017】実施例2 0.15mmの孔径の上記基板を用い、実施例1と同様
に、正弦波の正電圧印加時間τonと負電圧印加時間−τ
onを変化させた。実施例1では、τonを10ms、−τ
onを10ms、電極間隔6mm、正のピーク電圧600
0Vで98%であったが、τonを1ms、−τonを1m
s、ピーク電圧を8000V、電極間隔は5mmとした
ところ、光透過量が増加して透過率が99%に達した。
さらにτonを10μs、−τonを10μとした結果、1
00%に達したことがわかった。このように、プラズマ
放電処理は、対象物の材質、穴径によって、正電圧印加
時間τon及び負電圧印加時間−τonやピーク電圧と電極
間隔を変え、基板に対して最適条件でプラズマ処理を行
えば、ほぼ100%の細穴内壁処理が高速で、しかも確
実にできた。Example 2 Using the above substrate having a hole diameter of 0.15 mm, as in Example 1, the positive voltage application time τ on and the negative voltage application time τ on of the sine wave were calculated.
It was varied on. In the first embodiment, τ on is 10 ms, −τ
on for 10 ms, electrode spacing 6 mm, positive peak voltage 600
It was 98% at 0 V, but τ on was 1 ms and −τ on was 1 m.
s, the peak voltage was 8000 V, and the electrode interval was 5 mm, the amount of light transmission increased and the transmittance reached 99%.
Furthermore, as a result of setting τ on to 10 μs and −τ on to 10 μ, 1
It turned out that it reached 00%. As described above, the plasma discharge treatment is performed by changing the positive voltage application time τ on, the negative voltage application time −τ on , the peak voltage and the electrode interval according to the material of the object and the hole diameter, and the plasma treatment is performed on the substrate under the optimum conditions. By doing so, almost 100% of the inner wall of the fine holes could be processed at high speed and reliably.
【0018】実施例3 正電圧印加時間τonが10ms、負電圧印加時間−τon
が10msの二等辺三角波、方形波、台形波、鋸歯状
波、一般三角波を用い、又、τonが5ms、電圧無印加
時間τoffが5ms、−τonが5ms、再びτoffが5m
sの矩形衝撃波を用いて、実施例1を繰り返した。いず
れの波形において、光透過量98%以上で、ほぼ完全に
切粉等が除去された。 実施例4 正のピーク電圧は16000V、負のピーク電圧−60
00Vの正弦波を用いた以外は実施例1と同じ条件でプ
ラズマ処理を行った。その結果、光透過量100%で、
完全に切粉等が除去された。Example 3 Positive voltage application time τ on is 10 ms, negative voltage application time −τ on
Is an isosceles triangular wave, a square wave, a trapezoidal wave, a sawtooth wave, or a general triangular wave of 10 ms, τ on is 5 ms, no voltage application time τ off is 5 ms, −τ on is 5 ms, and τ off is 5 m again.
Example 1 was repeated using a rectangular shock wave of s. In any of the waveforms, the chips and the like were almost completely removed when the light transmission amount was 98% or more. Example 4 Positive peak voltage is 16000V, negative peak voltage is -60
Plasma treatment was performed under the same conditions as in Example 1 except that a sine wave of 00V was used. As a result, with 100% light transmission,
The chips etc. were completely removed.
【0019】[0019]
【発明の効果】本発明方法によれば、基板の小径穴加工
における切粉詰まり、穴内壁面の平滑化、バリの除去を
短時間で確実に行うことができる。According to the method of the present invention, chip clogging, smoothing of the inner wall surface of holes, and removal of burrs can be reliably performed in the processing of small-diameter holes in substrates.
【図1】本発明の効果を従来例と対比して穴径と平均光
透過量を光起電力の電圧との関係で試験した結果を示す
グラフである。FIG. 1 is a graph showing the results of testing the effect of the present invention in comparison with the conventional example in terms of the hole diameter and the average light transmission amount with respect to the voltage of the photovoltaic power.
【図2】本発明のプラズマ放電に用いられる各種波形を
示す図。FIG. 2 is a diagram showing various waveforms used in the plasma discharge of the present invention.
【図3】本発明のプラズマ放電に用いられる各種波形を
示す図。FIG. 3 is a diagram showing various waveforms used in the plasma discharge of the present invention.
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成6年6月30日[Submission date] June 30, 1994
【手続補正1】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】0009[Correction target item name] 0009
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【0009】本願発明において印加される電圧波形は、
前記特開平5−285895号に記載された発明のよう
に、正電圧印加時間τonがある一定の時間毎に繰り返し
印加されるものではなく、正電圧印加時間τonと負電圧
印加時間−τonが交互に繰り返される波形又は該波形の
電圧に直流電圧を重畳した波形のものであって、この点
に発明の最大の特徴を有する。これらの波形の具体例
は、正電圧印加時間τonと負電圧印加時間−τonが交互
に繰り返す正弦波、二等辺三角形、方形波、台形波、鋸
歯状波、一般三角波、矩形衝撃波などである。これらの
波形を図1〜7に示す。図1〜7において、τonは正電
圧印加時間、−τonは負電圧印加時間、Vpは正のピー
ク電圧、−Vpは負のピーク電圧を示す。The voltage waveform applied in the present invention is
As in the invention described in JP-A-5-285895, the positive voltage application time τ on is not repeatedly applied every certain time, but the positive voltage application time τ on and the negative voltage application time −τ. It is a waveform in which on is alternately repeated or a waveform in which a direct current voltage is superimposed on the voltage of the waveform, and has the greatest feature of the invention in this respect. Specific examples of these waveforms are a sine wave, an isosceles triangle, a square wave, a trapezoidal wave, a sawtooth wave, a general triangular wave, and a rectangular shock wave, in which a positive voltage application time τ on and a negative voltage application time −τ on alternate. is there. These waveforms are shown in Figure 1-7. 1 to 7 , τ on represents a positive voltage application time, −τ on represents a negative voltage application time, V p represents a positive peak voltage, and −V p represents a negative peak voltage.
【手続補正2】[Procedure Amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】0010[Correction target item name] 0010
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【0010】図1は正弦波であり、図2は二等辺三角
波、図3は方形波、図4は台形波、図5は鋸歯状波、図
6は一般三角波、図7は矩形衝撃波の典型例である。本
願発明においては、上記のような正電印加時間τonと負
電圧印加時間−τonが交互に繰り返される波形に直流電
圧Vを重畳した波形の電圧を印加する場合も含まれる。
これらの波形を図8〜12に示す。各記号は図1〜7の
場合と同義である。図8は、正電圧印加時間τonと負電
圧印加時間−τonか交互に繰り返される波形のピーク電
圧Vpより大なる絶対値を有する直流電圧Vを重畳した
波形を示す。この場合負電圧印加時間−τonは現われ
ず、正電圧印加時間τonは無限大となる。図9,図10
は正の直流電圧を重畳した場合、即ち、┃+V1┃>┃
−V2┃の場合の例であって、図9の場合は┃+τon┃
>┃−τon┃であり、図10の場合は┃+τon┃=┃−
τon┃である。図11,図12は、負の直流電圧を重畳
した場合、即ち、┃+V1┃<┃−V2┃の場合の例であ
って、図11の場合は┃+τon┃<┃−τon┃であり、
図12の場合は┃τon┃=┃−τon┃である。直流電圧
を重畳した波形はこれらに限られず、図2,4〜7に正
又は負の直流電圧を重畳したものが含まれる。ただし、
直流電圧が重畳されることによって、単にτonとτoff
が繰り返されるような、いわゆるパルス波形は含まれな
い。FIG. 1 shows a sine wave, FIG. 2 shows an isosceles triangular wave, FIG. 3 shows a square wave, FIG. 4 shows a trapezoidal wave, and FIG. 5 shows a sawtooth wave .
6 is a general triangular wave, and FIG. 7 is a typical example of a rectangular shock wave. The present invention includes the case of applying a voltage having a waveform in which the DC voltage V is superimposed on a waveform in which the positive voltage application time τ on and the negative voltage application time −τ on are alternately repeated.
These waveforms are shown in Figure 8-12. Each symbol has the same meaning as in FIGS. FIG. 8 shows a waveform in which the positive voltage application time τ on and the negative voltage application time −τ on are superimposed with the DC voltage V having an absolute value larger than the peak voltage V p of the waveform which is alternately repeated. In this case, the negative voltage application time −τ on does not appear, and the positive voltage application time τ on becomes infinite. 9 and 10
Is a positive DC voltage superimposed, that is, ┃ + V 1 ┃> ┃
In the case of −V 2 ┃, in the case of FIG. 9 , ┃ + τ on ┃
> ┃−τ on ┃, and in the case of FIG. 10 , ┃ + τ on ┃ = ┃−
τ on ┃. 11 and 12 show an example in which a negative DC voltage is superimposed, that is, ┃ + V 1 ┃ <┃−V 2 ┃. In the case of FIG. 11 , ┃ + τ on ┃ <┃−τ on ┃,
In the case of FIG. 12 , ┃τ on ┃ = ┃−τ on ┃. The waveform obtained by superimposing a DC voltage is not limited to, positive or FIG 2,4~7 are included those obtained by superimposing a negative DC voltage. However,
By superimposing the DC voltage, simply τ on and τ off
Does not include a so-called pulse waveform that is repeated.
【手続補正3】[Procedure 3]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】0016[Correction target item name] 0016
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【0016】比較例1 比較のために、正電圧印加時間τonが10msのみのパ
ルス波形の電圧を印加する以外は実施例1と同じ放電処
理を行った。その結果、各孔径において、穴内部の切粉
の除去、穴内壁面の状態、バリの除去などに効果があっ
たものの、いずれも実施例1には及ばなかった。図13
はCdS光検出器を使用して、基板穴の光の透過量によ
る出力電圧をとり、穴内の切粉の除去具合を調べた図で
ある。縦軸は光起電力の電圧を示し、2300個の平均
光透過量に比例した光起電力の電圧である。0.25m
mの場合、穴明けが100%で良好ならば、出力電圧は
5mVとなるが、本発明のプラズマ放電処理方法では
5.0mVで光透過率は100%である。超音波処理の
従来方法では1.4mVで28%であり、τonのみの比
較例1のプラズマ放電処理方法では4.9mVで光透過
率は98%であった。穴径が0.15mmになると、光
透過率は本願発明のプラズマ放電処理の場合98%であ
るのに対して、比較例1のプラズマ放電処理では11%
に過ぎないことがわかった。Comparative Example 1 For comparison, the same discharge treatment as in Example 1 was performed except that a voltage having a pulse waveform with a positive voltage application time τ on of only 10 ms was applied. As a result, at each hole diameter, although it was effective in removing chips inside the hole, the state of the inner wall surface of the hole, and removing burrs, none of them were as good as those in Example 1. Figure 13
FIG. 3 is a diagram in which an output voltage depending on the amount of light transmitted through a substrate hole is obtained by using a CdS photodetector to examine the degree of removal of chips in the hole. The vertical axis represents the voltage of the photovoltaic power, which is the voltage of the photovoltaic power proportional to the average light transmission amount of 2300 pieces. 0.25m
In the case of m, if the perforation is 100% and is good, the output voltage is 5 mV, but in the plasma discharge treatment method of the present invention, the light transmittance is 100% at 5.0 mV. The conventional method of ultrasonic treatment was 28% at 1.4 mV, and the plasma discharge treatment method of Comparative Example 1 using only τ on was 4.9 mV and the light transmittance was 98%. When the hole diameter is 0.15 mm, the light transmittance is 98% in the plasma discharge treatment of the present invention, whereas it is 11% in the plasma discharge treatment of Comparative Example 1.
I knew it was nothing more than.
【手続補正4】[Procedure amendment 4]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】図面の簡単な説明[Name of item to be corrected] Brief description of the drawing
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図面の簡単な説明】[Brief description of drawings]
【図1】本発明のプラズマ発電に用いられる波形を示す
図。FIG. 1 is a diagram showing a waveform used for plasma power generation of the present invention.
【図2】本発明のプラズマ放電に用いられる波形を示す
図。FIG. 2 is a diagram showing waveforms used in plasma discharge of the present invention.
【図3】本発明のプラズマ放電に用いられる波形を示す
図。FIG. 3 is a diagram showing waveforms used for plasma discharge of the present invention.
【図4】本発明のプラズマ放電に用いられる波形を示す
図。FIG. 4 is a diagram showing waveforms used for plasma discharge of the present invention.
【図5】本発明のプラズマ放電に用いられる波形を示す
図。FIG. 5 is a diagram showing waveforms used for plasma discharge of the present invention.
【図6】本発明のプラズマ放電に用いられる波形を示す
図。FIG. 6 is a diagram showing waveforms used for plasma discharge of the present invention.
【図7】本発明のプラズマ放電に用いられる波形を示す
図。FIG. 7 is a diagram showing waveforms used for plasma discharge of the present invention.
【図8】本発明のプラズマ放電に用いられる波形を示す
図。FIG. 8 is a diagram showing waveforms used in the plasma discharge of the present invention.
【図9】本発明のプラズマ放電に用いられる波形を示す
図。FIG. 9 is a diagram showing waveforms used for plasma discharge of the present invention.
【図10】本発明のプラズマ放電に用いられる波形を示
す図。FIG. 10 is a diagram showing waveforms used for plasma discharge of the present invention.
【図11】本発明のプラズマ放電に用いられる波形を示
す図。FIG. 11 is a diagram showing waveforms used in the plasma discharge of the present invention.
【図12】本発明のプラズマ放電に用いられる波形を示
す図。FIG. 12 is a diagram showing waveforms used for plasma discharge of the present invention.
【図13】本発明の効果を従来例と対比して穴径と平均
光透過量を光起電力の電圧との関係で試験した結果を示
すグラフである。FIG. 13 is a graph showing the results of testing the effect of the present invention in comparison with the conventional example in terms of the hole diameter and the average light transmission amount with respect to the voltage of the photovoltaic power.
【手続補正5】[Procedure Amendment 5]
【補正対象書類名】図面[Document name to be corrected] Drawing
【補正対象項目名】全図[Correction target item name] All drawings
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図1】 [Figure 1]
【図2】 [Fig. 2]
【図3】 [Figure 3]
【図4】 [Figure 4]
【図5】 [Figure 5]
【図6】 [Figure 6]
【図7】 [Figure 7]
【図8】 [Figure 8]
【図9】 [Figure 9]
【図10】 [Figure 10]
【図11】 FIG. 11
【図12】 [Fig. 12]
【図13】 [Fig. 13]
───────────────────────────────────────────────────── フロントページの続き (72)発明者 大場 和夫 埼玉県東松山市松葉町4丁目2番3号 (72)発明者 嶋 好範 神奈川県川崎市麻生区王禅寺768番地15 (72)発明者 大場 章 埼玉県朝霞市宮戸3丁目12番89号 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuo Oba 4-chome 2-3, Matsuba-cho, Higashimatsuyama-shi, Saitama (72) Inventor Yoshinori Shima 768, Ozenji, Aso-ku, Kawasaki-shi, Kanagawa 15 (72) Inventor Oba Chapter 3-1289 Miyato, Asaka City, Saitama Prefecture
Claims (3)
この電極に正電圧印加時間τonと負電圧印加時間−τon
が交互に繰り返す波形の電圧又は該波形の電圧に直流電
圧を重畳した波形の電圧を印加し気圧10ないし2×1
03Torr下でプラズマ放電処理して、被加工基板材
料の小径穴を加工することを特徴とする基板材料の小径
穴加工方法。1. An electrode is arranged on both sides of a substrate material to be processed,
Positive voltage application time τ on and negative voltage application time −τ on
Are alternately repeated or a voltage of a waveform in which a DC voltage is superimposed on the voltage of the waveform is applied, and the atmospheric pressure is 10 to 2 × 1.
A method for processing a small-diameter hole in a substrate material, which comprises processing a small-diameter hole in a substrate material to be processed by plasma discharge treatment under 0 3 Torr.
01〜50mmで電極を配置し、気圧10ないし2×1
03Torr下で、正電圧印加時間τonと負電圧印加時
間−τonが交互に繰り返す波形の電圧又は該波形の電圧
に直流電圧を重畳した波形の電圧が、τonと−τonが交
互に繰り返す正弦波、二等辺三角波、方形波、台形波、
鋸歯状波、一般三角波、矩形衝撃波及びこれらに直流電
圧を重畳した波形から選ばれる一種であり、正のピーク
電圧は2極間間隔に合せて10Vないし50000Vに
変化させてプラズマ放電処理して、被加工材の小径穴を
加工することを特徴とする基材材料の小径穴加工方法。2. A gap between two poles of 0.
The electrodes are arranged at 01 to 50 mm and the atmospheric pressure is 10 to 2 × 1.
Under 0 3 Torr, the voltage of the waveform in which the positive voltage application time τ on and the negative voltage application time −τ on are alternately repeated or the voltage of the waveform in which the DC voltage is superimposed on the voltage of the waveform is τ on and −τ on. Alternating sine wave, isosceles triangle wave, square wave, trapezoidal wave,
It is a kind selected from a sawtooth wave, a general triangular wave, a rectangular shock wave, and a waveform in which a DC voltage is superimposed on these, and the positive peak voltage is changed to 10V to 50000V according to the interval between the two poles, and plasma discharge processing is performed. A method for forming a small-diameter hole in a base material, which comprises forming a small-diameter hole in a workpiece.
性ガス、蒸気のいずれかである請求項1又は2記載の基
板材料の小径穴加工方法。3. The method for processing a small diameter hole in a substrate material according to claim 1, wherein the processing atmosphere is any one of air, a non-oxidizing gas, a reactive gas, and steam.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6034740A JP2607346B2 (en) | 1994-03-04 | 1994-03-04 | Small hole processing method for substrate material |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6034740A JP2607346B2 (en) | 1994-03-04 | 1994-03-04 | Small hole processing method for substrate material |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH07241732A true JPH07241732A (en) | 1995-09-19 |
JP2607346B2 JP2607346B2 (en) | 1997-05-07 |
Family
ID=12422725
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6034740A Expired - Lifetime JP2607346B2 (en) | 1994-03-04 | 1994-03-04 | Small hole processing method for substrate material |
Country Status (1)
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006078095A1 (en) * | 2005-01-20 | 2006-07-27 | Chang Young Lim | Device and method for controlling the discharge pulse of electric discharge machine drill |
JP2013534868A (en) * | 2010-07-02 | 2013-09-09 | ショット アクチエンゲゼルシャフト | Method and apparatus for making multiple holes in a workpiece |
JP2017518029A (en) * | 2014-04-03 | 2017-07-06 | タンパピエル ゲゼルシャフト ミット ベシュレンクテル ハフツングTannpapier GmbH | Diffusion optimized chipping paper |
US11744015B2 (en) | 2010-07-02 | 2023-08-29 | Schott Ag | Interposer and method for producing holes in an interposer |
Citations (8)
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JPS61197124A (en) * | 1985-02-26 | 1986-09-01 | Oyo Jiki Kenkyusho:Kk | Electro-chemical discharge machine and electro-chemical discharge machining method |
JPS6339725A (en) * | 1986-08-04 | 1988-02-20 | Inoue Japax Res Inc | Electric discharge machining device |
JPS6427812A (en) * | 1987-07-20 | 1989-01-30 | Mitsubishi Electric Corp | Electric discharge machining |
JPH01234115A (en) * | 1988-03-16 | 1989-09-19 | Hitachi Seiko Ltd | Power supply device for spark erosion machining |
JPH01257513A (en) * | 1988-04-08 | 1989-10-13 | Sodick Co Ltd | Electric discharge machine |
JPH03228521A (en) * | 1990-11-17 | 1991-10-09 | Fanuc Ltd | Electric discharge machining method |
JPH05285895A (en) * | 1992-04-07 | 1993-11-02 | Sakae Denshi Kogyo Kk | Processing method of small diameter hole on substrate material |
JPH05331634A (en) * | 1992-05-27 | 1993-12-14 | Asahi Glass Co Ltd | Sputtering device |
-
1994
- 1994-03-04 JP JP6034740A patent/JP2607346B2/en not_active Expired - Lifetime
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS61197124A (en) * | 1985-02-26 | 1986-09-01 | Oyo Jiki Kenkyusho:Kk | Electro-chemical discharge machine and electro-chemical discharge machining method |
JPS6339725A (en) * | 1986-08-04 | 1988-02-20 | Inoue Japax Res Inc | Electric discharge machining device |
JPS6427812A (en) * | 1987-07-20 | 1989-01-30 | Mitsubishi Electric Corp | Electric discharge machining |
JPH01234115A (en) * | 1988-03-16 | 1989-09-19 | Hitachi Seiko Ltd | Power supply device for spark erosion machining |
JPH01257513A (en) * | 1988-04-08 | 1989-10-13 | Sodick Co Ltd | Electric discharge machine |
JPH03228521A (en) * | 1990-11-17 | 1991-10-09 | Fanuc Ltd | Electric discharge machining method |
JPH05285895A (en) * | 1992-04-07 | 1993-11-02 | Sakae Denshi Kogyo Kk | Processing method of small diameter hole on substrate material |
JPH05331634A (en) * | 1992-05-27 | 1993-12-14 | Asahi Glass Co Ltd | Sputtering device |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006078095A1 (en) * | 2005-01-20 | 2006-07-27 | Chang Young Lim | Device and method for controlling the discharge pulse of electric discharge machine drill |
JP2013534868A (en) * | 2010-07-02 | 2013-09-09 | ショット アクチエンゲゼルシャフト | Method and apparatus for making multiple holes in a workpiece |
US11744015B2 (en) | 2010-07-02 | 2023-08-29 | Schott Ag | Interposer and method for producing holes in an interposer |
JP2017518029A (en) * | 2014-04-03 | 2017-07-06 | タンパピエル ゲゼルシャフト ミット ベシュレンクテル ハフツングTannpapier GmbH | Diffusion optimized chipping paper |
US11653694B2 (en) | 2014-04-03 | 2023-05-23 | Tannpapier Gmbh | Method for manufacturing mouthpiece lining paper |
Also Published As
Publication number | Publication date |
---|---|
JP2607346B2 (en) | 1997-05-07 |
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