JPH07240389A - Manufacture of semiconductor device and semiconductor device - Google Patents

Abstract

PURPOSE:To decrease the number of photolithography processes and realize cost reduction, by depositing first conducting material so as to cover the peripheral part of a protruding frame part, etching back the first conducting material, and covering the etched-back first conducting material 'and a dielectric film with second conducting material. CONSTITUTION:A first aperture 21b is formed in an insulating film 20, and a frame part 22a is formed on the side wall of the first aperture 21b. By etching back the whole part of the insulating film 20, a second aperture 21c is formed below the first aperture 21b, and the frame part 22a is made to protrude from the edge end portion of the second aperture 21c. First conducting material 27 is deposited on the insulating film 20 so as to cover the peripheral part of a protruding frame part 22 and be electrically connected with the bottom part of the second aperture 21c. The first conducting material 27 is etched back, and the first conducting material 27 after etched back is covered with a dielectric film 23, which is covered with second conducting material 24.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method and a semiconductor device, and more particularly to a semiconductor device and a manufacturing method thereof which enables high integration of a memory block.

[0002]

2. Description of the Related Art FIG. 33 shows a sectional structure of a memory cell portion of a shield bit line type DRAM in which a bit line is formed before a capacitor. In FIG. 33,
11 is a semiconductor substrate, 12 is an isolation oxide film, 13 is a gate oxide film of a MOS transistor, 14 is a gate electrode to be a word line of DRAM, 15 is a gate electrode overlay oxide film, 16 is a sidewall spacer oxide film, and 17 is Impurity diffusion region, 18 is first
Interlayer oxide film, 19a is a DRAM bit line, 20 is a second interlayer oxide film, 21b is a first contact hole, 21c is a second contact hole, 23 is a capacitor dielectric film, 24 is a capacitor upper electrode, 27a is a capacitor lower electrode.

A method of manufacturing this semiconductor device will be described in the order of steps. (1) Isolation oxide film 12, gate oxide film 1 on semiconductor substrate 11
3, a gate electrode 14 serving as a DRAM word line, an overlay oxide film 15, a sidewall spacer 16, an impurity diffusion region 17,
A first interlayer oxide film 18 and a bit line 19a are formed. (Figure 2
1) (2) After depositing the second interlayer oxide film 20 (FIG. 22), (3) A resist pattern 25 is formed by photoengraving technology (FIG. 23), (4) Using this as a mask Then, the oxide film is etched to form the first contact hole 21b by stopping it halfway without reaching the substrate. (Fig. 24) (5) Remove the resist (Fig. 25), (6) Deposit the oxide film 33 so as to cover the entire surface (Fig. 26), and (7) etch back the entire surface to remove the intermediate oxide film spacer 33a. While forming on the inner wall of the first contact hole 21b (FIG. 27), the second contact hole 21c is formed on the impurity diffusion layer 17 (FIG. 28). (8) Deposit the conductive layer 27 made of conductive polysilicon (FIG. 29). (9) A resist pattern 100 is formed by photolithography (Fig. 30), (10) The conductive layer 27 is processed by etching to form a capacitor lower electrode 27a (Fig. 31) (11) Resist pattern (Figure 32) (12) Capacitor dielectric film 23 and capacitor upper electrode 24
Are deposited to form a DRAM memory cell (FIG. 33). The formation of the contact hole 21c does not depend on the process of photoengraving and etching technology. The contact hole diameter of the current photoengraving technology is such that when misalignment occurs, for example, a gate electrode is formed in the contact hole. Is exposed and there is a high possibility that a short circuit will occur with the upper electrode. Therefore, after forming the contact hole to some extent, forming the oxide film spacer 33a and further etching, the diameter of the contact hole is made smaller than that obtained by only photolithography, and the short circuit due to misalignment is prevented. There is.

[0004]

In recent years, with the high integration of DRAM, the lower electrode is complicated as in the prior art, the number of manufacturing steps is increased, and the manufacturing cost is increased. On the other hand, D
It was said that the number of RAM manufacturing processes cannot be reduced. Also, with the high integration of DRAM, the memory cell area is shrinking while the memory capacity is increasing, and it is required to secure a larger capacity within the same area.

These inventions have been made in order to solve the above problems, and the present invention can reduce the number of photolithography processes during the DRAM manufacturing process and contribute to cost reduction. It is intended to obtain a method for manufacturing a device and a semiconductor device.

Another object of the present invention is to easily increase the surface area of the lower electrode of the capacitor (capacitance of the capacitor), and further to provide a method of manufacturing the same.

[0007]

In a method of manufacturing a semiconductor device according to the present invention, a first conductive material is deposited so as to cover the periphery of a protruding frame portion, and the first conductive material is etched. Then, the etched back first conductive material is covered with a dielectric film and a second conductive material. According to another aspect of the present invention, there is provided a semiconductor device including a first conductive material that surrounds a protruding frame portion and is electrically connected to an opening bottom portion, a dielectric film that covers the first conductive material, and the dielectric material. Second covering the membrane
Made of a conductive material. In a method of manufacturing a semiconductor device according to another invention, the first conductive material deposited so as to cover the periphery of the protruding frame portion is selectively removed, and the selectively removed first conductive material is removed. Cover with a dielectric film and a second conductive material.

[0008]

According to the present invention, the photolithography process can be omitted by covering the periphery of the protruding frame portion with the first conductive material and then performing etch back, and thus the number of processes can be reduced.

In another aspect of the invention, the first conductive material is three-dimensionally formed around the frame portion protruding above the insulating film, so that the first conductive material, the dielectric film and the second conductive material are formed. This brings about an increase in the capacitance of a capacitor made of a conductive material.

[0010]

【Example】

Example 1. 1 to 12 are cross-sectional views showing the steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention. In FIG. 1, 11 is a semiconductor substrate, 12 is an isolation oxide film,
13 is a gate oxide film of a MOS transistor, 14 is a gate electrode, 15 is a gate electrode overlay oxide film, 16 is a sidewall spacer, 17 is an impurity diffusion region, and in FIG.
A bit line of RAM, 21a is a third contact hole, 20 in FIG. 3 is a second interlayer oxide film as an insulating film, 25 in FIG. 4 is a resist pattern, and in FIG.
b is the first contact hole, 22 in FIG. 7 is the conductive layer, and in FIG. 8, 22a is the first of the lower electrode as the frame part.
In FIG. 10, 27 is a conductive layer as the first conductive material, 22b in FIG. 11 is the second part of the lower electrode formed from the first conductive material, and 22c in FIG. The third portion of the lower electrode formed of the first conductive material, in FIG. 12, 23 is the capacitor dielectric film, and 24 is the second
Is an upper electrode of the capacitor as a conductive material of.

A first embodiment will be described below with reference to FIGS. 1 to 12. (1) Isolation oxide film 12, gate oxide film 1 on semiconductor substrate 11
3, a gate electrode 14, an overlay oxide film 15, a sidewall spacer 16, and an impurity diffusion region 17
Form an S-transistor. (FIG. 1) Next, a first interlayer oxide film 18 is deposited so as to cover the MOS transistor, a third contact hole 21a is formed by using an anisotropic etching technique, and then a conductive film is deposited. The bit line 19a is formed by using the photolithography technique and the anisotropic etching technique. (FIG. 2) (2) After depositing the second interlayer oxide film 20 which is an insulating film (FIG. 3), (3) A resist pattern 25 is formed by photolithography (FIG. 4), (4) Is used as a mask to etch the oxide film, and the first contact hole 21b is formed as an intermediate stop without reaching the substrate. (FIG. 5) (5) The resist pattern 25 is removed (FIG. 6), (6) A conductive layer 22 made of polysilicon having a different etching property from the second interlayer oxide film 20 which is an insulating film is deposited,
(FIG. 7) (7) The conductive layer 22 is anisotropically etched to form a first portion 22a of the lower electrode as a frame portion on the inner wall of the first contact hole 21b. (FIG. 8) (8) A second contact hole 21c is formed on the impurity diffusion layer 17 by etching back the entire surface of the oxide film. At this stage, the first portion 22a of the lower electrode comes to project above the second interlayer oxide film 20. (Fig. 9) (9) First to fill the second contact hole 21c
A conductive layer 27 is deposited as the conductive substance of. (Fig. 10) (10) The third portion 22c of the plug-shaped lower electrode completely embedded in the second contact hole 21c inside the first portion 22a of the lower electrode by the anisotropic conductive layer etching technique.
And a second portion of the lower electrode on the outer periphery of the first portion 22a of the lower electrode.
22b are simultaneously formed. (FIG. 11) At this time, the first portion 22a of the lower electrode, the second portion 22b of the lower electrode, the third portion 22c of the lower electrode, and the impurity diffusion region 17 are electrically connected. As described above, the first portion 22a of the lower electrode, the second portion 22b of the lower electrode,
The third portion 22c of the lower electrode serves as the capacitor lower electrode. (11) Thereafter, the capacitor dielectric film 23 and the capacitor upper electrode 24 are formed as the second conductive material, and the semiconductor memory device as shown in FIG. 12 is completed. (Fig. 12)

Example 2. FIG. 13 is a sectional view showing a semiconductor device according to the second embodiment. In FIG. 13, 32a is a nitride film side wall spacer.

Next, a method of manufacturing the semiconductor device according to the second embodiment will be described. Steps (1) to (5) are the same as in Example 1. The steps (6) to (13) are described below from Fig. 14 to Fig.
20 and FIG. 13. In FIG. 14, 32 is a nitride film, 32a in FIG. 15 is a nitride film sidewall spacer as a frame portion, 26 in FIG. 18 is a resist pattern, and in FIG. 19, 27a is a first conductive material.
This is the lower electrode of the capacitor. (6) Deposit the nitride film 32 so as to cover the entire surface. This nitride film has etching characteristics different from those of the second interlayer oxide film 20. (FIG. 14) (7) A sidewall spacer 32a made of a nitride film as a frame is formed on the inner wall of the first contact hole 21b by the anisotropic nitride film etching technique. (FIG. 15) (8) The second contact hole 21c is formed by the anisotropic oxide film etching technique. The nitride film causes the sidewall spacers 32a to have a shape protruding above the second interlayer oxide film 20 to form a protruding frame portion. (Figure 16) (9) Cover the nitride film side wall spacer 32a,
Further, a conductive layer 27 made of polysilicon is deposited as a first conductive material so as to completely fill the second contact hole 21c. (Figure 17) (10) Form the resist pattern 26 by photoengraving technology,
(FIG. 18) (11) An anisotropic conductive layer etching technique is used to form capacitor lower electrode 27a from conductive layer 27 so that adjacent lower electrodes are separated from each other. (FIG. 19) (12) The resist pattern 26 is removed (FIG. 20) (13) Further, the capacitor dielectric film 23 and the capacitor upper electrode 24 as the second conductive material are deposited to complete the semiconductor memory device. (FIG. 13) Instead of the nitride film side wall spacer 32a, a side wall spacer made of conductive polysilicon may be used as the frame portion.

[0014]

As described above, according to the present invention, the photolithography process can be reduced, the number of processes can be reduced, and the manufacturing cost can be suppressed.

Further, although the first conductive material deposited for three-dimensionally depositing the first conductive material is selectively removed in the same pattern as the conventional one,
There is an effect that a larger capacitor capacity can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first step of an embodiment of the present invention.

FIG. 2 is a sectional view showing a first step of an embodiment of the present invention.

FIG. 3 is a sectional view showing a second step of the embodiment of the present invention.

FIG. 4 is a sectional view showing a third step of the embodiment of the present invention.

FIG. 5 is a sectional view showing a fourth step of the embodiment of the present invention.

FIG. 6 is a sectional view showing a fifth step of the embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a sixth step of one embodiment of the present invention.

FIG. 8 is a sectional view showing a seventh step of the embodiment of the present invention.

FIG. 9 is a sectional view showing an eighth step of the embodiment of the present invention.

FIG. 10 is a sectional view showing a ninth step of the embodiment of the present invention.

FIG. 11 is a sectional view showing a tenth step of the embodiment of the present invention.

FIG. 12 is a sectional view showing an eleventh step of the embodiment of the present invention.

FIG. 13 is a thirteenth embodiment of another embodiment of the present invention and another embodiment;
FIG. 6 is a cross-sectional view showing the step of.

FIG. 14 is a sectional view showing a sixth step of another embodiment of the present invention.

FIG. 15 is a sectional view showing a seventh step of another embodiment of the present invention.

FIG. 16 is a sectional view showing an eighth step of another embodiment of the present invention.

FIG. 17 is a sectional view showing a ninth step of another embodiment of the present invention.

FIG. 18 is a cross-sectional view showing the tenth step of another embodiment of the present invention.

FIG. 19 is a sectional view showing an eleventh step of another embodiment of the present invention.

FIG. 20 is a sectional view showing a twelfth step of another embodiment of the present invention.

FIG. 21 is a cross-sectional view showing a first step of the conventional technique.

FIG. 22 is a sectional view showing a second step of the conventional technique.

FIG. 23 is a sectional view showing a third step of the conventional technique.

FIG. 24 is a sectional view showing a fourth step of the conventional technique.

FIG. 25 is a sectional view showing a fifth step of the conventional technique.

FIG. 26 is a sectional view showing a sixth step of the conventional technique.

FIG. 27 is a sectional view showing a seventh step of the conventional technique.

FIG. 28 is a sectional view showing a seventh step of the conventional technique.

FIG. 29 is a sectional view showing an eighth step of the conventional art.

FIG. 30 is a cross-sectional view showing a ninth step of the conventional art.

FIG. 31 is a sectional view showing a tenth step of the conventional technique.

FIG. 32 is a sectional view showing an eleventh step of the conventional technique.

FIG. 33 is a cross-sectional view showing a conventional technique and a twelfth process of the conventional technique.

[Explanation of symbols]

 11 semiconductor substrate 12 isolation oxide film 13 MOS transistor gate oxide film 14 MOS transistor gate electrode 15 gate electrode overlay oxide film 16 sidewall spacer oxide film 17 impurity diffusion region 19a DRAM bit line 20 second interlayer oxide film 21a Third contact hole 21b First contact hole 21c Second contact hole 22 Conductive layer 22a First portion of capacitor lower electrode 22b Second portion of capacitor lower electrode 22c Third portion of capacitor lower electrode 23 Capacitor dielectric Body film 24 Capacitor upper electrode 26 Resist pattern 27 Conductive layer 27a Capacitor lower electrode 32a Nitride film sidewall spacer 33 Oxide film 33a Oxide film side spacer 100 Resist pattern

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 29/78 7514-4M H01L 29/78 301 M

Claims (4)

[Claims] 1. A method of manufacturing a semiconductor memory device including the following steps. (a) a step of forming an isolation oxide film, an impurity diffusion region, a gate oxide film, a gate electrode, and a bit line on a semiconductor substrate; (b) a step of covering the entire surface with an insulating film; A step of forming a first opening; (d) a step of providing a frame portion on the side wall of the first opening; and (e) an etch back of the entire surface of the insulating film to form a second layer below the first opening. Forming an opening, and projecting the frame portion from the edge of the second opening; (f) covering the periphery of the projecting frame portion and electrically connected to the bottom portion of the second opening. Depositing the first conductive material on the insulating film, (g) etching back the first conductive material, and (h) the first conductive material after the etchback. Covering the material with a dielectric film and covering the dielectric film with a second conductive material. 2. The method of manufacturing a semiconductor memory device according to claim 1, wherein the frame portion in step (d) is conductive. 3. The method of manufacturing a semiconductor memory device according to claim 1, wherein in the step (g), the first conductive material is subjected to a photolithography process and then etched. Method. 4. A semiconductor device having an isolation oxide film, an impurity diffusion region, a gate oxide film, a gate electrode, and a bit line, an opening, a frame portion protruding from the opening edge portion, and a periphery of the frame portion. It is characterized by comprising a first conductive substance which surrounds and electrically communicates with the bottom of the opening, a dielectric film which covers the first conductive substance, and a second conductive substance which covers the dielectric film. Semiconductor memory device.