JPH07239675A - Device for driving liquid crystal - Google Patents

Abstract

PURPOSE:To provide a signal control means capable of changing output timing delay time in a certain time without providing an output timing delay of a fixed liquid crystal drive signal. CONSTITUTION:This device is constituted so that a liquid crystal panel 13 is controlled by a segment liquid crystal driving channel output buffer 11 and a common liquid crystal driving channel output buffer 12. A frame signal FR is supplied to respective buffers 11, 12 through a delay signal switch circuit 14 (occasionally, through a delay element D) while switching the extent of the delay with a certain width. Thus, drive timing are dispersed uniformly at the time of viewing in individual channel output buffer. The data are supplied from shift registers 15, 16 to respective output buffers 11, 12 in parallel. The drive signals from respective buffers 11, 12 are outputted to a liquid crystal panel 13 through respective liquid crystal drive signal output terminals 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame signal system circuit of a liquid crystal driving device which is required to have high image quality and high quality.

[0002]

2. Description of the Related Art As a prior art, Japanese Patent Application No. 5-14897
The display data integrated circuit of No. 3 is given. This will be briefly described below. A dynamic liquid crystal drive signal to a matrix type liquid crystal display device (liquid crystal panel) is simultaneously input to a drive buffer circuit, and if a large number of switchings of the buffer circuit output occur at that time, a large switching current is generated and switching noise is large. There is a drawback that As a workaround for this switching noise,
A configuration is provided in which the driving buffers of the plurality of channels are divided into a plurality of groups, and liquid crystal driving signals having a phase shift for each group are received. Its main structure is to provide an operation control signal distribution circuit that provides various timing patterns to the operation control signals for the drive buffer. The operation control signal distribution circuit has a timing adjustment control terminal, and by inputting a signal to this terminal, it is possible to set the display drive timing pattern with a high degree of freedom. As a result, the number of simultaneous switchings of the drive buffer can be reduced to reduce the switching noise per unit time, and moreover, the optimum setting for each display device becomes possible.

However, in the above configuration, the display drive timing pattern is limited to the selected number. Looking at one drive buffer, its operation timing is the repetition of the pattern of the selected timing. In other words, the degree of delay of the liquid crystal drive signal can be adjusted in a fixed pattern. Therefore, the display quality on the liquid crystal panel depends on the specific delay pattern of the adjusted liquid crystal drive signal, and the voltage application to the liquid crystal panel for each liquid crystal drive output may be uneven in time.

[0004]

As described above, in the prior art,
By adjusting the degree of delay of the liquid crystal drive signal with a certain pattern, the voltage application to the liquid crystal panel for each liquid crystal drive output can be uneven in time, which adversely affects the display quality on the liquid crystal panel. There are drawbacks.

The present invention has been made in consideration of the above circumstances, and an object thereof is to reduce switching noise and to disperse the temporal unevenness of voltage application to the liquid crystal panel to display on the liquid crystal panel. An object of the present invention is to provide a liquid crystal driving device that improves the quality.

[0006]

A liquid crystal driving device of the present invention includes a transmission path for transmitting a frame signal for driving a liquid crystal,
Liquid crystal display output means, a plurality of liquid crystal drive buffer means for transmitting liquid crystal drive signals from the transmission path to the liquid crystal display output means, respectively, according to input data and according to the frame signal, and the frame signal drives the liquid crystal Provided on the way of the transmission path to the buffer means,
Signal control means for controlling the liquid crystal drive buffer means so that a plurality of types of delay times are added to the output timing of the liquid crystal drive signal and the liquid crystal drive signal is generated and output at timings where the delays are changed in a time division manner. Is provided.

[0007]

According to the invention, the output timing delay time is changed by a certain time by the signal control means without any liquid crystal drive buffer means having a fixed output timing delay of the liquid crystal drive signal.

[0008]

FIG. 1 is a circuit block diagram showing a main configuration of a liquid crystal driving device according to a first embodiment of the present invention. A segment output liquid crystal driving channel output buffer 11 and a common liquid crystal driving channel output buffer 12 are shown. Is a configuration for controlling the liquid crystal panel 13. The frame signal FR is a delay signal switching circuit
The signal is supplied to each buffer via 14 (may be via the delay element D) while switching the degree of delay with a certain width. As a result, the drive timing is evenly distributed in the individual channel output buffers. Data is supplied from the shift registers 15 and 16 to the output buffers 11 and 12 in parallel. The drive signal from each buffer is output to the liquid crystal panel 13 via each of the liquid crystal drive signal output terminals 17.

FIG. 2 is a circuit diagram showing a delay signal switching circuit, which is an essential part of the present invention, and a peripheral configuration related thereto. Figure 1
The same parts as those in the above are denoted by the same reference numerals. In this example, the delay signal switching circuit 14 has the following configuration. AN
OR gate 14 having two inputs of outputs of D gates 141 and 142
5, OR of which inputs of AND gates 143 and 144 are two inputs
Consists of a gate 146. Each of the AND gates 141 and 143 has a signal that does not pass through the delay element D as one input. AND gates 142 and 144 are delay elements D, respectively.
It has a signal that passes through as one input. Each of the AND gates 142 and 143 has the delay signal switching control signal DSW as one input. AND gates 141 and 144 are the inverted signal / DSW of the delay signal switching control signal DSW, respectively.
Has as one input. The output of the OR gate 145 is an odd number (121, 123,
125, ... 12 (2n-1)), and the output of the OR gate 146 is an even number (122,
Drive control of 124, 126, ... 12 (2n)).

FIG. 3 shows each channel output buffer 121 of FIG.
FIG. 11 is a waveform diagram showing drive timings of 12 (2n-1). First
The liquid crystal drive signal of the channel output buffer 121 is configured to have no delay when the delay signal switching control signal DSW is at "L" level and to have a delay when it is at "H" level. Further, the liquid crystal drive signal of the second channel output buffer 122 is configured such that there is a delay when the delay signal switching control signal is at "L" level and no delay when it is at "H" level. The same applies to the odd-numbered and even-numbered channel output buffers, and the delay timing of the output buffer itself is not fixed by switching the signal DSW.

FIG. 4 is a circuit diagram showing a delay signal switching circuit showing a main structure according to the second embodiment of the present invention and a peripheral structure related thereto. The same parts as those in FIG. 2 are designated by the same reference numerals. A delay signal switching control circuit 18 is provided so that the delay signal switching control signal DSW can be generated by the internal clock CK and the frame signal FR. The delay signal switching control circuit 18 uses two D-type flip-flop circuits 181, 182. The Q input of the flip-flop circuit 181 is the frame signal FR, and the CK input is the shift clock of the shift register 16. The D output of the flip-flop circuit 181 becomes the CK input of the flip-flop circuit 181, the / D output is the Q input, and the D output is the delay signal switching control signal DSW.
become.

FIG. 5 shows each channel output buffer 121 to 12 (2n-1) corresponding to the timing waveform of each part of the circuit having the configuration of FIG.
It is a waveform diagram showing the drive timing of. Basically Fig. 3
Similar to the first channel output buffer 12
The liquid crystal drive signal 1 has no delay when the delay signal switching control signal DSW is at "L" level, and has a delay when it is at "H" level. Further, the liquid crystal drive signal of the second channel output buffer 122 is configured such that there is a delay when the delay signal switching control signal is at "L" level and no delay when it is at "H" level. The same applies to the odd-numbered and even-numbered channel output buffers.
The switching of the output buffer does not fix the delay timing of the output buffer itself.

FIG. 6 is a circuit diagram showing a delay signal switching circuit showing a main structure according to the third embodiment of the present invention and a peripheral structure related thereto. In this example, the delay signal switching circuit 14 is configured to divide its drive timing into three. That is, the OR gate 1420 and the AND gates 1414, 141 which receive the outputs of the AND gates 1411, 1412, 1413 as three inputs.
OR gate 1421 that outputs 5 and 1416 as three inputs, AND
It is composed of an OR gate 1422 which receives the outputs of the gates 1417, 1418 and 1419 as three inputs. AND gates 1411, 1414, 1417
Each has a switching control signal DSW1 as a control input and a signal not passing through the delay element D2 as one input. Each of the AND gates 1412, 1415, 1418 has a switching control signal DSW2 as a control input, and has a signal via the delay element D1 as one input. AND gate
Each of 1413, 1416, and 1419 has a switching control signal DSW3 as a control input and a signal via a delay signal D2 as one input.

The switching control signals DSW1 to 3 are periodically changed by the delay signal switching control circuit 19 so that the switching control can be performed periodically. The output of the OR gate 1420 drives and controls the (2n-1) th row of the channel output buffer 12. The output of the OR gate 1421 is the channel output buffer.
The (2n) th row of the 12 rows is drive-controlled. OR gate 14
The output of 22 is (2n +
1) Drive control is performed (n = 1,2,3 ...).

According to the configuration of each of the above-described embodiments, the delayed liquid crystal drive signal can be periodically switched, so that the liquid crystal drive terminal is applied to the liquid crystal panel for each liquid crystal drive terminal caused by the presence or absence of delay as in the conventional case. It is possible to disperse the temporal unevenness of the voltage. It is known that the reaction time of the liquid crystal is generally several tens of μs. However, by setting the switching cycle time of the delay signal switching control signal in the present invention to be faster than the reaction time of the liquid crystal, a liquid crystal display device ( A high-quality liquid crystal display that does not have a visual effect on the panel) is possible.

Further, since switching noise is drastically reduced, it can be a countermeasure against malfunction which is very compatible with the liquid crystal display device. The liquid crystal display device has a large number of liquid crystal drive signal output terminals (17) (8 to 300 outputs), which will be further increased in the future. Further, the signal receiving unit (I / O system) from the outside and the control system have a low voltage (about 1.5 to 6.0 V), while the liquid crystal drive system has a voltage equal to or higher than the control system (1.5 to 6.0 V). It is operated at about 60V). The control system has a low power consumption, so that the voltage is lower, and the liquid crystal drive system has a higher voltage because of higher image quality. In such a trend, switching noise when the liquid crystal drive system operates causes malfunction of the control system. According to the present invention, while eliminating the switching noise, the temporal unevenness of the liquid crystal drive applied voltage due to the delay is dispersed to achieve high image quality. In each of the above embodiments, the timing of the liquid crystal drive signal is divided into three, but the present invention is not limited to this, and the same effect can be obtained by further dividing the degree of delay.

[0017]

As described above, according to the present invention,
Since the delayed liquid crystal drive signal can be periodically switched, it is possible to disperse the temporal unevenness of the voltage applied to the liquid crystal panel for each liquid crystal drive terminal caused by the presence or absence of the delay as in the conventional case. As a result, it is possible to provide a liquid crystal driving device capable of not only eliminating switching noise but also visually displaying a liquid crystal with high display quality.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a main configuration of a liquid crystal drive device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a delay signal switching circuit which is a main part of the present invention and a peripheral configuration related thereto.

FIG. 3 is a diagram showing the output buffers 121 to 12 (2n-1) of the respective channels of FIG.
FIG. 6 is a waveform diagram showing the drive timing of FIG.

FIG. 4 is a circuit diagram showing a delay signal switching circuit showing a main part configuration according to a second embodiment of the present invention and a peripheral configuration related thereto.

5 is a waveform diagram showing the drive timing of each channel output buffer 121 to 12 (2n-1) with respect to the timing waveform of each part of the circuit of the configuration of FIG.

FIG. 6 is a circuit diagram showing a delay signal switching circuit showing a main part configuration according to a third embodiment of the present invention and a peripheral configuration related thereto.

[Explanation of symbols]

11, 12 ... Channel output buffer for driving liquid crystal, 13 ... Liquid crystal panel, 14 ... Delay signal switching circuit, 15, 16 ... Shift register, 17 ... Liquid crystal driving signal output terminal, 18 ... Delay signal switching control circuit.

Claims (7)

[Claims] 1. A transmission path for transmitting a frame signal for driving a liquid crystal, a liquid crystal display output means, and a liquid crystal drive signal in accordance with input data from the transmission path to the liquid crystal display output means. A plurality of liquid crystal drive buffer means for transmitting the liquid crystal drive signal, and a plurality of types of delay times are added to the output timing of the liquid crystal drive signal, the frame signals being provided on the way of the transmission path to the liquid crystal drive buffer means. A liquid crystal drive device, comprising: a signal control means for controlling the liquid crystal drive buffer means so as to generate and output the liquid crystal drive signal at a timing when the delay changes in a time division manner. 2. The signal control means switches and gives the timing at which the delay changes in a predetermined cycle for each of the liquid crystal drive buffer means classified.
The liquid crystal driving device described. 3. The liquid crystal drive device according to claim 1, wherein the change in the delay timing of the liquid crystal drive signal is synchronized with the switching timing of the input data. 4. The liquid crystal drive buffer means is classified into odd-numbered and even-numbered buffer arrangements with respect to the output timing of the liquid crystal drive signal, and the timing at which the delay is changed by the signal control means is classified. 4. The liquid crystal drive device according to claim 2, wherein the liquid crystal drive buffer means is switched and provided at a predetermined cycle with an actual delay. 5. The liquid crystal drive buffer means is classified into three or more with respect to the output timing of the liquid crystal drive signal, and the timing at which the delay is changed by the signal control means is classified into each of the liquid crystal drive buffer means. 4. The liquid crystal drive device according to claim 2, wherein the liquid crystal drive device is switched by a predetermined cycle with an actual delay. 6. The signal control means includes a delay signal switching circuit which has paths having different delay times in frame signal transmission and logically switches by a control signal. LCD drive device. 7. The signal control means includes a delay signal switching circuit which has paths with different delay times in frame signal transmission and which is logically switched by a control signal, and the delay signal switching circuit is operated to operate the delay signal switching circuit. 7. A delay signal switching control circuit for generating a delay signal switching control signal using a clock signal for fetching the frame signal and the input data is provided in a stage preceding the switching circuit. Or a liquid crystal driving device as described above.