JPH07235877A - Variable length code packing device - Google Patents

Abstract

PURPOSE:To provide the variable length code packing device in which it is not required to modify a code to a serial one once and synchronization of packing with one clock is feasible. CONSTITUTION:The device is provided with an adder section 101 adding length of received signals to calculate a total length, a delay section 102 delaying the total length by one clock cycle to generate delayed data, and a multiplexer section 103 applying barrel shift to the received codes to generate rearranged data, and also with a control section 104 receiving the total length and the delayed data and generating 1st and 2nd control signals 1,2, a 2-stages of flip- flop section 105 storing tentatively the rearranged data based on the 1st control signal and a selection section selecting one of the data stored in the 2-stages of flip-flop section 105 based on the 2nd control signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packing device for packing variable length codes into a fixed length.

[0002]

2. Description of the Related Art Generally, Huffman coding, which is a typical data compression method, is a method of coding from the appearance probability of data. By assigning it, the entropy value of the data can be approached infinitely.

Coding in which the code length changes in this way is called variable length coding. Because of its superiority, conventionally, there are many encoding methods that make extensive use of Huffman codes. For example, MH, MR, MMR, and ADCT are also variable-length codes.

By the way, such a variable-length code must be finally packed to a constant bit depth, but in order to realize it, the code is taken out bit by bit and packed in a container. , It was output when it was collected. In other words, the parallel thing was once converted to serial and then made parallel again.

[0005]

However, the above-mentioned conventional method has a drawback that the processing speed becomes slow.

Since it takes time to convert a code output in parallel in one clock to serial, it is necessary to stop the next code.

It is possible to use a clock having a higher frequency, serialize the clock using the clock, and output the code with an ordinary clock. However, if different clocks are used, it becomes difficult to achieve synchronization. Not feasible.

It is an object of the present invention to provide a variable-length code packing device which does not need to serialize a code once and can perform packing in synchronization with one clock.

[0009]

SUMMARY OF THE INVENTION The present invention comprises an adding means for adding input code lengths to calculate a total length, and a delay means for delaying the total length by one clock cycle to create delay data. Multiplexer means for barrel shifting the input code and rearranging to create data,
Control means for inputting the total length and the delay data to generate a first control signal and a second control signal 2, and a two-stage flip-flop for temporarily storing the rearranged data based on the first control signal. By having the switching means and the selecting means for selecting one of the data stored in the two-stage flip-flop means based on the second control signal, it is not necessary to serialize the code.
Packing in synchronization with one clock is possible.

[0010]

1 is a block diagram showing the structure of a packing device according to an embodiment of the present invention.

In this embodiment, the PLD is used as the control signal output means, and the code to be handled has a maximum length of 8 bits.

The adder 101 receives an input code length (le
n [2. ． 0]) and the previous total code (pad
[2. ． 0]) and the total code (nad
[3. ． 0]) is output.

The delay unit 102 stores the total code (nad [3..0]) output from the adder 101 in synchronization with the clock, delays the clock by one clock, and pads [2. ．
0] and valid are output.

The barrel shift unit 103 rearranges the input code (code [7..0]) under the control of the output data (pad [2..0]) from the delay unit 102, and rcode [7]. ． ． 0] is output.

A PLD (Programmable Logic Device) 104 outputs the output (nad) from the adder 101.
[2. ． 0]) and the output from the delay unit 102 (pad
[2. ． 0]) as input, and the first control signal (we
[7. ． 0]) and the second control signal (sel [7 ..
1]) is output.

The two-stage flip-flop unit 105 outputs the output (rcode [7 ... 0]) from the barrel shift unit 103.
, And outputs the data (packed [7..0]) packed under the control of the first control signal (we [7..0]) and the second control signal (sel [7..1]). .

FIG. 2 is a block diagram showing the configuration of the two-stage flip-flop unit 105.

The first control signal (we [7..0]) is a write enable signal which controls each flip-flop, and when this write enable signal is HIGH,
Each flip-flop is writable and L
When OW, each flip-flop cannot be written.

The second control signal (sel [7..1]) is a select signal for controlling the selector (multiplexer) 203. When this is HIGH, the selector 203 selects the output 2a from the flip-flop group 202 at the back. Then L
At OW, the selector 203 selects the output 2b from the front flip-flop group 201.

The front flip-flop group 201 is the first
Rc input by control of control signal (we [7 ... 0])
ode [7. ． 0] is stored. The flip-flop group 202 in the back is the output 2 of the front flip-flop group 201 which is input by the control of the first control signal (we [7 ... 0]).
b [7. ． 0] is stored.

The multiplexer 203 inputs the output 2a from the back flip-flop and the output 2b from the front flip-flop group, and inputs sel [7. ． 0] control to select either one and output.

FIG. 3 is a table showing the operation contents of PDL.

In the figure, the horizontal axis is pad and the vertical axis is nad.
Is. The upper half of each table is we7, we6 from the left.
We5, we4, we3, we2, we1, and we0 are shown. On the other hand, the lower half is sel from the left.
7, sel6, sel5, sel4, sel3, sel
2 and sel1 are shown.

In the table, the bit value corresponding to sel0 is also shown, but it is understood that it is not necessary because it is always 0. Also, the hatched lines indicate that the condition does not exist or is not necessary.

Here, we [7. ． 0] is output according to the input pad and nad. For example, pad =
4, when nad = 7, we [7. ． 0] is “0001
110 ".

On the other hand, sel [7. ． 1] is the result of delaying the result calculated according to the input pad and nad with the clock.

For example, when pad = 5 and nad = 10,
sel [7. ． 1] is “110000”, a value obtained by delaying it by 1 clock is output from the PDL.

Next, the concrete calculation formula is that AND is AND, #
Is an OR, we7 = (pad == 0) # (nad
≧ 9), we6 = ((1 ≧ pd) & (nad ≧ 2)) #
(Nad ≧ 10), and so on.

On the other hand, sel_reg. d is the input of the flip-flop, sel_reg. Let q be the output of the flip-flop, sel7 = sel_reg7. q, se
l_reg7. d = (nad2 == 0) & (nad1 =
= 0) & (nad0 == 0).

It can be realized by such a formula. In this embodiment, sel is created by referring to only the lower 3 bits of nad.

FIG. 4 is a waveform diagram of sample data in this embodiment.

Reference numeral 401 is a clock, and the other circuits are synchronized with the rising edge of the clock 401.

Reference numeral 402 denotes an input 3-bit code length (l
en [2. ． 0]), and the operation of the block diagram of FIG. 1 when input in this order will be described.

First, as an initial state, pad [2. ．
0] is 0.

There, the first data len [2. ． 0]
When = 2 is input, the adder 101 adds pad and len and outputs nad = 2.

On the other hand, the barrel shifter unit 103 receives the input code code [7. ． 0] to pad [2. ． 0], but the pad [2. ． 0] is 0, so rcode7 = code7, rcode6 = c
The output is ode6 .... This is shown at 409 in FIG. The number (76543210) in the figure is co
Indicates the bit number of de.

The PDL 104 has pad = 0 and nad = 2.
By inputting we [7. ． 0] as “1100000
0 "is output.

On the other hand, sel [7. ． 1] is nad = 2
Therefore, “1100000” is input to sel_reg (because the upper 1 bit is not referred to). Then, at the next rising edge of the clock, it is stored in the internal flip-flop of the PDL 104 and "1100000" is output.

Pad [2. ． 0] 404 is nad
[3. ． 0] is the output of the flip-flop that latches the lower 3 bits (nad [2..0]), so that pad = 2 in synchronization with the rising edge of the next clock.

The valid 407 is the nad [3. ． 0]
Since it becomes the output of the flip-flop that latches the upper 1 bit (nad3) of, the valid = 0 becomes in synchronization with the rising edge of the next clock.

Reference numeral 408 shows an image of a two-stage flip-flop, and the portion indicated by a check (oblique lattice network) indicates that rcode is stored in the portion where the we signal is HIGH. The stripe (diagonal stripe) portion indicates that valid data has already been written.

Then, here, rcode7 (= co
de7) and rcode6 (= code6) were stored in a two-stage flip-flop (point 411 in the figure).

Next, the second data len [2. ． 0] =
When 1 is input, the adder 101 adds pad and len, and outputs nad = 3.

On the other hand, the barrel shifter unit 103 receives the input code code [7. ． 0] to pad [2. ． 0], but the pad [2. ． 0] is 2, rcode7 = code1, rcode6 = c
ode0, rcode5 = code7, rcode4 =
code6, rcode3 = code5, rcode2
= Code4, rcode1 = code3, rcode
0 = output code2

This is shown at 409 in FIG. The numeral (10765432) in the figure indicates the bit number of the code.

The PDL 104 has pad = 2 and nad = 3.
By inputting we [7. ． 0] as “00100000
0 "is output.

On the other hand, sel [7. ． 1] is nad = 3, so “1110,000” is input to sel_reg (because the upper 1 bit is not referred to). Then, at the next rising edge of the clock, the data is stored in the internal flip-flop of the PDL 103 and "1110,000" is output.

Pad [2. ． 0] 404 is nad
[3. ． 0] is the output of the flip-flop that latches the lower 3 bits (nad [2..0]), so that pad = 3 in synchronization with the rising edge of the next clock.

The valid 407 is the nad [3. ． 0]
Since it becomes the output of the flip-flop that latches the upper 1 bit (nad3) of, the valid = 0 becomes in synchronization with the rising edge of the next clock.

At point 412 of 408, rcode5 (=
The code 7) is newly stored in a two-stage flip-flop.

Next, the third data len [2. ． 0] =
When 4 is input, the adder 101 adds pad and len, and outputs nad = 7.

On the other hand, the barrel shifter unit 103 receives the input code code [7. ． 0] to pad [2. ． 0], but the pad [2. ． 0] is 3, rcode7 = code2, rcode6 = c
ode1, rcode5 = code0, rcode4 =
code7, rcode3 = code6, rcode2
= Code5, rcode1 = code4, rcode
7 = output code3.

This is shown in 409. The number (21076543) in the figure shows the bit number of the code.

The PDL 104 has pad = 3 and nad = 7.
By inputting we [7. ． 0] as “0001111
0 "is output.

On the other hand, sel [7. ． 1] is nad = 7
Therefore, “1111111” is input to sel_reg (because the upper 1 bit is not referred to). Then, at the next rising edge of the clock, it is stored in the internal flip-flop of the PDL 104 and "1110,000" is output.

Pad [2. ． 0] 404 is nad
[3. ． 0] is the output of the flip-flop that latches the lower 3 bits (nad [2..0]), so that pad = 7 in synchronization with the rising edge of the next clock.

The valid 407 is the nad [3. ． 0]
Since it becomes the output of the flip-flop that latches the upper 1 bit (nad3) of, the valid = 0 becomes in synchronization with the rising edge of the next clock.

As shown at 413 of 408, rco
de4 (= code7), rcode3 (= code
6), rcode2 (= code5), rcode1
(= Code4) is newly stored in the two-stage flip-flop.

Next, the fourth data len [2. ． 0] =
When 4 is input, the adder 101 adds pad and len, and outputs nad = 11.

On the other hand, the barrel shifter section 103 receives the input code code [7. ． 0] to pad [2. ． 0], but the pad [2. ． 0] is 7, rcode7 = code6, rcode6 = c
ode5, rcode5 = code4, rcode4 =
code3, rcode3 = code2, rcode2
= Code1, rcode1 = code0, rcode
0 = output code7.

The state is shown at 409. The number (65432107) in the figure shows the bit number of the code.

The PDL 104 has pad = 7 and nad = 1.
1 and input we [7. ． 0] as “1110,000
1 ”is output.

On the other hand, sel [7. ． 1] is nad = 1
Since it is 1, “1110,000” is input to sel_reg. Then, at the next rising edge of the clock, P
The value is stored in the internal flip-flop of the DL, “111000”.
0 "is output.

Pad [2. ． 0] 404 is nad
[3. ． 0] is the output of the flip-flop that latches the lower 3 bits (nad [2..0]), so that pad = 3 in synchronization with the rising edge of the next clock.

The valid 407 is the nad [3. ． 0]
Since the upper 1 bit (nad3) of the above is output from the flip-flop latched, valid = 1 in synchronization with the next rising edge of the clock.

As indicated by point 414 in 408, rco
de0 (= code7), rcode7 (= code
6), rcode6 (= code5), rcode5
(= Code4) is newly stored in the two-stage flip-flop.

Also, for the first time at the next clock, v
The alid becomes “1” (point 421 in the figure).

The circled portion of the image of the 408 two-stage flip-flop at that time is sel [7. ． 1] and output from the two-stage flip-flop unit 105, it indicates that the data is valid data. Therefore, the circled portion is the packed data (packed [7..0]) (414 in the figure).

Next, the fifth data len [2. ． 0] =
When 5 is input, the adder 101 adds pad and len, and outputs nad = 8.

On the other hand, the barrel shifter section 103 receives the input code code [7. ． 0] to pad [2. ． 0], but the pad [2. ． 0] is 3, rcode7 = code2, rcode6 = c
ode1, rcode5 = code0, rcode4 =
code7, rcode3 = code6, rcode2
= Code5, rcode1 = code4, rcode
0 = output code3

This is shown in 409. The number (21076543) in the figure shows the bit number of the code.

The PDL 104 has pad = 3 and nad = 8.
By inputting we [7. ． 0] as “0001111
1 ”is output.

On the other hand, sel [7. ． 1] is nad = 8
Therefore, “0000000” is input to sel_reg. Then, at the next rising edge of the clock, PD
Stored in the internal flip-flop of L104,
0000 "is output.

Pad [2. ． 0] 404 is nad
[3. ． 0] is the output of the flip-flop that latches the lower 3 bits (nad [2..0]), so that pad = 0 is set in synchronization with the rising edge of the next clock.

The valid 407 is the nad [3. ． 0]
Since the upper 1 bit (nad3) of the above is output from the flip-flop latched, valid = 1 in synchronization with the next rising edge of the clock.

As indicated by point 415 of 408, rco
de4 (= code7), rcode3 (= code
6), rcode2 (= code5), rcode1
(= Code4), rcode0 (= code3) to 2
Newly stored in the stage flip-flop.

Here again, the next clock is valid.
Becomes "1" (422 in the figure). 2 of 408 at that time
The circled part in the image of the stage flip-flop is s
el [7. ． 1] and output from the two-stage flip-flop unit 105, it indicates that the data is valid data. Therefore, the data indicated by the circle is packed data (packed).
[7. ． 0]).

Similarly, according to 402 in FIG.
[2. ． 0] and code [7. ． [0] is input, variable length codes randomly following 2, 1, 4, 4, 5, 1, 3, 2, 3, ... Are neatly packed and output. The output is valid only when valid is 1.

Although the maximum length of the variable length data is set to 8 in the above embodiments, it is obvious that the present invention is not limited to this and can be easily applied to 16 or 6, for example.

Further, in the above embodiment, the PDL is used as the means for outputting the control signal, but it may be created by using TTL, and there are various other methods.

Further, as shown in FIG. 5, two-stage flip-flop means may be constructed. In this case, sel
And valid are directly output without delay. In this case, after valid = HIGH, it is necessary to pass the data written in the front FF next.

[0082]

As described above, according to the present invention,
Addition means for adding the input code lengths to calculate the total length, delay means for delaying the total length by one clock cycle to create delay data, and barrel-shifting the input codes for rearranging data. Multiplexer means for creating, control means for inputting the total length and the delay data to generate a first control signal and a second control signal 2, and the rearrangement data based on the first control signal. A two-stage flip-flop means for storing the data;
By having one of the data stored in the flip-flop means of the stage selected based on the second control signal, the packing data is synchronized with the system clock without stopping the next code. There is an effect that it is possible to output.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a two-stage flip-flop unit of the above embodiment.

FIG. 3 is a table showing operation contents of the PDL of the above embodiment.

FIG. 4 is a waveform diagram of sample data in the above embodiment.

FIG. 5 is a block diagram showing another embodiment of the present invention.

[Explanation of symbols]

 101 ... Adder, 102 ... Delay unit, 103 ... Barrel shift unit, 104 ... PLD, 105 ... Two-stage flip-flop unit.

Claims (1)

[Claims] 1. Addition means for adding input code lengths to calculate total length; delay means for delaying the total length by one clock cycle to create delay data; barrel-shifting input codes. Multiplexer means for creating rearrangement data by the above; control means for inputting the total length and the delay data to generate a first control signal and a second control signal 2; the rearrangement data for the first control Two-stage flip-flop means for temporarily storing based on a signal; and selecting means for selecting one of the data stored in the two-stage flip-flop means based on the second control signal. Characteristic variable length code packing device.