JPH07235834A - Fm demodulation circuit - Google Patents

Abstract

PURPOSE:To provide the FM demodulation circuit formed to be an integrated circuit. CONSTITUTION:The circuit is provided with a biquad filter 182 comprising operational amplifiers A1-A3, resistors R1-R6, and capacitors C1, C2, a multiplier circuit 181 multiplying an input FM signal S16 with an output signal of the biquad filter 182 and a low pass filter 183 receiving an output signal of the multiplier circuit 181. Then the biquad filter 182 receives an input FM signal S16 and has a phase shift characteristic shifting a phase of pi/2 to the input FM signal S16 at a center frequency fc of the input FM signal S16 and extracts an FM demodulation signal of the input FM signal S16 from the low pass filter 183.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FM demodulation circuit used for mobile phones and the like.

[0002]

2. Description of the Related Art In an analog cellular type mobile telephone, for example, the E-TACS type, a frequency band of downlink channels: 917.0125 to 950.0125 MHz, a frequency interval of channels is 12.5 kHz.

For this reason, the receiving circuit of the E-TACS type mobile phone is constructed in the double superheterodyne system as shown in FIG. 4, for example. That is, FIG.
At the downlink FM signal S11 from the base station
The (frequency f11) is received by the antenna 11, and the received signal S11 is supplied to the first mixer circuit 14 through the high-frequency amplifier 12 and the bandpass filter 13 having the passbands of all the downstream channels. In addition, PLL2
From 1, the oscillation signal S21 of the frequency f21 corresponding to the channel used for the call is taken out, and this oscillation signal S21 is supplied to the mixer circuit 14 as the first local oscillation signal.

Thus, the received signal S11 is transmitted to the mixer circuit 1
At 4, the frequency f14 is frequency converted into a first intermediate frequency signal S14 of f14 = f21-f11 = 55 MHz.

Then, the first intermediate frequency signal S14 is supplied to the second mixer circuit 16 through the first intermediate frequency circuit 15, and the oscillation signal S22 of the frequency f22 and f22 = 54.95 MHz is taken out from the PLL22. The oscillation signal S22 is supplied to the mixer circuit 16 as the second local oscillation signal.

In this way, the frequency f16 of the first intermediate frequency signal S14 is converted into the second intermediate frequency signal S16 having a frequency f16 of f16 = f14-f22 = 55-54.95 MHz = 50 kHz. And
The second intermediate frequency signal S16 is supplied to the FM demodulation circuit 18 through the second intermediate frequency circuit 17, and the voice signal of the other party and the data signal from the base station are taken out to the terminal 19.

The above is the general configuration and operation of the receiving circuit in the analog cellular type mobile phone.

[0008]

By the way, as described above, the frequency f16 of the intermediate frequency signal S16 to be FM demodulated is
When f16 is as low as 50 kHz, the FM demodulation circuit 18 is generally composed of a quadrature demodulation circuit.

FIG. 5 shows a concrete connection example of the quadrature demodulation circuit. The second intermediate frequency signal S16 from the second intermediate frequency circuit 16 is supplied to the multiplication circuit 181 and transferred. It is supplied to the phase circuit 182. The phase shift circuit 182 has a phase shift characteristic as shown in FIG. 6, for example, and when the center frequency fc of the signal S16 is 50 kHz,
The signal S16 is phase-shifted by π / 2 and the signal S16 is shifted.
The phase shift corresponding to the frequency is performed.

Then, the output signal of the phase shift circuit 182 is supplied to the multiplication circuit 181, and is multiplied by the original signal S16, the audio signal is demodulated by this multiplication, and the audio signal is supplied to the low-pass filter 183. Then, unnecessary high frequency components are removed and then taken out to the terminal 19.

However, in this case, the phase shift circuit 182 is
As shown in FIG. 5, if the coil, the capacitor, and the resistor are used, these elements cannot be integrated, and therefore the FM demodulation circuit 18 cannot be integrated. Alternatively, when the demodulation circuit 18 is integrated into an IC, the phase shift circuit 182 is externally attached to the IC, and the effect of the IC is reduced.

The present invention is intended to solve the above problems.

[0013]

Therefore, in the present invention, when the reference numerals of the respective parts correspond to the embodiments described later, the operational amplifiers A1 to A3, the resistors R1 to R6, and the capacitors C1 and C2 are used. A multiplier circuit 181 configured to multiply the configured biquad filter 182, the input FM signal S16, and the output signal of the biquad filter 182.
And a low-pass filter 183 to which the output signal of the multiplication circuit 181 is supplied. The biquad filter 182 is supplied with the input FM signal S16 and has a phase shift characteristic of performing a π / 2 phase shift with respect to the input FM signal S16 at the center frequency fc of the input FM signal S16. The FM demodulated signal of the input FM signal S16 is taken out from the low pass filter 183.

[0014]

The biquad filter 182 functions as a phase shift circuit to perform quadrature FM demodulation.
As a result, the entire FM demodulation circuit can be integrated into an IC.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1, a multiplication circuit 181 is composed of a double balance type mixer circuit.
A second intermediate frequency signal S16 is supplied to the first intermediate frequency circuit 17 from the second intermediate frequency circuit 17.

Further, three operational amplifiers A1 to A3 are provided, the output terminal of the second intermediate frequency circuit 17 is connected to the inverting input terminal of the operational amplifier A1 through the resistor R1, and between the inverting input terminal and the output terminal. , A resistor R2 and a capacitor C1 are connected in parallel. Further, the output terminal of the operational amplifier A1 is connected to the inverting input terminal of the operational amplifier A2 through the resistor R3, and the capacitor C2 is connected between the inverting input terminal and the output terminal. Moreover, the output terminal of the operational amplifier A2 is
The resistor R4 is connected to the inverting input terminal of the operational amplifier A3, the resistor R5 is connected between the inverting input terminal and the output terminal, and the output terminal is connected to the inverting input terminal of the operational amplifier A1 via the resistor R6. Connected. Further, the non-inverting input terminals of the operational amplifiers A1 to A3 are grounded.

Thus, the operational amplifiers A1 to A3 and the element R are
By 1 to R6, C1, C2, bike quad filter 18
2 is configured. Then, at this time, by selecting the values of the resistors R1 to R6 and the capacitors C1 and C2, the phase characteristic of the filter 182 is set to the characteristic shown in FIG.
The filter 182 is a phase shift circuit.

The output signal of the operational amplifier A2 is supplied to the multiplication circuit 181. Further, the output signal of the multiplication circuit 181 is taken out to the terminal 19 through the low pass filter 183.

According to this structure, when the second intermediate frequency circuit 17 outputs the second intermediate frequency signal S16, the operational amplifier A2 shifts the phase of the second intermediate frequency signal S16 according to the characteristic shown in FIG. Is output. And this phase-shifted second
The intermediate frequency signal S16 and the original second intermediate frequency signal S16 from the second intermediate frequency circuit 17 are multiplied in the multiplication circuit 181. That is, quadrature FM demodulation is performed.

Therefore, from the multiplication circuit 181, the second
The FM demodulated audio signal is extracted from the intermediate frequency signal S16, and the audio signal is output to the terminal 19 after unnecessary high frequency components are removed by the low-pass filter 183.

In this case, the phase shift circuit 182 is composed of operational amplifiers A1 to A3 and elements R1 to R6, C1 and C2, and the elements R1 to R6, C1 and C2 are ICs.
Since it becomes a value that can be converted, the phase shift circuit 182 is set to I
It can be converted to C. Therefore, the FM demodulation circuit 18
Can be integrated into an IC, or can be integrated into a single chip including other circuits.

By the way, the elements R1 to R6, C1 and C2 are integrated into an IC.
In that case, the variation in the relative value becomes negligible, but the variation in the absolute value becomes non-negligible, resulting in an error in the phase shift characteristic of the phase shift circuit 182.

FIG. 2 shows an example in which such an error can be ignored by adjustment. That is, in the phase shift circuit 182, the resistors R2, R3, and R6 are variable resistance elements (or variable resistor circuits), and the variable control voltage VCTL is taken out from the control circuit 184, and the control voltage VCTL is changed. It is supplied to the resistance elements R2, R3 and R6 as its control voltage.

Therefore, since the values of the variable resistance elements R2, R3, and R6 are changed by changing the magnitude of the control voltage VCTL, this change causes the phase shift characteristic of the phase shift circuit 182 to be the characteristic shown in FIG. Can be adjusted to.

FIG. 3 shows an example in which the second intermediate frequency circuit 17 can be integrated into an IC together with the FM demodulation circuit 18. That is, a plurality of n band pass filters 71 to 71
7N is provided. In this case, the bandpass filter 71
7N are operational amplifiers A11 to A13 and a resistor R1 respectively.
It has 1, R14, R15, variable resistance elements R12, R13, R16, and capacitors C11, C12, and is configured as a biquad filter similar to the phase shift circuit 182. The filters 71 to 7N are connected in series, and the second intermediate frequency signal S16
A second intermediate frequency filter 171 having a pass band of?

A limiter amplifier 172 is connected to the next stage of the filter 171, and the filter 171 and the amplifier 172 form a second intermediate frequency circuit 17. Then, the output signal of the second mixer circuit 16 is supplied to the filter 71, and the output signal of the amplifier 172 is supplied to the demodulation circuit 18.

Further, the control voltage V from the control circuit 184
CTL is the variable resistance elements R12 and R1 of the filters 71 to 7N.
It is supplied to the variable resistors R2, R3, and R6 of the filter 181 as its control voltage, while being supplied to 3 and R16 as its control voltage, respectively.

According to such a configuration, the second intermediate frequency signal S16 of the output signals of the second mixer circuit 16 is selected and taken out by the filter 171, and the extracted second intermediate frequency signal S16 is obtained. After being amplified by the amplifier 172, it is supplied to the demodulation circuit 18 and FM demodulated.

In this case, according to this example, the filter 171 can also be integrated into an IC together with the demodulation circuit 18, and a ceramic filter element for selecting the second intermediate frequency signal S16 is externally attached to the IC. No need.

Further, the values of the variable resistance elements R12, R13, R16, R2, R3, and R6 can be changed by the control voltage VCTL to adjust the filters 71 to 7N and 181 to the required characteristics. At this time, in the IC, since the relative variations of the elements are small, the filters 71 to 7N, 1
81 can be adjusted by a common control voltage VCTL.

[0031]

According to the present invention, the phase shift circuit 182 is
Since it is composed of a biquad filter having operational amplifiers A1 to A3 and elements R1 to R6, C1 and C2,
The entire M demodulation circuit 18 can be integrated. Alternatively, the second intermediate frequency circuit 17 may be further included to form a one-chip IC.

Further, when integrated into an IC, even if there are variations in the elements, it is possible to adjust to the required characteristics by the control voltage VCTL.

[Brief description of drawings]

FIG. 1 is a system diagram showing an example of the present invention.

FIG. 2 is a system diagram showing another example of the present invention.

FIG. 3 is a system diagram showing another example of the present invention.

FIG. 4 is a system diagram showing an example of a receiving circuit.

FIG. 5 is a connection diagram showing a conventional example of an FM demodulation circuit.

FIG. 6 is a characteristic diagram showing a phase shift characteristic.

[Explanation of symbols]

 13 band pass filter 14 1st mixer circuit 15 1st intermediate frequency circuit 16 2nd mixer circuit 17 2nd intermediate frequency circuit 18 FM demodulation circuit 21 PLL for 1st local oscillation circuit 22 PLL for 2nd local oscillation circuit 71- 7N band pass filter 171 band pass filter 172 limiter amplifier 181 phase shift circuit 182 multiplication circuit 183 low pass filter

Claims (5)

[Claims] 1. A biquad filter comprising an operational amplifier, a resistor and a capacitor, a multiplication circuit for multiplying an input FM signal and an output signal of the biquad filter, and a multiplication circuit of the multiplication circuit. A low-pass filter supplied with an output signal, wherein the biquad filter is supplied with the input FM signal and at the center frequency of the input FM signal, the input FM signal
An FM demodulation circuit having a phase shift characteristic of performing a π / 2 phase shift on a signal, and adapted to extract an FM demodulation signal of the input FM signal from the low pass filter. 2. The F according to claim 1, which is integrated into an IC.
M demodulation circuit. 3. The FM demodulation circuit according to claim 1, wherein the input FM signal is an intermediate frequency signal of a superheterodyne receiver circuit. 4. The FM demodulation circuit according to claim 3, further comprising a plurality of biquad filters connected in series, and a limiter amplifier to which output signals from the final stages of the biquad filters are supplied. However, the plurality of biquad filters have a characteristic of passing an intermediate frequency signal output from the mixer circuit, the output signal of the mixer circuit is supplied to the first stage of the plurality of biquad filters, and the limiter is supplied. An FM demodulation circuit in which an output signal of an amplifier is supplied as the input FM signal to the biquad filter and the multiplication circuit. 5. The FM demodulation circuit according to claim 1, claim 2, claim 3 or claim 4, wherein a part of the resistor is a variable resistor element or a variable resistor circuit, An FM demodulation circuit in which a predetermined control voltage is supplied to a resistor element or a variable resistor circuit to adjust the characteristics of the biquad filter and the biquad filters.