JPH07235770A - Multilayer printed wiring board - Google Patents

Multilayer printed wiring board

Info

Publication number
JPH07235770A
JPH07235770A JP5142594A JP5142594A JPH07235770A JP H07235770 A JPH07235770 A JP H07235770A JP 5142594 A JP5142594 A JP 5142594A JP 5142594 A JP5142594 A JP 5142594A JP H07235770 A JPH07235770 A JP H07235770A
Authority
JP
Japan
Prior art keywords
layer
printed wiring
wiring board
power supply
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5142594A
Other languages
Japanese (ja)
Inventor
Takayuki Nakamura
隆行 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP5142594A priority Critical patent/JPH07235770A/en
Publication of JPH07235770A publication Critical patent/JPH07235770A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits

Abstract

PURPOSE:To provide a multilayer printed wiring board capable of reducing EMI caused by radiation of electromagnetic waves from side faces of the board. CONSTITUTION:Circuit patterns 3a and 3b are formed on a multilayer printed wiring board 5A. A power source layer 1a set to a source potential and ground layer 2 are oppositely on both sides of a dielectric layer 6. An end dielectric layer 10 having a less dielectric const. than that of the layer 6 is formed at the fringe of the layer 6. Electromagnetic waves induced over the layers 1a and 2 at the fringe of the board 5A are attenuated by the layer 10 disposed at the fringe of the dielectric disposed between the layers 1a and 2.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は電子機器に用いられる多
層プリント配線基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board used in electronic equipment.

【0002】[0002]

【従来の技術】近年の電子機器の急激な発達に伴って、
電子機器に搭載されるプリント配線基板に形成される回
路が高密度化しその動作が高速化すると共に、プリント
配線基板から放出される電磁波が、周囲の電子機器の動
作に悪影響を及ぼす電磁波妨害(EMI)が問題になっ
ている。
2. Description of the Related Art With the recent rapid development of electronic devices,
Circuits formed on a printed wiring board mounted on an electronic device have a high density and its operation speeds up, and electromagnetic waves emitted from the printed wiring board adversely affect the operation of surrounding electronic devices. ) Is a problem.

【0003】一般にプリント配線基板では、電源電位に
設定される電源層と、アース電位に設定されるグランド
層とを独立して設けて電源電圧の安定を図り、回路パタ
ンの電源電圧の変動による誤動作を防止している。この
ようにすることにより、回路パターンを流れる電流のル
ープが小さくなり、且つ電源層及びグランド層のインピ
ーダンスが低下するので、プリント配線基板から放出さ
れる電磁波を抑制することができる。
Generally, in a printed wiring board, a power supply layer set to a power supply potential and a ground layer set to a ground potential are independently provided to stabilize the power supply voltage and malfunction due to fluctuations in the power supply voltage of a circuit pattern. Is being prevented. By doing so, the loop of the current flowing through the circuit pattern becomes small, and the impedance of the power supply layer and the ground layer decreases, so that the electromagnetic waves emitted from the printed wiring board can be suppressed.

【0004】しかし、回路パターンでの動作の高速化に
比例して消費電力が増加し、電源層とグランド層のノイ
ズ電流が増えるために、プリント配線基板に対して別途
電磁波の放出を低減する手段を施すことが必要になって
いる。
However, since the power consumption increases in proportion to the speeding up of the operation in the circuit pattern and the noise current in the power supply layer and the ground layer increases, a means for separately reducing the emission of electromagnetic waves to the printed wiring board. Need to be applied.

【0005】これを受けて、実開平3−6859号公報
において、回路パターンを形成したプリント配線基板上
に、電源層の少なくとも一部を除いて、回路パターンを
覆うように絶縁層を形成し、該絶縁層上の電源層の絶縁
されていない部分と接続する導電層を形成し、プリント
配線基板からの電磁波の放出を抑制するプリント配線基
板が開示されている。
In response to this, in Japanese Utility Model Laid-Open No. 3-6859, an insulating layer is formed on a printed wiring board on which a circuit pattern is formed so as to cover the circuit pattern except at least a part of the power supply layer, There is disclosed a printed wiring board that suppresses the emission of electromagnetic waves from the printed wiring board by forming a conductive layer connected to the non-insulated portion of the power supply layer on the insulating layer.

【0006】この開示の方式によると、電源層に接続さ
れた導電層に対して、回路パターンとグランド層との分
布静電容量が大きくなり、回路インピーダンスが小さく
なるので、不要な高周波成分は電源層に高周波的にアー
スされて輻射ノイズが抑制される。また、導電層による
シールド効果が得られると共に、導電層によつて回路パ
ターン及びグランド層が覆われているために、回路イン
ピーダンスが均一化し、インピーダンス不整合による高
周波成分の発生が防止される。
According to the method of this disclosure, the distributed electrostatic capacitance between the circuit pattern and the ground layer becomes large with respect to the conductive layer connected to the power supply layer, and the circuit impedance becomes small. Radiation noise is suppressed by grounding the layer in a high frequency manner. In addition, the conductive layer shields the circuit pattern and the ground layer, so that the circuit impedance is made uniform and high frequency components due to impedance mismatch are prevented.

【0007】[0007]

【発明が解決しようとする課題】前述の開示に係るプリ
ント配線基板では、特に基板が多層構造になった場合に
問題となる基板の周端部分からの電磁波の放出について
は配慮されていない。図3は従来の多層プリント配線基
板の構成を示す断面説明図であり、図4は従来の多層プ
リント配線基板での電磁波放出の説明図である。図3に
示すように、多層構造のプリント配線基板5は、エポキ
シ樹脂などの絶縁材料で形成される複数の基板が積層さ
れて構成されている。これらの基板には、回路パターン
3a、3b、電源電位に設定される電源層1a、1b、
アース電位に設定されるグランド層2が、既知のフォト
リゾグラフィの技術により形成されている。
In the printed wiring board according to the above disclosure, no consideration is given to the emission of electromagnetic waves from the peripheral edge portion of the board, which is a problem particularly when the board has a multilayer structure. FIG. 3 is a cross-sectional explanatory view showing a configuration of a conventional multilayer printed wiring board, and FIG. 4 is an explanatory view of electromagnetic wave emission in the conventional multilayer printed wiring board. As shown in FIG. 3, the multilayer printed wiring board 5 is formed by stacking a plurality of boards made of an insulating material such as epoxy resin. On these substrates, circuit patterns 3a, 3b, power supply layers 1a, 1b set to a power supply potential,
The ground layer 2 set to the ground potential is formed by a known photolithography technique.

【0008】そして、多層構造のプリント配線基板5に
おいては、一つの基板の1面側に形成された電源層1a
と、他の基板の一面側に形成されたグランド層2とが、
樹脂材などの誘電体層6を挟んで対向配設されている。
In the printed wiring board 5 having a multilayer structure, the power supply layer 1a formed on one surface side of one board.
And the ground layer 2 formed on the one surface side of the other substrate,
The dielectric layers 6 made of a resin material or the like are arranged so as to face each other.

【0009】このような構成の従来の多層構造のプリン
ト配線基板5では、図4に示すように、電源層1aとグ
ランド層2との端部位置において、電源層1aとグラン
ド層2とにわたって電磁波7が誘起され、この電磁波7
がプリント配線基板5の周端部から放出され、放出され
た電磁波によつて、周囲の電子機器の動作に悪影響が及
ぼされることがある。
In the conventional multi-layered printed wiring board 5 having such a structure, as shown in FIG. 4, at the end positions of the power supply layer 1a and the ground layer 2, electromagnetic waves are spread across the power supply layer 1a and the ground layer 2. 7 is induced and this electromagnetic wave 7
May be emitted from the peripheral edge of the printed wiring board 5, and the emitted electromagnetic waves may adversely affect the operation of electronic devices in the vicinity.

【0010】本発明は、前述したようなプリント配線基
板でのEMI防止の現状に鑑みてなされたものであり、
その目的は、基板の側端部からの電磁波の放出によるE
MIを低減することが可能な多層プリント配線基板を提
供することにある。
The present invention has been made in view of the present situation of EMI prevention in a printed wiring board as described above,
The purpose is to emit E from the side edge of the substrate.
An object of the present invention is to provide a multilayer printed wiring board capable of reducing MI.

【0011】[0011]

【課題を解決するための手段】請求項1に記載の多層プ
リント配線基板は、回路パターンが形成された多層プリ
ント配線基板に、電源電位に設定される電源層と、アー
ス電位に設定されるグランド層とが、誘電体層を挟んで
対向配置され、前記誘電体層の誘電率よりも誘電率が低
い端部誘電体層が、前記誘電体層の周端部に配設されて
いることを特徴とする。
According to a first aspect of the present invention, there is provided a multilayer printed wiring board having a circuit pattern, a power source layer set to a power source potential, and a ground set to a ground potential. The layers are opposed to each other with the dielectric layer sandwiched therebetween, and an end dielectric layer having a dielectric constant lower than that of the dielectric layer is provided at a peripheral end of the dielectric layer. Characterize.

【0012】請求項2に記載の多層プリント配線基板
は、前記電源層及び前記グランド層の周端部が、前記誘
電体層の周端部よりも突出して配置され、前記電源層及
び前記グランド層の周端部と前記誘電体層の周端部間
に、前記端部誘電体層が配設されていることを特徴とす
る。
In the multilayer printed wiring board according to the present invention, the peripheral ends of the power supply layer and the ground layer are arranged so as to protrude from the peripheral end parts of the dielectric layer, and the power supply layer and the ground layer. The end dielectric layer is disposed between the peripheral end of the dielectric layer and the peripheral end of the dielectric layer.

【0013】[0013]

【作用】この構成によると、多層プリント配線基板の周
端部において、電源層とグランド層とにわたって誘起さ
れる電磁波は、電源層とグランド層間に配設されている
誘電体層の誘電率よりも誘電率が低く、電源層とグラン
ド層間に配設されている誘電体の周端部に配設されてい
る端部誘電体層により減衰され、多層プリント配線基板
の周端部から放出される電磁波の強度は低下する。
According to this structure, the electromagnetic wave induced across the power supply layer and the ground layer at the peripheral edge of the multilayer printed wiring board is higher than the dielectric constant of the dielectric layer disposed between the power supply layer and the ground layer. Electromagnetic waves that have a low dielectric constant and are attenuated by the end dielectric layers disposed at the peripheral edges of the dielectrics disposed between the power supply layer and the ground layer and emitted from the peripheral edges of the multilayer printed wiring board. The strength of is reduced.

【0014】[0014]

【実施例】■以下、本発明の一実施例を図1及び図2を
参照して説明する。図1は同実施例の構成を示す断面説
明図、図2は同実施例の電磁波抑制の説明図である。図
1に示すように、本実施例ではすでに図3を参照して説
明した従来の多層構造のプリント配線基板に対して、プ
リント配線基板5Aの周端部において、誘電体層6に切
欠部8が形成され、切欠部8内には端部誘電体層10と
して空気が充填されている。本実施例のその他の部分の
構成は、すでに図3を参照して説明した従来の多層構造
のプリント配線基板と同一なので重複した説明は省略す
る。
EXAMPLE 1 An example of the present invention will be described below with reference to FIGS. 1 is a cross-sectional explanatory view showing the configuration of the same embodiment, and FIG. 2 is an explanatory view of electromagnetic wave suppression of the same embodiment. As shown in FIG. 1, in the present embodiment, the cutout portion 8 is formed in the dielectric layer 6 at the peripheral end portion of the printed wiring board 5A, as compared with the conventional printed wiring board having the multilayer structure described with reference to FIG. Is formed, and the notch 8 is filled with air as the end dielectric layer 10. The configuration of the other parts of the present embodiment is the same as that of the conventional printed wiring board of the conventional multilayer structure already described with reference to FIG.

【0015】次に、このような構成の本実施例の電磁波
放出の抑制動作を説明する。図2に示すように、本実施
例では、プリント配線基板5Aの周端部において、電源
層1aとグランド層2間に配設されている誘電体層6に
切欠部8が形成され、この切欠部8には比誘電率がほぼ
1である空気が端部誘電体層10として充填されてい
る。
Next, the operation of suppressing the electromagnetic wave emission of this embodiment having such a configuration will be described. As shown in FIG. 2, in the present embodiment, a cutout 8 is formed in the dielectric layer 6 disposed between the power supply layer 1a and the ground layer 2 at the peripheral end of the printed wiring board 5A. Air having a relative dielectric constant of about 1 is filled in the portion 8 as the end dielectric layer 10.

【0016】一般に、切欠部8の誘電率をεとし、電源
層1aとグランド層2間の電位差をEとすると、電源電
位に設定された電源層1aとアース電位に設定されたグ
ランド層2間において、切欠部8内の端部誘電体層10
に流れる変位電流の密度iは〔数1〕で与えられる。
Generally, when the dielectric constant of the notch 8 is ε and the potential difference between the power supply layer 1a and the ground layer 2 is E, the power supply layer 1a set to the power supply potential and the ground layer 2 set to the ground potential are set. At the end dielectric layer 10 in the cutout 8
The density i of the displacement current flowing in is given by [Equation 1].

【0017】[0017]

【数1】i=ε(∂E/∂t)[Equation 1] i = ε (∂E / ∂t)

【0018】そして、〔数1〕で与えられる変位電流密
度iに基づいて、電源層1とグランド層2間にわたって
電磁波が誘起され、プリント配線基板5Aの周端部から
放出される。
Electromagnetic waves are induced between the power supply layer 1 and the ground layer 2 based on the displacement current density i given by [Equation 1], and emitted from the peripheral end portion of the printed wiring board 5A.

【0019】本実施例においては、切欠部8には空気が
充填されていて、その誘電率εは誘電体層6の誘電率よ
りも著しく小さいので、プリント配線基板5Aの周端部
から放出される電磁波の強度は大幅に低下され、プリン
ト配線基板5Aの周端部から放出される電磁波によるE
MIを防止することが可能になる。
In this embodiment, the notch 8 is filled with air, and its dielectric constant ε is significantly smaller than the dielectric constant of the dielectric layer 6, so that the notch 8 is discharged from the peripheral edge of the printed wiring board 5A. The intensity of the electromagnetic wave is greatly reduced, and the electromagnetic wave E emitted from the peripheral edge of the printed wiring board 5A
It becomes possible to prevent MI.

【0020】なお、実施例では端部誘電体層として空気
を利用する場合を説明したが、本発明は本実施例に限定
されるものでなく、端部誘電体層として電源層とグラン
ド層間の誘電体層よりも誘電率の小さい各種の材質を使
用することができる。
In the embodiment, the case where air is used as the end dielectric layer has been described, but the present invention is not limited to this embodiment, and the end dielectric layer is provided between the power supply layer and the ground layer. Various materials having a dielectric constant smaller than that of the dielectric layer can be used.

【0021】[0021]

【発明の効果】本発明によると、多層プリント配線基板
の周端部において、電源層とグランド層にわたって誘起
される電磁波は、電源層とグランド層間に配設されてい
る誘電体層の誘電率よりも誘電率が低く、電源層とグラ
ンド層間に配設されている誘電体層の周端部に配設され
ている端部誘電体層により減衰される。このために、多
層プリント配線基板の周端部から放出される電磁波の強
度が低下し、多層プリント配線基板による電磁波妨害
(EMI)が低減される。
According to the present invention, the electromagnetic wave induced across the power supply layer and the ground layer at the peripheral edge of the multilayer printed wiring board is more than the dielectric constant of the dielectric layer disposed between the power supply layer and the ground layer. Also has a low dielectric constant, and is attenuated by the end dielectric layers arranged at the peripheral ends of the dielectric layers arranged between the power supply layer and the ground layer. For this reason, the intensity of electromagnetic waves emitted from the peripheral end portion of the multilayer printed wiring board is reduced, and electromagnetic interference (EMI) due to the multilayer printed wiring board is reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の構成を示す断面説明図であ
る。
FIG. 1 is a cross-sectional explanatory view showing the configuration of an embodiment of the present invention.

【図2】同実施例の電磁波抑制の説明図である。FIG. 2 is an explanatory diagram of electromagnetic wave suppression of the example.

【図3】従来の多層プリント配線基板の構成を示す断面
説明図である。
FIG. 3 is an explanatory sectional view showing the structure of a conventional multilayer printed wiring board.

【図4】従来の多層プリント配線基板の電磁波放出の説
明図である。
FIG. 4 is an explanatory diagram of electromagnetic wave emission of a conventional multilayer printed wiring board.

【符号の説明】[Explanation of symbols]

1a、1b 電源層 2 グランド層 3a、3b 回路パタン 6 誘電体層 8 切欠部 10 端部誘電体層 1a, 1b Power layer 2 Ground layer 3a, 3b Circuit pattern 6 Dielectric layer 8 Notch 10 Edge dielectric layer

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 回路パターンが形成された多層プリント
配線基板に、電源電位に設定される電源層と、アース電
位に設定されるグランド層とが誘電体層を挟んで対向配
置され、前記誘電体層の誘電率よりも誘電率が低い端部
誘電体層が、前記誘電体層の周端部に配設されているこ
とを特徴とする多層プリント配線基板。
1. A multilayer printed wiring board on which a circuit pattern is formed, a power supply layer set to a power supply potential and a ground layer set to a ground potential are arranged to face each other with a dielectric layer interposed therebetween, A multilayer printed wiring board, characterized in that an end dielectric layer having a dielectric constant lower than that of the layer is disposed at a peripheral end of the dielectric layer.
【請求項2】 前記電源層及び前記グランド層の周端部
が、前記誘電体層の周端部よりも突出して配置され、前
記電源層及び前記グランド層の周端部と前記誘電体層の
周端部間に、前記端部誘電体層が配設されていることを
特徴とする請求項1記載の多層プリント配線基板。
2. The peripheral edges of the power supply layer and the ground layer are arranged so as to project from the peripheral edges of the dielectric layer, and the peripheral edges of the power supply layer and the ground layer and the dielectric layer are arranged. The multilayer printed wiring board according to claim 1, wherein the end dielectric layer is disposed between the peripheral ends.
JP5142594A 1994-02-24 1994-02-24 Multilayer printed wiring board Pending JPH07235770A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5142594A JPH07235770A (en) 1994-02-24 1994-02-24 Multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5142594A JPH07235770A (en) 1994-02-24 1994-02-24 Multilayer printed wiring board

Publications (1)

Publication Number Publication Date
JPH07235770A true JPH07235770A (en) 1995-09-05

Family

ID=12886579

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5142594A Pending JPH07235770A (en) 1994-02-24 1994-02-24 Multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JPH07235770A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007019198A (en) * 2005-07-07 2007-01-25 Fujitsu Ltd Laminated substrate and electronic apparatus having the same
JP2008034584A (en) * 2006-07-28 2008-02-14 Kyocera Corp Plural patterning wiring substrate, wiring substrate, and electronic equipment

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007019198A (en) * 2005-07-07 2007-01-25 Fujitsu Ltd Laminated substrate and electronic apparatus having the same
JP4689375B2 (en) * 2005-07-07 2011-05-25 富士通株式会社 Laminated substrate and electronic device having the laminated substrate
JP2008034584A (en) * 2006-07-28 2008-02-14 Kyocera Corp Plural patterning wiring substrate, wiring substrate, and electronic equipment

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