JPH07235189A - Semiconductor memory integrated circuit - Google Patents

Abstract

PURPOSE:To increase an operating range of a low power source voltage without decreasing an operating speed. CONSTITUTION:The semiconductor memory integrated circuit comprises a power source voltage detector 7 for outputting a voltage detection signal DV which becomes an active level when a power source voltage Vcc becomes lower than a preset level. A transistor Q63 which is turned on/off in response to the signal DV and a transistor Q62 which is connected in series with the transistor Q63 are provided in parallel with transistors Q58-Q61 for outputting a reference voltage Vr. Thus, when the signal DV is the active level, the transistor Q63 is turned on, and the voltage Vr is deviated to a level of an OFF cell information side of binary information read from a memory cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory integrated circuit, and more particularly to a semiconductor memory integrated circuit provided with a CMOS type inverter and a current detection type cell information sensing circuit which operates at high speed and which has a transistor whose gate receives the output thereof. Regarding

[0002]

2. Description of the Related Art In an EPROM type semiconductor memory integrated circuit using a MOS transistor having a floating gate as a memory cell, a threshold voltage is controlled by injecting charges into the floating gate to store binary information. When the threshold voltage is high, when the voltage for reading is supplied to the control gate, it is turned off and the current flowing is extremely small. When the threshold voltage is low, it is turned on when the voltage for reading is supplied and the resistance value is The current flowing low becomes large. Therefore, by supplying the power supply voltage to the stored information reading point of the memory cell through the resistance element, the power supply voltage level is read in the off state, and the divided voltage information by the resistance element and the memory cell is read in the on state. It

However, since a large number of memory cells are connected to one bit line for reading information and the additional capacitance thereof is large, the level between the power supply voltage level and the voltage dividing level by the resistive element and the memory cell is increased. If the voltage is changed, the charging / discharging time becomes long and high-speed operation cannot be obtained. In addition, power consumption due to charging and discharging also increases. Therefore, an inverter that receives the level of the selected bit line at its input end and a transistor that receives the output of this inverter at its gate are provided.
A current detection type cell information sense circuit is often used, which supplies a bias voltage with almost no level change to a selected bit line and provides an output with a large difference in read voltage between memory cells in an on state and an off state. (For example, Japanese Patent Publication No. 3-27998, Japanese Patent Laid-Open No. 63-
No. 117397, Japanese Patent Laid-Open No. 4-67500).

The output voltage of the cell information sense circuit is compared with the reference voltage corresponding to the intermediate level of the binary information level in the comparison circuit, and the information on the on-state and off-state of the memory cell (hereinafter, on-cell information, off-cell information). The signal of the level corresponding to the information) is output.

As a method of generating the above-mentioned reference voltage,
A reference cell section having a dummy cell that generates a current at a level intermediate between the on-cell information level and the off-cell information level is provided, and the current of this dummy cell is detected by a reference cell information sense circuit having the same circuit configuration as the cell information sense circuit. Then, a method of generating a reference voltage at a level corresponding to the detected current (see, for example, Japanese Patent Publication No. 3-27998), on-cell information having the same size and structure as a normal memory cell,
A reference cell section having a dummy cell for storing one of the off-cell information (for example, on-cell information) is provided, and the current of this dummy cell is detected by a reference cell information sense circuit having the same circuit configuration as the cell information sense circuit and the detected current is detected. A method of generating a voltage of a level corresponding to and level shifting this voltage to be a reference voltage (for example, our 8M bit EPR
OM. μPD27C8000 etc.).

In the former method, the dummy cell needs to be formed in a size different from that of the normal memory cell, but the circuit configuration is simplified. Further, in the latter method, although the circuit configuration becomes slightly complicated, the dummy cell can be formed with the same size and the same structure as a normal memory cell.

FIG. 6 is a circuit diagram showing an example of a semiconductor memory integrated circuit adopting the latter method.

This semiconductor memory integrated circuit has a plurality of memory cells MC arranged in a matrix of rows and columns and storing binary information of on-cell information and off-cell information corresponding to the magnitude of a current value in a selected state (see FIG. 6 shows only one),
Information read from the plurality of word lines (only one line is shown in FIG. 6) for selecting the plurality of memory cells MC in row units and the memory cells in the selected state of each column of the plurality of memory cells MC are displayed. A plurality of bit lines BL to be transmitted (see FIG. 6).
Memory cell array 1 having only one display), a column selection circuit 2 for selecting one (one column) of a plurality of bit lines BL (columns), and a memory cell array 1 which operates at a power supply voltage Vcc. A CMOS type inverter IV1 for receiving the information read from the memory cell MC in the row or column (selected state) selected by the word line WL and the column selection circuit 2 and inverting the signal level of this information, source Is connected to the input terminal of the inverter IV1 and the gate is connected to the inverter IV.
N-channel type transistor Q3 for receiving the output signal of 1
3. The source is the power supply voltage Vcc and the gate is the inverter IV
Transistor Q receives the output signal of 1 and the drain
A P-channel type transistor Q34 connected to the drain of 33 and a P-channel type transistor Q35 having its source receiving the power supply voltage Vcc and connecting its gate and drain to the drain of the transistor Q33 are provided. And the voltage (V
mc) is output from the gate and drain of the transistor Q35, a cell information sense circuit 3, a dummy cell DMC that stores on-cell information, and a transistor Q41 having the same characteristics as the transistor Q21 of the column selection circuit 2, and a reference cell section that outputs on-cell information. 4 and an inverter IV2, transistors Q513, Q514, and Q515, and the circuit configuration thereof is the same as that of the cell information sense circuit 3;
From the gate and drain of the transistor Q515, which outputs a voltage (Vdmc) corresponding to the information from the transistor Q515.
The power supply voltage V is connected to the source by connecting to the gate and drain of 15.
A P-channel type transistor Q51 which receives a cc and forms a current mirror circuit together with the transistor Q515 and transmits a current of a level corresponding to the current flowing in the transistor Q515, and a drain and a gate are connected to each other and the drain is transmitted from the transistor Q51 to the drain. The N-channel type transistor Q52 which receives the generated current and the gate are both connected to the gate and drain of the transistor Q52 and the drains are commonly connected to form a current mirror circuit together with the transistor Q52 to correspond to the current transmitted from the transistor Q51. N-channel type transistors Q54 and Q55, which flow currents of the same level, and sources are both connected to the ground potential point, and gates receive the power supply voltage Vcc and drains are connected to the sources of the transistors Q52, Q54, and Q55, respectively. Level shifting N-channel type transistors Q53, Q56, Q57, and level shifting P-channel type transistors in which the source receives the power supply voltage Vcc and the gate is connected to the ground potential point and the drain is connected to the drains of the transistors Q54 and Q55, respectively. A level-shifting P-channel transistor Q in which both Q58 and source receive the power supply voltage Vcc and whose gate and drain are both connected to the drains of the transistors Q54 and Q55.
59, Q60, Q61 are provided, and the output voltage (Vdmc) of the reference cell information sense circuit 51 is level-shifted to correspond to the intermediate level of the binary information (on-cell information, off-cell information) stored in the memory cell MC. Reference voltage V
The reference voltage generation circuit 5b that outputs r from the gates and drains of the transistors Q59, Q60, and Q61 is compared with the reference voltage Vr and the output voltage (Vmc) of the cell information sense circuit 3, and the signal (OUT) of the comparison result is compared. It has a configuration including a comparison circuit 6 for outputting.

Next, the operation of this semiconductor memory integrated circuit will be described with reference to FIG.

First, the case where on-cell information is stored in the memory cell MC will be described. This memory cell M
When C enters the selected state, a current flows through the memory cell MC and the level at the input end of the inverter IV1 drops. As a result, the output level of the inverter IV1 rises, the on-resistances of the transistors Q33 and Q34 decrease, and the bit line B
The level of L and the input terminal of the inverter IV1 rises.
When this level becomes higher than the threshold voltage of the inverter IV1, the output level of the inverter IV1 decreases and the on-resistances of the transistors Q33 and Q34 increase, so that the level of the input terminal (bit line BL) of the inverter IV1 eventually becomes the inverter IV1. Near the threshold voltage (for example, 1.
It stabilizes at 5V). Output voltage Vmc (ON) at this time
Is a voltage higher than the level of the input terminal of the inverter IV1 by a voltage drop of the transistor Q33 (for example, 1.8 V).
Becomes

On the other hand, when off-cell information is stored in the memory cell MC and this memory cell MC is in the selected state,
Since almost no current flows through this memory cell, the level at the input end of the inverter IV1 rises and the level at the output end drops, so that the on-resistances of the transistors Q33 and Q34 increase and the level at the input end of the inverter IV1 increases. Will fall. When this level falls below the threshold voltage of the inverter IV1, the output level of the inverter IV1 rises and the ON resistances of the transistors Q33 and Q34 are reduced, so that the input terminal (bit line B
The level of (L) stabilizes near the threshold voltage of the inverter IV1 (a level slightly higher than that in the case of on-cell information, for example, 1.52V). Output voltage Vmc at this time
Since (OFF) is a state in which the transistors Q33 and Q34 are close to the OFF state, the power supply voltage Vcc (for example, 5.0).
The voltage is about the voltage (for example, 4.8 V) obtained by subtracting the threshold voltage of the transistor Q35 from V) (transistor Q35).
Threshold voltage is set to a small value in order to maximize the output voltage Vmc (OFF)).

On the other hand, the basic cell information sense circuit 51
Since the on-cell information is stored in the dummy cell DMC, the output voltage Vdmc of is the same as the output voltage Vmc of the cell information sense circuit 3 when the on-cell information is received from the memory cell array 1. This output voltage Vdmc is transmitted as a current to the transistor Q51 by the current mirror circuit composed of the transistors Q515 and Q51, and the current is further transferred to the transistor Q54 and Q5 by the current mirror circuit composed of the transistors Q52, Q54 and Q55.
5 to the transistors Q54 to Q61 connected in series and in parallel between the power supply voltage Vcc supply terminal and the ground potential point to divide the power supply voltage Vcc to obtain the reference voltage Vr in which the output voltage Vdmc is level-shifted. It has become.

As described above, the current flowing through the output transistor Q515 of the reference cell information sense circuit 51 is generated by using the two-stage current mirror circuit.
And a transistor Q3 for output of the cell information sense circuit 3
5, the power supply voltage Vcc fluctuates and the current value of the memory cell (dummy cell) storing the on-cell information changes, and the output voltage changes. Vmc, V
Even if dmc changes, the reference voltage Vr remains the output voltage V
Since it changes following mc and Vdmc, the power supply voltage Vc
It can be applied in a wide range to the variation of c.

[0014]

In the conventional semiconductor memory integrated circuit described above, the information from the dummy cell DMC storing the on-cell information is equal to the cell information sense circuit 3 for detecting the stored information of the normal memory cell MC. It is detected by the reference cell information sense circuit 51 of the configuration, and the detection output is 2
By passing through the current mirror circuit of the stages, the same connection as the output transistor Q35 of the cell information sense circuit 3 and the reference voltage Vr from the transistors Q59 to Q61 of the same conductivity type are provided.
Therefore, it is possible to adapt to a variation in the power supply voltage Vcc in a wide range.

On the other hand, increasing the capacity of the semiconductor memory integrated circuit,
Miniaturization is progressing more and more, and along with it, lowering of power supply voltage and lower power consumption are becoming indispensable. The above-described conventional semiconductor memory integrated circuit can be applied to a wide range of the power supply voltage Vcc, but the following problems occur as the power supply voltage is lowered.

The cell information sense circuit 3 includes a CMOS-type inverter IV1 which operates with a power supply voltage Vcc. The threshold voltage of the inverter IV1 determines the output voltage Vmc (ON) of the on-cell information. And this Vm
c (ON) and output voltage Vmc (OFF) of off-cell information
It is set to a low value so that the difference between and becomes large. Therefore, the P-channel transistor L of the inverter IV1
The threshold voltage of Q32 is set to a large value, and when the power supply voltage Vcc decreases, the output voltage of the inverter IV1 decreases at [Vcc- | Vt (Q32) |] (Vt (Q32) is The threshold voltage of the transistor Q32) and the resistance value of the transistor Q33 increase, and the current flowing through the transistor Q33 decreases, so that the output voltage Vmc (ON) rises.

On the other hand, although the output voltage Vdmc of the reference cell information sense circuit 51 changes as much as the output voltage Vmc (ON), P-channel type transistors Q35 and Q515 are used.
Of the output voltage V corresponding to the off-cell information
Since mc (OFF) is set to a value as close as possible to the power supply voltage Vcc, it is small, and therefore the P-channel transistor Q5
1, the threshold voltage of Q58 to Q62 is also set small,
The threshold voltages of the N-channel transistors Q52 to Q57 are also set smaller than those of the transistors Q32 and Q512, so that the output voltages of the inverters IV1 and IV2 are influenced by the threshold voltages of the transistors Q32 and Q512. Even if the power supply voltage becomes Vcc, the reference voltage V depending on the threshold voltage of these transistors Q51 to Q62.
There is no effect on r, and the reference voltage Vr is the power supply voltage Vcc.
Changes linearly with respect to.

As a result, when the power supply voltage Vcc becomes low,
The output voltage Vmc (ON) becomes equal to the reference voltage Vr (power supply voltage V1) and becomes higher than the reference voltage Vr, and the read information of the memory cell cannot be detected.

In order to solve this problem, if the reference voltage Vr is biased to the output voltage Vmc (OFF) side from the beginning, the operating amplitude of the comparison circuit 6 at the time of detecting the on-cell information becomes large and the operating speed thereof. Is reduced.

It is an object of the present invention to provide a semiconductor memory integrated circuit capable of expanding the low power supply voltage operating range without lowering the operating speed.

[0021]

In a semiconductor memory integrated circuit of the present invention, a plurality of memory cells for storing binary information of on-cell information and off-cell information corresponding to the magnitude of a current value in a selected state are arranged. A memory cell array section for reading the stored information of the memory cell in the selected state, and a CMOS type first section which operates at a predetermined power supply voltage and receives at the input terminal the information read from the memory cell array section and inverts the signal level of this information. One inverter, a first conductivity type first transistor having a source connected to the input terminal of the inverter and having a gate for receiving the output signal of the inverter; and a source receiving the power supply voltage for a gate and a drain of the first transistor. A voltage of a level corresponding to the information from the memory cell in the selected state is provided, which is provided with a second transistor of reverse conductivity type connected to the drain. A cell information sense circuit for outputting from the gate and drain of the second transistor; a reference information output unit for outputting information corresponding to one of binary information stored in the memory cell array unit; and the first inverter. , A first transistor, a second transistor respectively corresponding to the second transistor, a third transistor, and a fourth transistor, the circuit configuration of which is the same as that of the cell information sense circuit, and the information from the reference information output unit. Binary information stored in the memory cell array unit by providing a reference information sense circuit for outputting a voltage of a level corresponding to the above from the gate and drain of the fourth transistor and level shifting the output voltage of the reference information sense circuit. A reference voltage generating section for outputting a reference voltage corresponding to an intermediate level of the In the semiconductor memory integrated circuit having a comparator circuit which compares the output voltage of the serial cell information sense circuit outputs a signal of the comparison result,
A power supply voltage detection circuit that outputs a voltage detection signal that becomes an active level when the power supply voltage falls below a preset level; and a gate that receives the voltage detection signal and turns on.
A fifth transistor which is turned off is provided, and when the voltage detection signal is at an active level, the reference voltage has a level biased toward the off cell information side of the output voltage of the cell information sense circuit. ing.

Further, the reference information output section is a circuit for outputting information corresponding to on-cell information of the binary information, and the output voltage of the reference information sense circuit in the reference voltage generating circuit is level-shifted to obtain the reference voltage. The circuit portion to be obtained is of a reverse conductivity type for connecting the gate to the gate and drain of the fourth transistor to form a current mirror circuit together with the fourth transistor and transmitting a current corresponding to the current flowing through the fourth transistor. A sixth transistor, a seventh transistor of one conductivity type that causes a current corresponding to the current transmitted by the sixth transistor to flow, a source for receiving a power supply voltage, and a gate and a drain for the drain of the seventh transistor. A reverse-conductivity-type eighth transistor to be connected, and the reference voltage is applied from the gate and drain of the eighth transistor. And a fifth transistor of a reverse conductivity type that supplies the power supply voltage to its source, and connects between the supply end of the power supply voltage and the output end of the reference voltage when the voltage detection signal is at the active level. It is configured to reduce the impedance.

Further, a plurality of power supply voltage detection circuits for outputting voltage detection signals each of which becomes an active level when the power supply voltage is preset and drops below a plurality of different levels are provided, and the gates are provided with the power supply voltage detection circuits. And a plurality of fifth transistors that respectively receive the voltage detection signals of the above.

[0024]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment is different from the conventional semiconductor memory integrated circuit shown in FIG. 6 in that when the power supply voltage Vcc falls below a preset voltage, a voltage detection signal DV which becomes an active level (low level) is generated. A power supply voltage detection circuit 7 for outputting is provided, and in the reference voltage generation circuit 5b, a P-channel type transistor Q63 which turns on and off by receiving the power supply voltage Vcc at the source and receiving the voltage detection signal DV at the gate,
The source is connected to the drain of the transistor Q63, and the gate and drain are connected to the reference voltage Vr output terminal (transistor Q5
P-channel type transistor Q62 connected to the gates and drains of 9 to Q61 is used as the reference voltage generation circuit 5, and when the voltage detection signal DV is at the active level, the transistor Q63 is turned on to set the reference voltage Vr to the output voltage. The point is that the level is biased toward the off-cell information side of Vmc.

Next, the operation of this embodiment will be described.
FIG. 2 is a power supply voltage Vc for explaining the operation of this embodiment.
6 is a characteristic diagram of a reference voltage Vr and an output voltage Vmc of the cell information sense circuit 3 with respect to c. FIG.

In the power supply voltage detection circuit 7, the power supply voltage Vcc is a preset voltage V2 (for example, the output voltage Vmc (O
When N) is higher than the power supply voltage which starts to rise, for example, 3.6 V), the voltage detection signal DV is maintained at a high level inactive level. Therefore, the transistor Q63 is turned off, and the circuit configuration is the same as that of the conventional example shown in FIG.
The reference voltage Vr at this time is, for example, 5.0 V for the power supply voltage Vcc, 1.8 V for the output voltage Vmc (ON), and Vmc.
When (OFF) is set to 4.8V, the transistor Q54,
The combined resistance of Q55, the combined resistance of the transistors Q56 and Q57, and the combined resistance of the transistors Q59 to Q61 are, for example, 1 KΩ, and Vmc (ON) and Vmc (OF
The intermediate value of F) is set to 3.3V.

When the power supply voltage Vcc becomes lower than the voltage V2 (3.6V), the voltage detection signal DV becomes a low level active level and the transistor Q63 is turned on, and the series circuit of the transistors Q62 and Q63 forms a transistor Q.
The circuit configuration is further connected in parallel to the parallel circuit of 58 to Q61. As a result, the reference voltage Vr is on the power supply voltage Vcc side,
In other words, the level is biased to the output voltage Vmc (OFF) side, and conventionally, when the power supply voltage Vcc is V1 or less, it is impossible to detect the information of the memory cell, but it is possible to detect to the vicinity of V3 which is lower than that. If V1 is 3.0 V, for example, the voltage at which the extension line of the reference voltage Vr crosses Vmc (ON) is 2.0 V. Here, the transistor Q6
Assuming that the combined resistance of 2, Q63 is 0.8 KΩ, the reference voltage Vr when the power supply voltage Vcc is 3.0 V is 2.4.
It becomes 5V. When the power supply voltage Vcc further decreases, the reference voltage Vr crosses the output voltage Vmc (ON). If the output voltage Vmc (ON) at this time is about 2.1V, the power supply voltage Vcc at the intersection becomes 2.57V. That is, the low voltage side of the power supply voltage Vcc can be expanded to about 2.6 to 2.7V.

In this embodiment, the range in which the reference voltage Vr is biased toward the output voltage Vmc (OFF) side is the output voltage Vr.
Since the difference between mc (ON) and the level on the extension line of the reference voltage Vr is small, the operating speed of the comparison circuit 6 does not fall within this range.

As a concrete circuit of the power supply voltage detecting circuit 7, the most basic example of FIG. 3 using the constant voltage characteristic of a diode and the resistance change characteristic of a depletion type transistor are used to simplify the circuit. Figure 4 (A), (B)
The example of is raised.

Further, in this embodiment, the bias of the reference voltage Vr in the low power supply voltage range is determined by the transistor Q62,
Although it is realized by the series circuit of Q63, transistor Q6
It is also possible to directly connect the drain of No. 3 to the output terminal of the reference voltage Vr and realize it only by the transistor Q63.

FIG. 5 is a circuit diagram of a reference voltage generating portion according to the second embodiment of the present invention.

In this embodiment, two power supply voltage detecting circuits 7 are provided.
a, 7b and the transistors Q62 to Q65 are provided to switch the reference voltage Vr in two stages, and the difference voltage between the output voltage Vmc (ON) and the reference voltage Vr at this switching point is reduced to reduce the comparison circuit 6 at a low power supply voltage. In addition to speeding up the operation of, the low voltage side of the power supply voltage Vcc is further expanded.

In this embodiment, the reference voltage V
Although the number of switching stages of r is two, the number of switching stages can be further increased.

[0036]

As described above, according to the present invention, a power supply voltage detection circuit that outputs a voltage detection signal that becomes an active level when the power supply voltage falls below a preset level, and an ON circuit in response to the voltage detection signal. ， Provided with a transistor to turn off, when the voltage detection signal is active level,
The CMO included in the cell information sense circuit is operated at the time of low power supply voltage operation by switching the reference voltage serving as the comparison reference of the level of the binary information read from the memory cell.
Due to the characteristics of the S-type inverter, when the output voltage corresponding to the on-cell information among the binary information read from the memory cell is biased to the output voltage side corresponding to the off-cell information, the reference voltage also shifts to the output voltage side corresponding to the off-cell information. Since the switching is performed in a biased manner, there is an effect that the operating range of the low power supply voltage can be expanded without increasing the difference between the reference voltage and the output voltage corresponding to the on-cell information, that is, without reducing the operating speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a characteristic diagram of a reference voltage and a memory cell read information voltage with respect to a power supply voltage for explaining the operation of the embodiment shown in FIG.

FIG. 3 is a circuit diagram showing a first specific example of the power supply voltage detection circuit of the embodiment shown in FIG.

FIG. 4 is a circuit diagram showing a second specific example of the power supply voltage detection circuit of the embodiment shown in FIG. 1 and a power supply voltage characteristic diagram of its circuit element.

FIG. 5 is a circuit diagram of a reference voltage generating portion according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing an example of a conventional semiconductor memory integrated circuit.

FIG. 7 is a characteristic diagram of a reference voltage and a memory cell read information voltage with respect to a power supply voltage for explaining the operation and problems of the semiconductor memory integrated circuit shown in FIG.

[Explanation of symbols]

1 memory cell array 2 column selection circuit 3 cell information sense circuit 4 reference cell section 5, 5a, 5b reference voltage generation circuit 6 comparison circuit 7, 7a, 7b power supply voltage detection circuit 51 reference cell information detection circuit DMC dummy cell IV1, IV2 inverter MC Memory cells Q21, Q31 to Q35, Q41, Q51 to Q65, Q
511-Q515 transistors

Claims (4)

[Claims] 1. A memory cell array for arranging a plurality of memory cells for storing binary information of on-cell information and off-cell information corresponding to the magnitude of a current value in a selected state and reading the stored information of the selected memory cell. And a CMOS which operates at a predetermined power supply voltage and receives at its input terminal the information read from the memory cell array section and inverts the signal level of this information.
Type first inverter, a source is connected to an input terminal of the inverter, a first conductivity type first transistor whose gate receives an output signal of the inverter, and a source which receives the power supply voltage and a gate and a drain which are the first And a cell information sense circuit which outputs a voltage of a level corresponding to information from the memory cell in the selected state from a gate and a drain of the second transistor, the cell information sense circuit including a second transistor of an opposite conductivity type connected to the drain of the second transistor. A reference information output unit that outputs information corresponding to one of the binary information stored in the memory cell array unit;
Of the inverter, the first transistor and the second transistor respectively corresponding to the second inverter, the third transistor and the fourth transistor, the circuit configuration of which is the same as that of the cell information sense circuit from the reference information output unit. 2 is provided with a reference information sense circuit for outputting a voltage of a level corresponding to the information from the gate and drain of the fourth transistor, and the output voltage of the reference information sense circuit is level-shifted and stored in the memory cell array section. A reference voltage generator that outputs a reference voltage corresponding to an intermediate level of the value information level, and a comparison circuit that compares the reference voltage with the output voltage of the cell information sense circuit and outputs a signal of the comparison result. In the semiconductor memory integrated circuit, the active level is lowered when the power supply voltage drops below a preset level. A power supply voltage detection circuit for outputting a voltage detection signal and a fifth transistor for turning on / off the gate when receiving the voltage detection signal, and when the voltage detection signal is at an active level, the reference voltage is A semiconductor memory integrated circuit, wherein an output voltage of the cell information sense circuit is set to a level biased to an off cell information side. 2. The reference information output section is a circuit for outputting information corresponding to on-cell information in the binary information, and the output voltage of the reference information sense circuit in the reference voltage generating circuit is level-shifted to obtain the reference voltage. The circuit portion obtained is connected to the gate and the drain of the fourth transistor,
A sixth transistor of the opposite conductivity type that forms a current mirror circuit with the transistor of FIG. 6 and transmits a current corresponding to the current flowing in the fourth transistor, and a current corresponding to the current transmitted by the sixth transistor. A seventh transistor of one conductivity type; and an eighth transistor of the opposite conductivity type, the source of which receives a power supply voltage and the gate and drain of which are connected to the drain of the seventh transistor. A circuit for outputting the reference voltage from the drain, a fifth transistor of reverse conductivity type is supplied to the source of the power supply voltage, and when the voltage detection signal is at the active level, the supply end of the power supply voltage and the reference voltage 2. The semiconductor memory integrated circuit according to claim 1, wherein the impedance between the output terminal and the output terminal is reduced. 3. A ninth transistor of reverse conductivity type is provided, the source of which is connected to the drain of the fifth transistor and the gate and drain of which are connected to the gate and drain of the eighth transistor (the output terminal of the reference voltage). Item 2. A semiconductor memory integrated circuit according to item 2. 4. A plurality of power supply voltage detection circuits, each of which outputs a voltage detection signal that becomes an active level when the power supply voltage is preset and drops below a plurality of different levels, and a gate is provided with the plurality of power supply voltage detection circuits. 2. The semiconductor memory integrated circuit according to claim 1, further comprising a plurality of fifth transistors that respectively receive the voltage detection signals of 1.