JP2901481B2 - Semiconductor memory integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory integrated circuit, and more particularly to a semiconductor memory integrated circuit having a current detection type cell information sense circuit which operates at high speed with a CMOS type inverter and a transistor receiving its output at its gate. About.

[0002]

2. Description of the Related Art In an EPROM type semiconductor memory integrated circuit using a MOS transistor having a floating gate as a memory cell, a threshold voltage is controlled by injection of electric charge into the floating gate and the like, and binary information is stored. When the threshold voltage is high, the control gate is turned off when a voltage for reading is supplied to the control gate, and the flowing current is extremely small. When the threshold voltage is low, the state is turned on when the voltage for reading is supplied, and the resistance value becomes low. The low flowing current increases. Therefore, by supplying the power supply voltage to the storage information read point of the memory cell through the resistance element, the power supply voltage level is read in the off state, and the divided level information is read out by the resistance element and the memory cell in the on state. You.

However, since a large number of memory cells are connected to one bit line from which information is read, and the added capacitance is large, the bit line between the power supply voltage level and the voltage division level of the resistance element and the memory cell is switched. If the voltage is changed, the charge / discharge time becomes long, and high-speed operation cannot be obtained. In addition, power consumption due to charging and discharging also increases. Therefore, there is provided an inverter receiving the level of the selected bit line at the input terminal, and a transistor receiving the output of the inverter at the gate,
A current detection type cell information sense circuit that supplies a bias voltage with almost no level change to the selected bit line and obtains an output having a large difference between read voltages of memory cells in an on state and an off state is often used. (See, for example, Japanese Patent Publication No. 3-27998,
No. 117397, JP-A-4-67500).

The output voltage of the cell information sense circuit is compared with a reference voltage corresponding to an intermediate level of the binary information in a comparison circuit, and information on the on state and off state of the memory cell (hereinafter, on cell information, off cell (Referred to as information).

As a method of generating the above-mentioned reference voltage,
A reference cell section having a dummy cell that generates a current at a level intermediate between the level of the on-cell information and the level of the off-cell information is provided, and the current of the dummy cell is detected by a reference cell information sense circuit having the same circuit configuration as the cell information sense circuit. And a method of generating a reference voltage having a level corresponding to the detected current (for example, see Japanese Patent Publication No. 3-27998).
A reference cell unit including a dummy cell for storing one of the off-cell information (for example, on-cell information) is provided, and the current of the dummy cell is detected by a reference cell information sense circuit having the same circuit configuration as the cell information sense circuit. And a method of generating a voltage having a level corresponding to the reference voltage and shifting the voltage to a reference voltage (for example, an 8-Mbit EPR manufactured by our company).
OM. μPD27C8000).

In the former method, it is necessary to form the dummy cell in a size different from that of a normal memory cell, but the circuit configuration is simplified. In the latter method, the circuit configuration is slightly complicated, but the dummy cells can be formed with the same dimensions and the same structure as ordinary memory cells.

FIG. 6 is a circuit diagram showing an example of a semiconductor memory integrated circuit employing the latter method.

This semiconductor memory integrated circuit has a plurality of memory cells MC (see FIG. 1) which are arranged in a row and column matrix and store binary information of on-cell information and off-cell information corresponding to the magnitude of a current value in a selected state. 6 shows only one),
A plurality of word lines (only one is shown in FIG. 6) for selecting the plurality of memory cells MC on a row-by-row basis, and information read from the selected memory cells of each column of the plurality of memory cells MC are A plurality of bit lines BL to be transmitted (FIG. 6
(Only one is shown), a column selection circuit 2 for selecting one (one column) of a plurality of bit lines BL (columns), and a memory cell array 1 A CMOS type inverter IV1, which receives at its input terminal information read from the memory cell MC (in a selected state) of the row and column selected by the word line WL and the column selection circuit 2 and inverts the signal level of this information, Is connected to the input terminal of the inverter IV1 and the gate of the inverter IV1 is connected to the gate.
N-channel transistor Q3 receiving the output signal of 1
3. The source is the power supply voltage Vcc and the gate is the inverter IV.
1 output signals and the drain of the transistor Q
33, a P-channel transistor Q34 connected to the drain of the transistor 33, and a P-channel transistor Q35 receiving the power supply voltage Vcc at the source and connecting the gate and the drain to the drain of the transistor Q33. And the voltage of the corresponding level (V
mc) from the gate and the drain of the transistor Q35, a cell information sensing circuit 3, a dummy cell DMC for storing on-cell information, and a transistor Q41 having the same characteristics as the transistor Q21 of the column selection circuit 2, and a reference cell section for outputting on-cell information. 4 and an inverter IV2, transistors Q513, Q514, and Q515.
A reference cell information sense circuit 51 which outputs a voltage (Vdmc) of a level corresponding to the information from the gate and the drain of the transistor Q515, and sets the gate to the transistor Q5.
15 connected to the gate and drain, and the source
Receiving cc, a current mirror circuit is formed together with transistor Q515, a P-channel transistor Q51 transmitting a current of a level corresponding to the current flowing through transistor Q515, a drain and a gate are connected, and the drain is transmitted from transistor Q51 to the drain. An N-channel type transistor Q52 receiving the applied current, the gate is connected to the gate and the drain of the transistor Q52, and the drain is commonly connected to form a current mirror circuit together with the transistor Q52, corresponding to the current transmitted from the transistor Q51. N-channel type transistors Q54 and Q55 through which a current of a predetermined level flows, the sources are connected to the ground potential point, the gates receive power supply voltage Vcc, and the drains are connected to the sources of transistors Q52, Q54 and Q55, respectively. N-channel type transistors Q53, Q56 and Q57 for level shifting, P-channel type transistors for level shifting which receive power supply voltage Vcc at the source and connect the gate to the ground potential point and the drain to the drains of transistors Q54 and Q55, respectively Q58 and a level-shifting P-channel transistor Q which receives the power supply voltage Vcc at its source and connects its gate and drain to the drains of the transistors Q54 and Q55.
59, Q60, and Q61, corresponding to an intermediate level between the levels of binary information (on-cell information and off-cell information) stored in the memory cell MC by level-shifting the output voltage (Vdmc) of the reference cell information sense circuit 51. Reference voltage V
The reference voltage generator 5b that outputs r from the gates and drains of the transistors Q59, Q60, and Q61, compares the reference voltage Vr with the output voltage (Vmc) of the cell information sense circuit 3, and outputs the comparison result signal (OUT). And a comparison circuit 6 for outputting.

Next, the operation of the semiconductor memory integrated circuit will be described with reference to FIG.

First, the case where on-cell information is stored in memory cell MC will be described. This memory cell M
When C is selected, a current flows through the memory cell MC, and the level at the input terminal of the inverter IV1 decreases. As a result, the output level of inverter IV1 rises, the on-resistance of transistors Q33 and Q34 decreases, and bit line B
The level of L and the input terminal of the inverter IV1 rises.
When this level becomes higher than the threshold voltage of inverter IV1, the output level of inverter IV1 decreases and the on-resistance of transistors Q33 and Q34 increases, so that the level of the input terminal (bit line BL) of inverter IV1 turns to inverter IV1. Near the threshold voltage (for example, 1.
5V). The output voltage Vmc (ON) at this time
Is a voltage (for example, 1.8 V) higher than the level of the input terminal of the inverter IV1 by the voltage drop of the transistor Q33.
Becomes

On the other hand, when off-cell information is stored in memory cell MC and this memory cell MC is in a selected state,
Since almost no current flows through this memory cell, the level of the input terminal of the inverter IV1 rises and the level of the output terminal decreases, so that the on-resistance of the transistors Q33 and Q34 increases, and the level of the input terminal of the inverter IV1 increases. Drops. When this level falls below the threshold voltage of inverter IV1, the output level of inverter IV1 rises and the on-resistance of transistors Q33 and Q34 decreases, so that the input terminal of inverter IV1 (bit line B
The level L) stabilizes around the threshold voltage of the inverter IV1 (a level slightly higher than that in the case of on-cell information, for example, 1.52 V). The output voltage Vmc at this time
(OFF) is a state in which the transistors Q33 and Q34 are close to the off state, so that the power supply voltage Vcc (for example, 5.0)
V) minus the threshold voltage of transistor Q35 (eg, 4.8V) (transistor Q35
Is set small in order to maximize the output voltage Vmc (OFF).)

On the other hand, the basic cell information sense circuit 51
Since the on-cell information is stored in the dummy cell DMC, the output voltage Vdmc becomes equal to the output voltage Vmc of the cell information sense circuit 3 when the on-cell information is received from the memory cell array 1. This output voltage Vdmc is transmitted as a current to transistor Q51 by a current mirror circuit including transistors Q515 and Q51, and the current is further transmitted to transistors Q54 and Q5 by a current mirror circuit including transistors Q52, Q54 and Q55.
5 to the transistors Q54 to Q61 connected in series and parallel between the power supply voltage Vcc supply terminal and the ground potential point to divide the power supply voltage Vcc to obtain a reference voltage Vr obtained by level-shifting the output voltage Vdmc. It has become.

As described above, the current flowing through the output transistor Q515 of the reference cell information sensing circuit 51 is transferred to the transistor Q515 using the two-stage current mirror circuit.
And an output transistor Q3 of the cell information sense circuit 3.
5, the power supply voltage Vcc fluctuates and the current value of the memory cell (dummy cell) storing on-cell information changes, and the output voltage is changed. Vmc, V
Even if dmc changes, the reference voltage Vr remains at these output voltages Vr.
mc and Vdmc, so that the power supply voltage Vc
A wide range can be accommodated for the variation of c.

[0014]

In the above-described conventional semiconductor memory integrated circuit, the information from the dummy cell DMC for storing the on-cell information is equal to that of the cell information sense circuit 3 for detecting the storage information of the normal memory cell MC. The reference cell information sense circuit 51 having the above structure detects the
Through the current mirror circuit of the stage, the same connection as the output transistor Q35 of the cell information sense circuit 3 and the reference voltage Vr from the transistors Q59 to Q61 of the same conductivity type.
Therefore, it is possible to adapt to the fluctuation of the power supply voltage Vcc in a wide range.

On the other hand, increasing the capacity of a semiconductor memory integrated circuit,
As miniaturization progresses more and more, low voltage and low power consumption of power supplies are indispensable. Although the above-described conventional semiconductor memory integrated circuit can be applied to a wide range of the power supply voltage Vcc, the following problems occur as the power supply voltage decreases.

The cell information sense circuit 3 includes a CMOS inverter IV1 operating at a power supply voltage Vcc. The threshold voltage of the inverter IV1 determines an output voltage Vmc (ON) of on-cell information. And this Vm
c (ON) and output voltage Vmc (OFF) of off-cell information
Is set to a low value so as to increase the difference from. Therefore, the P-channel transistor L of the inverter IV1
The threshold voltage of Q32 is set to a large value, and when the power supply voltage Vcc decreases, the output voltage of the inverter IV1 decreases by [Vcc- | Vt (Q32) |] (Vt (Q32) The threshold value of the transistor Q32) and the resistance value of the transistor Q33 increase, and the current flowing through the transistor Q33 decreases, so that the output voltage Vmc (ON) increases.

On the other hand, the output voltage Vdmc of the reference cell information sense circuit 51 also changes equal to the output voltage Vmc (ON), but the P-channel transistors Q35 and Q515
Is the output voltage V corresponding to the off-cell information.
In order to make mc (OFF) a value as close as possible to the power supply voltage Vcc, the transistor Q5 is small and, therefore, a P-channel transistor Q5.
1, the threshold voltages of Q58 to Q62 are also set small,
Since the threshold voltages of N-channel type transistors Q52 to Q57 are also set smaller than those of transistors Q32 and Q512, the output voltages of inverters IV1 and IV2 are affected by the threshold voltages of transistors Q32 and Q512. Even when the power supply voltage Vcc is reached, the reference voltage V
has no effect on the power supply voltage Vcc.
Changes linearly with respect to.

As a result, when the power supply voltage Vcc decreases,
The output voltage Vmc (ON) becomes equal to the reference voltage Vr (power supply voltage V1), and further becomes higher than the reference voltage Vr, so that the read information of the memory cell cannot be detected.

If the reference voltage Vr is biased toward the output voltage Vmc (OFF) from the beginning to solve this problem, the operating amplitude of the comparison circuit 6 at the time of detecting on-cell information increases, and the operating speed increases. Decrease.

An object of the present invention is to provide a semiconductor memory integrated circuit capable of expanding a low power supply voltage operation range without lowering the operation speed.

[0021]

According to the present invention, there is provided a semiconductor memory integrated circuit in which a plurality of memory cells storing binary information of on-cell information and off-cell information corresponding to the magnitude of a current value in a selected state are arranged. CMOS for inverting and reading the memory cell array portion of the information stored in the memory cells of the selected state, in response to information read from the memory cell array portion in operation is input at a predetermined power supply voltage to the signal level of the information
And a source connected to the input of the inverter, and an output signal of the first inverter being gated.
Into a first transistor of one conductivity type for receiving, and a second transistor of opposite conductivity type connecting the gate and drain receiving said power supply voltage to the source and drain of the first transistor, the selection state A cell information sense circuit for outputting a voltage at a level corresponding to information from a memory cell from a gate and a drain of the second transistor
When the reference cell section which outputs one and the corresponding information in the binary information stored in the memory cell array portion,
A second inverter corresponding to the first inverter;
A third transistor corresponding to the first transistor
And a fourth transistor corresponding to the second transistor.
A cell information sensing circuit.
It has the same configuration as the road, and is paired with information from the reference cell section.
A corresponding level of voltage is applied to the gate of the fourth transistor.
And a reference cell information sense circuit that outputs from the drain,
A reference voltage generator for level-shifting the output voltage of the reference cell information sense circuit and outputting a reference voltage corresponding to an intermediate level between the levels of the binary information stored in the memory cell array unit; comparing the output voltage of the cell information sensing circuit, placed in a semiconductor memory integrated circuit having a comparator circuit for outputting a signal of the comparison result
Te, a power supply voltage detection circuitry that the power supply voltage to output a voltage detection signal which becomes an active level when drops below a preset level, on receiving the voltage detection signal to a gate, and a fifth transistor that is turned off The reference voltage when the voltage detection signal is at an active level ,
When the voltage detection signal is at a non-active level,
Configuration der which was set to be OFF cell information side skewed level of the output voltage of the cell information sensing circuit the reference voltage
You.

Also, the semiconductor memory integrated circuit of the present invention
The reference cell section, a circuit for outputting a corresponding information and the ON cell information of binary information, obtain the reference voltage and the level shifted output voltage of the reference cell information sensing circuit in the reference voltage generating circuit transmitting circuit section, the gate connected to the gate and drain of the <br/> fourth transistor to form a current mirror circuit together with the fourth transistor a current corresponding to the current flowing in the fourth transistor A sixth transistor of a reverse conductivity type;
A seventh transistor of one conductivity type, which flows a current corresponding to the current transmitted by the transistor, and an eighth transistor of the opposite conductivity type, which receives a power supply voltage at the source and connects the gate and the drain to the drain of the seventh transistor. A circuit for outputting the reference voltage from the gate and the drain of the eighth transistor, the fifth transistor being of a reverse conductivity type, supplying the power supply voltage to its source, and the voltage detection signal being an active level. In this case, the impedance between the supply terminal of the power supply voltage and the output terminal of the reference voltage is reduced.

Further, a plurality of power supply voltage detection circuits for outputting voltage detection signals which become active when the power supply voltage falls below a plurality of preset levels different from each other, respectively, are provided, and a gate is provided from the plurality of power supply voltage detection circuits. And a plurality of fifth transistors receiving the voltage detection signals correspondingly.

[0024]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment differs from the conventional semiconductor memory integrated circuit shown in FIG. 6 in that a voltage detection signal DV which becomes an active level (low level) when the power supply voltage Vcc falls below a preset voltage is used. A power-supply voltage detection circuit 7 for output, a P-channel transistor Q63 in a reference voltage generation circuit 5b which is turned on / off by receiving a power supply voltage Vcc at a source and a voltage detection signal DV at a gate;
The source is connected to the drain of the transistor Q63, and the gate and the drain are connected to the reference voltage Vr output terminal (transistor Q5
9 to Q61) and a P-channel transistor Q62 connected to the reference voltage generating circuit 5. The transistor Q63 is turned on when the voltage detection signal DV is at the active level, and the reference voltage Vr is set to the output voltage. The point is that the level is biased toward the off-cell information side of Vmc.

Next, the operation of this embodiment will be described.
FIG. 2 shows a power supply voltage Vc for explaining the operation of this embodiment.
6 is a characteristic diagram of a reference voltage Vr and an output voltage Vmc of the cell information sense circuit 3 with respect to c.

The power supply voltage detecting circuit 7 supplies the power supply voltage Vcc to a preset voltage V2 (for example, the output voltage Vmc (O
When N) is higher than the power supply voltage at which the voltage starts to rise, for example, 3.6 V), the voltage detection signal DV is kept at a high level inactive level. Therefore, the transistor Q63 is turned off, and has the same circuit configuration as the conventional example shown in FIG.
The reference voltage Vr at this time is, for example, 5.0 V for the power supply voltage Vcc, 1.8 V for the output voltage Vmc (ON), and Vmc for the output voltage Vmc (ON).
When (OFF) is 4.8 V, the transistors Q54,
The combined resistance of Q55, the combined resistance of transistors Q56 and Q57, and the combined resistance of transistors Q59 to Q61 are, for example, 1 KΩ, respectively, and Vmc (ON) and Vmc (OF
F) is set to an intermediate value of 3.3V.

When the power supply voltage Vcc falls below the voltage V2 (3.6 V), the voltage detection signal DV goes to a low active level to turn on the transistor Q63, and the series circuit of the transistors Q62 and Q63 is connected to the transistor Q62.
The circuit configuration is further connected in parallel to the parallel circuits 58 to Q61. As a result, the reference voltage Vr becomes the power supply voltage Vcc side,
That is, the level is biased toward the output voltage Vmc (OFF) side, and the information of the memory cell cannot be detected when the power supply voltage Vcc is equal to or lower than V1. Assuming that V1 is, for example, 3.0V, the voltage at which the extension of the reference voltage Vr intersects with Vmc (ON) is 2.0V. Here, the transistor Q6
Assuming that the combined resistance of Q2 and Q63 is, for example, 0.8 KΩ, the reference voltage Vr when the power supply voltage Vcc is 3.0 V is 2.4.
It becomes 5V. When the power supply voltage Vcc further decreases, the reference voltage Vr crosses the output voltage Vmc (ON). If the output voltage Vmc (ON) at this time is about 2.1 V, the power supply voltage Vcc at the intersection becomes 2.57 V. That is, the low voltage side of the power supply voltage Vcc can be expanded to about 2.6 to 2.7 V.

In this embodiment, the range in which the reference voltage Vr is biased toward the output voltage Vmc (OFF) is the output voltage Vr.
Since the difference between mc (ON) and the level on the extension of the reference voltage Vr is in a small range, the operating speed of the comparison circuit 6 in this range does not decrease.

As the specific circuit of the power supply voltage detection circuit 7, the most basic example shown in FIG. 3 utilizing the constant voltage characteristic of a diode, or the circuit is simplified utilizing the resistance change characteristic of a depletion type transistor. FIGS. 4 (A) and (B)
Examples are given.

In this embodiment, the bias of the reference voltage Vr in the low power supply voltage range is determined by the transistors Q62 and Q62.
Q63 is realized by the series circuit,
3 can be directly connected to the output terminal of the reference voltage Vr, and can be realized only by the transistor Q63.

FIG. 5 is a circuit diagram of a reference voltage generating portion according to a second embodiment of the present invention.

This embodiment uses two power supply voltage detecting circuits 7
a, 7b and transistors Q62 to Q65 to switch the reference voltage Vr in two stages, reduce the difference voltage between the output voltage Vmc (ON) and the reference voltage Vr at this switching point, and compare the reference voltage Vr with a low power supply voltage. The operation speed is increased, and the low voltage side of the power supply voltage Vcc is further expanded.

In this embodiment, the reference voltage V
Although the number of switching stages of r is two, the number of switching stages can be further increased.

[0036]

As described above, according to the present invention, a power supply voltage detection circuit for outputting a voltage detection signal which becomes an active level when a power supply voltage falls below a predetermined level, and a power supply voltage detection circuit which is turned on in response to the voltage detection signal. , A transistor to turn off, and when the voltage detection signal is at the active level,
By switching the reference voltage serving as a reference for comparing the level of the binary information read from the memory cell, the CMO included in the cell information sense circuit can be operated during low power supply voltage operation.
Due to the characteristics of the S-type inverter, when the output voltage corresponding to the on-cell information of the binary information read from the memory cell is biased toward the output voltage corresponding to the off-cell information, the reference voltage is also shifted to the output voltage corresponding to the off-cell information. Since the switching is biased, there is an effect that the low power supply voltage operation range can be expanded without increasing the difference between the reference voltage and the output voltage corresponding to the on-cell information, that is, without lowering the operation speed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a characteristic diagram of a reference voltage and a memory cell read information voltage with respect to a power supply voltage for explaining an operation of the embodiment shown in FIG. 1;

FIG. 3 is a circuit diagram showing a first specific example of the power supply voltage detection circuit of the embodiment shown in FIG.

FIG. 4 is a circuit diagram showing a second specific example of the power supply voltage detection circuit of the embodiment shown in FIG. 1, and a power supply voltage characteristic diagram of the circuit element;

FIG. 5 is a circuit diagram of a reference voltage generating portion according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing an example of a conventional semiconductor memory integrated circuit.

7 is a characteristic diagram of a reference voltage and a memory cell read information voltage with respect to a power supply voltage for explaining an operation and a problem of the semiconductor memory integrated circuit shown in FIG. 6;

[Explanation of symbols]

Reference Signs List 1 memory cell array 2 column selection circuit 3 cell information sense circuit 4 reference cell section 5, 5a, 5b reference voltage generation circuit 6 comparison circuit 7, 7a, 7b power supply voltage detection circuit 51 reference cell information detection circuit DMC dummy cell IV1, IV2 inverter MC Memory cells Q21, Q31-Q35, Q41, Q51-Q65, Q
511-Q515 transistor

Claims (4)

(57) [Claims] 1. A current value of the magnitude and the corresponding on-cell information, reading the memory information stored in the memory cells of the selected binary information by arranging a plurality of memory cells to be stored off-cell information when the selected state A cell array unit , a CMOS-type first inverter which operates at a predetermined power supply voltage and receives an information read from the memory cell array unit at an input terminal and inverts a signal level of the information, and a source connected to the input terminal of the inverter connected to, said first transistor of one conductivity type output signal of the first inverter receiving the gate, opposite conductivity type which connects the receiving gate and the drain to the source of the power supply voltage to the drain of said first transistor and a second transistor, the information and corresponding said level of the voltage to be second from the memory cells in the selected state
A cell information sense circuit that outputs from the gate and drain of the transistor, a reference cell unit that outputs information corresponding to one of binary information stored in the memory cell array unit, and a first inverter that corresponds to the first inverter. A second inverter,
A third transistor corresponding to the first transistor
And a fourth transistor corresponding to the second transistor.
A cell information sensing circuit.
It has the same configuration as the road, and is paired with information from the reference cell section.
A corresponding level of voltage is applied to the gate of the fourth transistor.
And a reference cell information sense circuit that outputs from the drain,
A reference voltage generator for level-shifting the output voltage of the reference cell information sense circuit and outputting a reference voltage corresponding to an intermediate level between the levels of the binary information stored in the memory cell array unit; comparing the output voltage of the cell information sensing circuit, the active level when the Oite a semiconductor memory integrated circuit having a comparator circuit for outputting a signal of the comparison result, the power supply voltage drops below a preset level on receiving a power supply voltage detection circuitry that outputs a voltage detection signal, the voltage detection signal to the gate, a fifth turning off
The criteria for the to and a transistor, the voltage detection signal is active level
The voltage when the voltage detection signal is at a non-active level.
Wherein the level of the output voltage of the cell information sense circuit is biased toward the off-cell information side from the reference voltage at the time of the operation. 2. The method according to claim 1, wherein the reference cell section is a circuit for outputting information corresponding to on-cell information of binary information, and the output voltage of the reference cell information sense circuit in the reference voltage generation circuit is level-shifted. transmitting a circuit portion for obtaining the reference voltage, and a gate connected to the gate and drain of said fourth transistor to form a current mirror circuit together with the fourth transistor a current corresponding to the current flowing in the fourth transistor A sixth transistor of the opposite conductivity type, a seventh transistor of one conductivity type for passing a current corresponding to the current transmitted by the sixth transistor, and a gate and a drain which receive the power supply voltage at the source and are connected to the seventh transistor. An eighth transistor of the opposite conductivity type connected to the drain of the eighth transistor, and the gate and the drain of the eighth transistor A circuit for outputting the reference voltage, a fifth transistor having a reverse conductivity type for supplying the power supply voltage to a source thereof, and a supply terminal for the power supply voltage and an output terminal for the reference voltage when a voltage detection signal is at an active level. 2. The semiconductor memory integrated circuit according to claim 1, wherein the impedance between the two is reduced. 3. A ninth transistor of a reverse conductivity type having a source connected to the drain of the fifth transistor and a gate and drain connected to the gate and drain (output terminal of the reference voltage) of the eighth transistor. Item 3. A semiconductor memory integrated circuit according to item 2. 4. A plurality of power supply voltage detection circuits each outputting a voltage detection signal which becomes an active level when the power supply voltage falls below a plurality of preset levels different from each other, and a gate is provided from these plurality of power supply voltage detection circuits. 2. The semiconductor memory integrated circuit according to claim 1, further comprising a plurality of fifth transistors receiving the voltage detection signals correspondingly.