JPH07234264A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable a normal burn-in test to be conducted, even if noises are superimposed on clock signals, for a semiconductor integrated circuit such as an SDRAM which is designed so that information signals supplied from the outside are sampled in synchronization with the clock signals supplied from the outside. CONSTITUTION:During normal operation, a differential amplifier circuit 31 which sets an H-level threshold VIH to l.7V and an L-level thresohld VIL, to 1.3V for clock signals CLK is used as an input circuit; during a burn-in test, a NOR circuit 41 which sets the H-level threshold VIH to 2.2V and the L-level threshold VIL to 0.8V for the clock signals CLK so as to be more resistant to noise than the differential amplifier circuit 31 is used as an input circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit configured to capture an information signal supplied from the outside in synchronization with a clock signal supplied from the outside.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor integrated circuit of this type,
For example, SDRAM (Synchronous Dynamic Random)
Access Memory) is known, and FIG. 8 shows a part thereof.

[0003] In FIG. 8, ₁ 1 to 1 _{m + 1} is an external terminal (not shown external terminal 1 ₈ to 1 _m-1), 1 ₁ a clock signal input terminal to which the clock signal CLK is supplied, 1 ₂ is a chip select signal input terminal to which the chip select signal / CS is supplied.

[0004] 1 ₃ row address strobe signal input terminal to which a row address strobe signal / RAS is supplied, 1 ₄ column address strobe signal / C
This is a column address / strobe signal input terminal to which AS is input.

Reference numeral ₁₅ is a write enable signal / W
Write enable signal input terminal to which E is supplied, ₁₆
Is an output mask signal input terminal to which the output mask signal DQM is supplied.

Further, 1 ₇ is an address signal input terminal to which the most significant bit address signal A _n is supplied, 1 _m is an address signal input terminal to which the least significant bit address signal A ₁ is supplied, and 1 _{m + 1} is Reference voltage VREF, for example 1.65V
Is a reference voltage input terminal to which is supplied.

2 ₁ to 2 _m are input circuits (input circuit 2 ₈
~ 2 _m-1 is not shown) 3 _{1 to} 3 _m-1 are input circuits 2 ₂ to 2
A latch circuit (latch circuits 3 _{7 to} 3 _m-2 are not shown) that latches the signal output from _m in synchronization with the rising timing of the clock signal CLK output from the input circuit 2 ₁ .

Here, the input circuits 2 ₁ to 2 _m have the same circuit configuration. If the input circuit 2 ₁ is shown as a representative, FIG.
It is configured as shown in.

In FIG. 9, 4 is a differential amplifier circuit, and 5 is a VCC power supply line for supplying a power supply voltage VCC, for example, 3.3V.

Further, 6 and 7 are p-channel MIS (metal insulator) which constitutes a load current mirror circuit.
enhancement type p-channel MOS (metal oxide semiconduc) which is a type of semiconductor transistor.
tor) transistor (hereinafter referred to as pMOS transistor).

Further, 8 and 9 are enhancement type n-channel MOS transistors (hereinafter referred to as nMO) which are driving transistors which are a kind of n-channel MIS transistors.
S transistor).

Further, 10 is a differential amplifier activation signal φ _E
Conduction (hereinafter referred to as ON), non-conduction (hereinafter referred to as OF)
Enhancement type nMOS in which F) is controlled
It is a transistor.

Further, 11 and 12 are enhancement type pMOS transistors whose ON and OFF are controlled by a differential amplifier circuit activation signal φ _E , 13 to 15 are waveform shaping inverters, and an output terminal of the inverter 15 is , Latch circuits 3 _{1 to} 3 _m−1 are connected to clock signal input terminals.

The differential amplifier circuit 4 has a high level (hereinafter referred to as H level or "H") threshold (threshold voltage) V _IH = 1.7 V and a low level (hereinafter referred to as L level or The threshold value V _IL on the “L” side is 1.3 V.

In the input circuit 2 ₁ , when the differential amplifier activation signal φ _E = “H”, the nMOS transistor 10 = ON and the pMOS transistors 11 and 12 are turned on.
= OFF and the differential amplifier circuit 4 = active state.

When the clock signal CLK = “H”, the nMOS transistor 8 = ON, the nMOS transistor 9 = OFF, and the voltage of the node 16 = “L”.
Becomes

As a result, the output of the inverter 13 =
“H”, output of inverter 14 = “L”, inverter 1
The output of 5 is "H", which is the latch circuit 3 _{1 to} 3 _m-1.
Is supplied to the clock signal input terminal of.

On the other hand, the clock signal CLK =
In the case of “L”, the nMOS transistor 8 = OFF,
The nMOS transistor 9 = ON and the voltage of the node 16 = “H”.

As a result, the output of the inverter 13 =
“L”, output of inverter 14 = “H”, inverter 1
The output of 5 is "L", which is the latch circuit 3 _{1 to} 3 _m-1.
Is supplied to the clock signal input terminal of.

Further, the differential amplifier circuit activation signal φ _E =
When it is set to “L”, the nMOS transistor 10 =
OFF, pMOS transistors 11 and 12 = ON, the differential amplifier circuit 4 = inactive state, and the output of the differential amplifier circuit 4 is fixed at “H”.

[0021]

In such a semiconductor integrated circuit, an operation test under high temperature condition for a certain period of time, so-called burn-in, is performed before shipment in order to remove those containing potential defects. A (burn-in) test is conducted.

In this case, since 100 to 200 semiconductor integrated circuits are mounted on the burn-in test board, that is, a so-called burn-in board, the wiring on the burn-in board becomes long and the rising waveform of the clock signal CLK. And the falling waveform becomes large.

Therefore, if noise is superimposed on the rising waveform or the falling waveform of the clock signal CLK, the latch circuits 3 _{1 to} 3 _m-1 malfunction and the normal burn-in test cannot be performed. There was a point.

In view of the above point, the present invention provides a semiconductor integrated circuit capable of performing a normal burn-in test even when noise is superimposed on the clock signal during the burn-in test. With the goal.

[0025]

FIG. 1 is a diagram for explaining the principle of the present invention and shows a part of an input circuit section. 2 in the figure
Reference numeral 0 is a clock signal input terminal to which a clock signal CLK is externally supplied, and 21 is an information signal input terminal to which an information signal is externally supplied.

Reference numeral 22 is an input circuit for amplifying an externally supplied clock signal CLK, 23 is an input circuit for amplifying an externally supplied information signal, and 24 is an input circuit 23.
A latch circuit for latching the information signal output from the input circuit 22 at the rising or falling timing of the clock signal CLK output from the input circuit 22, 24A is the latch circuit 2
4 is a clock signal input terminal, and 24B is an information signal input terminal of the latch circuit 24.

Further, in the input circuit 22, 25, 26
This is a threshold logic circuit, and the threshold logic circuit 26 sets the threshold V _IH on the H level side higher than the threshold logic circuit 25 and sets the threshold V _IL on the L level side threshold logic circuit 25. It is set to a lower level, is inactive during normal operation, and is active during burn-in test.

Further, 27 selects the clock signal CLK output from the threshold logic circuit 25 in the normal operation, and selects this clock signal CLK from the clock signal input terminal 24A of the latch circuit 24.
To the threshold logic circuit 26 during the burn-in test.
It is a selection circuit that selects the clock signal CLK output from and supplies it to the clock signal input terminal of the latch circuit 24.

[0029]

In the threshold logic circuit 26, the threshold V _IH on the H level side is set higher than that of the threshold logic circuit 25, and the threshold V _IL on the L level side is set lower than that of the threshold logic circuit 25. It is configured to be more resistant to noise than the threshold logic circuit 25. During the burn-in test, the clock signal CLK output from the threshold logic circuit 26 is supplied to the clock signal input terminal 24A of the latch circuit 24.

Therefore, during the burn-in test, even if noise is superimposed on the rising or falling waveform of the clock signal CLK, malfunction is prevented,
A normal burn-in test can be performed.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 2 to 7 by taking the case where the present invention is applied to an SDRAM as an example. In FIG. 2, parts corresponding to those in FIG. 8 are designated by the same reference numerals, and duplicate description thereof will be omitted.

FIG. 2 is a circuit diagram showing a part of an embodiment of the present invention. This embodiment is a conventional SDRAM shown in FIG.
Input circuits 2 ₁ to 2 _m (input circuits 2 ₈ to 2 _m-1 are not shown) and input circuits 30 ₁ to 30 _{m having} different circuit configurations.
(The input circuits 30 ₈ to 30 _m-1 are not shown), and the other parts are configured in the same manner as the conventional SDRAM shown in FIG. Note that φ _T is a test control signal.

The input circuits 30 ₁ to 30 _m have the same circuit configuration, and the input circuit 30 ₁ is representatively shown in FIG.

In FIG. 3, 31 is a differential amplifier circuit, and 32 is
Is a power supply voltage VCC, for example, VCC that supplies 3.3V
Power supply lines 33 and 34 are enhancement type pMOS transistors forming a current mirror circuit which forms a load,
Reference numerals 35 and 36 are enhancement type nMOS transistors which form drive transistors.

37 is a differential amplifier circuit activation signal φ _E
Enhancement type nMOS transistors whose ON and OFF are controlled by, and 38 and 39 are enhancement type pMOS transistors whose ON and OFF are controlled by the differential amplifier circuit activation signal φ _E.

The differential amplifier circuit 31 has a clock signal C.
H level threshold V _IH = 1.7 V with respect to LK,
It is the threshold V _IL = 1.3V the L level side.

Further, 40 is an inverter for inverting the test control signal φ _T , 41 is a NOR circuit, 42 is a VCC power supply line, 43 and 44 are enhancement type pMOS transistors, and 45 and 46 are enhancement type nMOS.
It is a transistor.

The NOR circuit 41 uses the clock signal C
With respect to LK, an H level side threshold (threshold voltage) V _IH = 2.2 V, an L level side threshold V _IL = 0.
It is set to 8V.

Further, 47 is a selection circuit, and 48, 49
Is a NAND circuit, 50 and 51 are inverters, and the output terminal of the inverter 51 is connected to the clock signal input terminals of the latch circuits 3 _{1 to} 3 _m−1 .

In the present embodiment thus constructed, in the normal operation, as shown in FIG. 4, the test control signal φ _T = “L” and the output of the inverter 40 = “H” are fixed.

As a result, in the NOR circuit 41, p
The MOS transistor 43 = OFF and the nMOS transistor 46 = ON, the NOR circuit 41 is deactivated, and its output is fixed at “L”.

In the selection circuit 47, the output of the inverter 40 is fixed to "H", so that the NAND
The circuit 48 operates as an inverter for the output of the differential amplifier circuit 31.

Since the output of the NOR circuit 41 is fixed to "L", the output of the inverter 50 is fixed to "H", and the NAND circuit 49 operates as an inverter for the output of the NAND circuit 48. It will be.

Here, for example, when the differential amplifier circuit activation signal φ _E = “H” is set, in the differential amplifier circuit 31, the nMOS transistor 37 = ON, pMOS.
The transistors 38 and 39 are turned off, and the differential amplifier circuit 31 is activated.

In this case, the clock signal CLK =
In the case of “H”, the nMOS transistor 35 = ON,
The nMOS transistor 36 turns off, and the node 52
Voltage = “L”.

As a result, in the selection circuit 47, NA
The output of the ND circuit 48 = “H”, the output of the NAND circuit 49 = “L”, and the output of the inverter 51 = “H”, which are supplied to the clock signal input terminals of the latch circuits 3 _{1 to} 3 _m−1. .

On the other hand, as shown in FIG. 5, when the clock signal CLK = “L”, in the differential amplifier circuit 31, the nMOS transistor 35 = OFF, the nMOS transistor 36 = ON, and the voltage of the node 52 = It becomes "H".

As a result, in the selection circuit 47, NA
The output of the ND circuit 48 = “L”, the output of the NAND circuit 49 = “H”, and the output of the inverter 51 = “L”, which are supplied to the clock signal input terminals of the latch circuits 3 _{1 to} 3 _m−1. .

Although not shown, when the differential amplifier circuit activation signal φ _E = “L” is set, the nMOS transistor 37 = OFF, the pMOS transistors 38, 3,
9 = ON, the differential amplifier circuit 31 is inactivated, and the voltage of the node 52 is fixed to “H”.

Further, in the present embodiment, during the burn-in test, as shown in FIG. 6, the test control signal φ _T =
“H” and the output of the inverter 40 = “L”.

As a result, in the NOR circuit 41, p
The MOS transistor 43 = ON, the nMOS transistor 46 = OFF, and the NOR circuit 41 receives the pMOS transistor 44 and the nMO with respect to the clock signal CLK.
It operates as a CMOS inverter composed of the S transistor 45.

In the selection circuit 47, the NAND
The output of the circuit 48 is fixed to "H", and the NAND circuit 49
Will operate as an inverter for the output of the NOR circuit 41.

Therefore, for example, the clock signal CLK =
In the case of “H”, in the NOR circuit 41, pMOS transistor 44 = OFF, nMOS transistor 45 =
When turned on, the output of the NOR circuit 41 becomes "L".

As a result, in the selection circuit 47, the output of the inverter 50 = “H”, the output of the NAND circuit 49 =
“L”, the output of the inverter 51 = “H”, and this is supplied to the clock signal input terminals of the latch circuits 3 _{1 to} 3 _m−1 .

On the other hand, as shown in FIG. 7, when the clock signal CLK = “L”, in the NOR circuit 41, the pMOS transistor 44 = ON and the nMOS transistor 45 = OFF, so that the NOR circuit 41 operates. Output = “H”.

As a result, in the selection circuit 47, the output of the inverter 50 = “L”, the output of the NAND circuit 49 =
“H”, the output of the inverter 51 = “L”, and this is supplied to the clock signal input terminals of the latch circuits 3 _{1 to} 3 _m−1 .

As described above, in the present embodiment, in the normal operation, the threshold V _IH on the H level side is 1.7 V and the threshold V _1L on the L level side is 1.7 V with respect to the clock signal CLK. The differential amplifier circuit 31 of 3V is used as an input circuit.

On the other hand, in the burn-in test, the threshold value V _IH on the H level side with respect to the clock signal CLK.
Is 2.2 V and the threshold V _IL on the L level side is 0.8 V,
The NOR circuit 41, which is more resistant to noise than the differential amplifier circuit 31, is used as an input circuit.

Therefore, according to the present embodiment, during the burn-in test, even if noise is superimposed on the rising or falling waveform of the clock signal CLK, malfunction is prevented and a normal burn-in test is performed. You can

Further, in this embodiment, the input circuits 30 _{2 to} 3 3 for information signals such as the chip select signal / CS are used.
Since 0 _m has the same circuit configuration as the input circuit 30 ₁ for the clock signal CLK, malfunction can be prevented and a normal burn-in test can be performed even when noise is superimposed on these information signals. .

[0061]

According to the present invention, in addition to the threshold logic circuit used in the normal operation with respect to the clock signal supplied from the outside, a threshold logic circuit having a structure resistant to noise is provided. During the burn-in test, the clock signal output from the threshold logic circuit configured to be resistant to this noise is supplied to the clock signal input terminal of the latch circuit that latches the information signal supplied from the outside. Even when noise is superimposed on the rising or falling waveform of CLK during the burn-in test, malfunction can be prevented and a normal burn-in test can be performed.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a part of an embodiment of the present invention.

FIG. 3 is a circuit diagram showing an input circuit that amplifies a clock signal supplied from the outside, among the input circuits provided in one embodiment of the present invention.

FIG. 4 is a circuit diagram showing an operation (during normal operation) of an input circuit that amplifies a clock signal supplied from the outside, among input circuits provided in an embodiment of the present invention.

FIG. 5 is a circuit diagram showing an operation (during normal operation) of an input circuit that amplifies a clock signal supplied from the outside, among input circuits provided in an embodiment of the present invention.

FIG. 6 is a circuit diagram showing an operation (during a burn-in test) of an input circuit that amplifies a clock signal supplied from the outside, among input circuits provided in an embodiment of the present invention.

FIG. 7 is a circuit diagram showing an operation (during a burn-in test) of an input circuit that amplifies a clock signal supplied from the outside among the input circuits provided in the embodiment of the present invention.

FIG. 8 is a circuit diagram showing a part of a conventional SDRAM.

FIG. 9 is a circuit diagram showing an input circuit that amplifies a clock signal supplied from the outside, among input circuits provided in a conventional SDRAM.

[Explanation of symbols]

 (FIG. 1) 20 clock signal input terminal 21 information signal input terminal 22, 23 input circuit 24 latch circuit 25, 26 threshold logic circuit 27 selection circuit

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/66 F 7630-4M 21/82 27/04 21/822 8832-4M H01L 21/82 T 27/04 T

Claims (10)

[Claims] 1. A first input circuit for amplifying a clock signal supplied from the outside, a second input circuit for amplifying an information signal supplied from the outside, and a clock output from the first input circuit. In a semiconductor integrated circuit comprising a latch circuit that latches an information signal output from the second input circuit at the timing of rising or falling of a signal, the first input circuit has an input end from the outside. A first threshold logic circuit supplied with the supplied clock signal;
The clock signal supplied from the outside is supplied to the input terminal, the threshold value on the high level side is set higher than that of the first threshold logic circuit, and the threshold value on the low level side is set to the first threshold value. A second threshold logic circuit that is lower than the logic circuit, is inactive during normal operation, and is active during burn-in test, and the clock output from the first threshold logic circuit during normal operation. A signal is selected and supplied to the clock signal input terminal of the latch circuit. During the burn-in test, the clock signal output from the second threshold logic circuit is selected and input to the clock signal input of the latch circuit. A semiconductor integrated circuit, comprising: a selection circuit supplied to an end. 2. The first threshold logic circuit of the first input circuit comprises a differential amplifier circuit in which a current mirror circuit composed of a p-channel MIS transistor is a load and an n-channel MIS transistor is a drive transistor. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is configured as follows. 3. The second threshold logic circuit of the first input circuit is composed of a logic circuit which is activated / deactivated by a control signal and functions as a complementary MIS inverter when activated. The semiconductor integrated circuit according to claim 1 or 2, wherein: 4. The first logic circuit of the second threshold logic circuit of the first input circuit has a source connected to a power supply line for supplying a power supply voltage, and a gate to which the control signal is supplied. A p-channel MIS transistor, a source thereof is connected to the drain of the first p-channel MIS transistor, and a gate thereof is supplied with a clock signal supplied from the outside, and a drain thereof is connected to the second p-channel MIS transistor. A second n-channel MIS transistor connected to the drain of the second p-channel MIS transistor, the source thereof is grounded, and the gate thereof is supplied with the clock signal supplied from the outside.
A second n-channel MIS transistor connected to the drain of the channel MIS transistor, having its source grounded, and having its gate supplied with the control signal;
4. The semiconductor integrated circuit according to claim 3, wherein a connection point between the drain of the p-channel MIS transistor and the drain of the first n-channel MIS transistor is an output terminal. 5. The selection circuit of the first input circuit has a first input end connected to an output end of the first threshold logic circuit of the first input circuit, and a second input end. A first NAND circuit to which a control signal is supplied, a first inverter having an output end connected to an output end of the second threshold logic circuit of the first input circuit, and a first input end. The first N
A second NAND circuit connected to the output terminal of the AND circuit and having a second input terminal connected to the output terminal of the first inverter; and an input terminal connected to the output terminal of the second NAND circuit, 5. The semiconductor integrated circuit according to claim 1, further comprising a second inverter having an output terminal connected to a clock signal input terminal of the latch circuit. 6. The second input circuit supplies a first threshold logic circuit having an input terminal supplied with the information signal supplied from the outside, and an input terminal supplied with the information signal supplied from the outside. The threshold value on the high level side is set higher than that of the first threshold logic circuit, and the threshold value on the low level side is set lower than that of the first threshold logic circuit, and is in an inactive state during normal operation. And is activated during the burn-in test.
Threshold logic circuit and the information signal output from the first threshold logic circuit during normal operation is selected and supplied to the information signal input terminal of the latch circuit, and during the burn-in test the second signal is selected. 4. A selection circuit for selecting an information signal output from a threshold logic circuit and supplying the selected information signal to an information signal input terminal of the latch circuit. 4. The semiconductor integrated circuit according to 4 or 5. 7. The first threshold logic circuit of the second input circuit comprises a differential amplifier circuit in which a current mirror circuit composed of a p-channel MIS transistor is used as a load and an n-channel MIS transistor is used as a drive transistor. 7. The semiconductor integrated circuit according to claim 6, wherein the semiconductor integrated circuit is configured as follows. 8. The second threshold logic circuit of the second input circuit is constituted by a logic circuit whose activation / inactivation is controlled by a control signal and which functions as a CMIS inverter when activated. 8. The semiconductor integrated circuit according to claim 6 or 7. 9. The first logic circuit of the second threshold logic circuit of the second input circuit has a source connected to a power supply line for supplying a power supply voltage and a gate to which the control signal is supplied. And a second p-channel MIS transistor whose source is connected to the drain of the first p-channel MIS transistor and whose gate is supplied with the information signal supplied from the outside, and whose drain is the first p-channel MIS transistor. A first n-channel M connected to the drain of the second p-channel MIS transistor, the source of which is grounded, and the gate of which is supplied with the information signal supplied from the outside.
An IS transistor and a second n-channel MIS transistor having a drain connected to the drain of the second p-channel MIS transistor, a source grounded, and a gate supplied with the control signal are provided. 9. The semiconductor integrated circuit according to claim 8, wherein a connection point between the drain of the channel MIS transistor and the drain of the first n-channel MIS transistor is used as an output terminal. 10. The selection circuit of the second input circuit is the first circuit.
A first NAND circuit having an input end connected to an output end of the first threshold logic circuit of the second input circuit and a control signal supplied to a second input end, and an output end connected to the first NAND circuit. A first inverter connected to the output end of the second threshold logic circuit of the second input circuit; and a first input end connected to the first NA.
The second input end is connected to the output end of the ND circuit and is connected to the first end.
A second NAND circuit connected to the output terminal of the inverter, and a second NAND circuit having an input terminal connected to the output terminal of the second NAND circuit and an output terminal connected to the information signal input terminal of the latch circuit. 10. The semiconductor integrated circuit according to claim 6, wherein the semiconductor integrated circuit comprises an inverter.